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drm/amdgpu: Add C2PMSG_109/126 reg field shift/masks
Add MP0_C2PMSG_109/126 register field shift/masks that are used to identify boot status by driver. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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//MP0_SMN_C2PMSG_103
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#define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
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#define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
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//MP0_SMN_C2PMSG_109
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#define MP0_SMN_C2PMSG_109__CONTENT__SHIFT 0x0
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#define MP0_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL
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//MP0_SMN_C2PMSG_126
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#define MP0_SMN_C2PMSG_126__GPU_ERR_MEM_TRAINING__SHIFT 0x0
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#define MP0_SMN_C2PMSG_126__GPU_ERR_FW_LOAD__SHIFT 0x1
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#define MP0_SMN_C2PMSG_126__GPU_ERR_WAFL_LINK_TRAINING__SHIFT 0x2
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#define MP0_SMN_C2PMSG_126__GPU_ERR_XGMI_LINK_TRAINING__SHIFT 0x3
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#define MP0_SMN_C2PMSG_126__GPU_ERR_USR_CP_LINK_TRAINING__SHIFT 0x4
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#define MP0_SMN_C2PMSG_126__GPU_ERR_USR_DP_LINK_TRAINING__SHIFT 0x5
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#define MP0_SMN_C2PMSG_126__GPU_ERR_HBM_MEM_TEST__SHIFT 0x6
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#define MP0_SMN_C2PMSG_126__GPU_ERR_HBM_BIST_TEST__SHIFT 0x7
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#define MP0_SMN_C2PMSG_126__SOCKET_ID__SHIFT 0x8
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#define MP0_SMN_C2PMSG_126__AID_ID__SHIFT 0xb
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#define MP0_SMN_C2PMSG_126__HBM_ID__SHIFT 0xd
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#define MP0_SMN_C2PMSG_126__BOOT_STATUS__SHIFT 0x1f
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#define MP0_SMN_C2PMSG_126__GPU_ERR_MEM_TRAINING_MASK 0x00000001L
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#define MP0_SMN_C2PMSG_126__GPU_ERR_FW_LOAD_MASK 0x00000002L
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#define MP0_SMN_C2PMSG_126__GPU_ERR_WAFL_LINK_TRAINING_MASK 0x00000004L
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#define MP0_SMN_C2PMSG_126__GPU_ERR_XGMI_LINK_TRAINING_MASK 0x00000008L
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#define MP0_SMN_C2PMSG_126__GPU_ERR_USR_CP_LINK_TRAINING_MASK 0x00000010L
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#define MP0_SMN_C2PMSG_126__GPU_ERR_USR_DP_LINK_TRAINING_MASK 0x00000020L
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#define MP0_SMN_C2PMSG_126__GPU_ERR_HBM_MEM_TEST_MASK 0x00000040L
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#define MP0_SMN_C2PMSG_126__GPU_ERR_HBM_BIST_TEST_MASK 0x00000080L
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#define MP0_SMN_C2PMSG_126__SOCKET_ID_MASK 0x00000700L
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#define MP0_SMN_C2PMSG_126__AID_ID_MASK 0x00001800L
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#define MP0_SMN_C2PMSG_126__HBM_ID_MASK 0x00002000L
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#define MP0_SMN_C2PMSG_126__BOOT_STATUS_MASK 0x80000000L
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//MP0_SMN_IH_CREDIT
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#define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
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#define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
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