From 9891b3df2b4300d24735c1a1822985d2d173aade Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 20 Apr 2023 03:14:54 +0200 Subject: [PATCH 001/118] drm/msm/dpu1: Rename sm8150_dspp_blk to sdm845_dspp_blk SDM845 was the first SoC to include both PCC v4 and GC v1.8. We don't currently support any other blocks but the common config for these two can be reused for a large amount of SoCs. Rename it to indicate the origin of that combo. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/533003/ Link: https://lore.kernel.org/r/20230420-topic-dpu_gc-v1-1-d9d1a5e40917@linaro.org [DB: also applied to new catalog files] Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- 15 files changed, 39 insertions(+), 39 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index b6098141bb9b..18e27f7550e6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -111,13 +111,13 @@ static const struct dpu_lm_cfg sdm845_lm[] = { static const struct dpu_dspp_cfg sdm845_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), }; static const struct dpu_pingpong_cfg sdm845_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index b5f751354267..a654ba8226cd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -118,13 +118,13 @@ static const struct dpu_lm_cfg sm8150_lm[] = { static const struct dpu_dspp_cfg sm8150_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), }; static const struct dpu_pingpong_cfg sm8150_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 8ed2b263c5ea..6dd24bd39a68 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -117,13 +117,13 @@ static const struct dpu_lm_cfg sc8180x_lm[] = { static const struct dpu_dspp_cfg sc8180x_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), }; static const struct dpu_pingpong_cfg sc8180x_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index daebd2170041..6a6d37c1dede 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -119,13 +119,13 @@ static const struct dpu_lm_cfg sm8250_lm[] = { static const struct dpu_dspp_cfg sm8250_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), }; static const struct dpu_pingpong_cfg sm8250_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 67566b07195a..a3124661cb65 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -76,7 +76,7 @@ static const struct dpu_lm_cfg sc7180_lm[] = { static const struct dpu_dspp_cfg sc7180_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), }; static const struct dpu_pingpong_cfg sc7180_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 031fc8dae3c6..04a0dbf96e17 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -56,7 +56,7 @@ static const struct dpu_lm_cfg sm6115_lm[] = { static const struct dpu_dspp_cfg sm6115_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), }; static const struct dpu_pingpong_cfg sm6115_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 06eba23b0236..3262a5232b5a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -85,7 +85,7 @@ static const struct dpu_lm_cfg sm6350_lm[] = { static const struct dpu_dspp_cfg sm6350_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), }; static struct dpu_pingpong_cfg sm6350_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index f2808098af39..06cf48b55f98 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -53,7 +53,7 @@ static const struct dpu_lm_cfg qcm2290_lm[] = { static const struct dpu_dspp_cfg qcm2290_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), }; static const struct dpu_pingpong_cfg qcm2290_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 241fa6746674..a01c7ea43c33 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -57,7 +57,7 @@ static const struct dpu_lm_cfg sm6375_lm[] = { static const struct dpu_dspp_cfg sm6375_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), }; static const struct dpu_pingpong_cfg sm6375_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 8da424eaee6a..8f3bf7964ba0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -117,13 +117,13 @@ static const struct dpu_lm_cfg sm8350_lm[] = { static const struct dpu_dspp_cfg sm8350_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), }; static const struct dpu_pingpong_cfg sm8350_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 900fee410e11..1624e5035a2c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -84,7 +84,7 @@ static const struct dpu_lm_cfg sc7280_lm[] = { static const struct dpu_dspp_cfg sc7280_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), }; static const struct dpu_pingpong_cfg sc7280_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index f6ce6b090f71..1362552027fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -112,13 +112,13 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = { static const struct dpu_dspp_cfg sc8280xp_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), }; static const struct dpu_pingpong_cfg sc8280xp_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 8d13c369213c..c368a216933a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -118,13 +118,13 @@ static const struct dpu_lm_cfg sm8450_lm[] = { static const struct dpu_dspp_cfg sm8450_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), }; static const struct dpu_pingpong_cfg sm8450_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index f17b9a7fee85..22096c1a8287 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -123,13 +123,13 @@ static const struct dpu_lm_cfg sm8550_lm[] = { static const struct dpu_dspp_cfg sm8550_dspp[] = { DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sm8150_dspp_sblk), + &sdm845_dspp_sblk), }; static const struct dpu_pingpong_cfg sm8550_pp[] = { PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 0de507d4d7b7..8d5f83321be2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -448,7 +448,7 @@ static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { .len = 0x90, .version = 0x10007}, }; -static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = { +static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = { .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, .len = 0x90, .version = 0x40000}, }; From 274f161474627646e16ce69a304030ff34d492ff Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 19 May 2023 18:07:34 +0300 Subject: [PATCH 002/118] drm/msm: stop storing the array of CRTCs in struct msm_drm_private The array of CRTC in the struct msm_drm_private duplicates a list of CRTCs in the drm_device. Drop it and use the existing list for CRTC enumeration. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/538068/ Link: https://lore.kernel.org/r/20230519150734.3879916-1-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +- drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 2 +- drivers/gpu/drm/msm/msm_drv.c | 42 ++++++++++++------------ drivers/gpu/drm/msm/msm_drv.h | 2 -- 5 files changed, 24 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index aa8499de1b9f..84403520d245 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -794,7 +794,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) ret = PTR_ERR(crtc); return ret; } - priv->crtcs[priv->num_crtcs++] = crtc; + priv->num_crtcs++; } /* All CRTCs are compatible with all encoders */ diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c index 6e37072ed302..b6201ae5b42e 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -332,7 +332,7 @@ static int modeset_init(struct mdp4_kms *mdp4_kms) goto fail; } - priv->crtcs[priv->num_crtcs++] = crtc; + priv->num_crtcs++; } /* diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c index 323079cfd698..92bf9d949d09 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -497,7 +497,7 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) DRM_DEV_ERROR(dev->dev, "failed to construct crtc %d (%d)\n", i, ret); goto fail; } - priv->crtcs[priv->num_crtcs++] = crtc; + priv->num_crtcs++; } /* diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 891eff8433a9..45d3d14909df 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -155,7 +155,7 @@ static void msm_irq_uninstall(struct drm_device *dev) struct msm_vblank_work { struct work_struct work; - int crtc_id; + struct drm_crtc *crtc; bool enable; struct msm_drm_private *priv; }; @@ -168,15 +168,15 @@ static void vblank_ctrl_worker(struct work_struct *work) struct msm_kms *kms = priv->kms; if (vbl_work->enable) - kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); + kms->funcs->enable_vblank(kms, vbl_work->crtc); else - kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); + kms->funcs->disable_vblank(kms, vbl_work->crtc); kfree(vbl_work); } static int vblank_ctrl_queue_work(struct msm_drm_private *priv, - int crtc_id, bool enable) + struct drm_crtc *crtc, bool enable) { struct msm_vblank_work *vbl_work; @@ -186,7 +186,7 @@ static int vblank_ctrl_queue_work(struct msm_drm_private *priv, INIT_WORK(&vbl_work->work, vblank_ctrl_worker); - vbl_work->crtc_id = crtc_id; + vbl_work->crtc = crtc; vbl_work->enable = enable; vbl_work->priv = priv; @@ -407,7 +407,8 @@ static int msm_drm_init(struct device *dev, const struct drm_driver *drv) struct msm_drm_private *priv = dev_get_drvdata(dev); struct drm_device *ddev; struct msm_kms *kms; - int ret, i; + struct drm_crtc *crtc; + int ret; if (drm_firmware_drivers_only()) return -ENODEV; @@ -494,20 +495,21 @@ static int msm_drm_init(struct device *dev, const struct drm_driver *drv) ddev->mode_config.funcs = &mode_config_funcs; ddev->mode_config.helper_private = &mode_config_helper_funcs; - for (i = 0; i < priv->num_crtcs; i++) { + drm_for_each_crtc(crtc, ddev) { + struct msm_drm_thread *ev_thread; + /* initialize event thread */ - priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id; - priv->event_thread[i].dev = ddev; - priv->event_thread[i].worker = kthread_create_worker(0, - "crtc_event:%d", priv->event_thread[i].crtc_id); - if (IS_ERR(priv->event_thread[i].worker)) { - ret = PTR_ERR(priv->event_thread[i].worker); + ev_thread = &priv->event_thread[drm_crtc_index(crtc)]; + ev_thread->dev = ddev; + ev_thread->worker = kthread_create_worker(0, "crtc_event:%d", crtc->base.id); + if (IS_ERR(ev_thread->worker)) { + ret = PTR_ERR(ev_thread->worker); DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n"); - priv->event_thread[i].worker = NULL; + ev_thread->worker = NULL; goto err_msm_uninit; } - sched_set_fifo(priv->event_thread[i].worker->task); + sched_set_fifo(ev_thread->worker->task); } ret = drm_vblank_init(ddev, priv->num_crtcs); @@ -639,25 +641,23 @@ static void msm_postclose(struct drm_device *dev, struct drm_file *file) int msm_crtc_enable_vblank(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; struct msm_drm_private *priv = dev->dev_private; struct msm_kms *kms = priv->kms; if (!kms) return -ENXIO; - drm_dbg_vbl(dev, "crtc=%u", pipe); - return vblank_ctrl_queue_work(priv, pipe, true); + drm_dbg_vbl(dev, "crtc=%u", crtc->base.id); + return vblank_ctrl_queue_work(priv, crtc, true); } void msm_crtc_disable_vblank(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; struct msm_drm_private *priv = dev->dev_private; struct msm_kms *kms = priv->kms; if (!kms) return; - drm_dbg_vbl(dev, "crtc=%u", pipe); - vblank_ctrl_queue_work(priv, pipe, false); + drm_dbg_vbl(dev, "crtc=%u", crtc->base.id); + vblank_ctrl_queue_work(priv, crtc, false); } /* diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index e13a8cbd61c9..5d56ca99c1c5 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -97,7 +97,6 @@ struct msm_display_topology { /* Commit/Event thread specific structure */ struct msm_drm_thread { struct drm_device *dev; - unsigned int crtc_id; struct kthread_worker *worker; }; @@ -198,7 +197,6 @@ struct msm_drm_private { struct workqueue_struct *wq; unsigned int num_crtcs; - struct drm_crtc *crtcs[MAX_CRTCS]; struct msm_drm_thread event_thread[MAX_CRTCS]; From 9ed6141b72c766432c4a5e7ccde78263ab615a67 Mon Sep 17 00:00:00 2001 From: Kuogee Hsieh Date: Thu, 22 Jun 2023 10:24:45 -0700 Subject: [PATCH 003/118] drm/msm/dpu: retrieve DSI DSC struct through priv->dsi[0] Currently struct drm_dsc_config for DSI is populated at display setup during system boot up. This mechanism works fine with embedded display but not for pluggable displays as the struct drm_dsc_config will become stale once external display is unplugged. In preparation of adding support for DP DSC support move storing of DSI DSC struct to atomic_enable() so that same mechanism will work for both embedded display and pluggable displays. Changes in v4: -- fix checkpatch.pl warning Changes in v5: -- delete dpu_encoder_get_dsc_config() from atomic_mode_set Signed-off-by: Kuogee Hsieh Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/543867/ Link: https://lore.kernel.org/r/1687454686-10340-2-git-send-email-quic_khsieh@quicinc.com [DB: fixed commit message] Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 42 +++++++++++++++------ 1 file changed, 30 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 493905a5b63a..5dd52ede2d63 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -543,11 +543,24 @@ bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) return (num_dsc > 0) && (num_dsc > intf_count); } +static struct drm_dsc_config *dpu_encoder_get_dsc_config(struct drm_encoder *drm_enc) +{ + struct msm_drm_private *priv = drm_enc->dev->dev_private; + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); + int index = dpu_enc->disp_info.h_tile_instance[0]; + + if (dpu_enc->disp_info.intf_type == INTF_DSI) + return msm_dsi_get_dsc_config(priv->dsi[index]); + + return NULL; +} + static struct msm_display_topology dpu_encoder_get_topology( struct dpu_encoder_virt *dpu_enc, struct dpu_kms *dpu_kms, struct drm_display_mode *mode, - struct drm_crtc_state *crtc_state) + struct drm_crtc_state *crtc_state, + struct drm_dsc_config *dsc) { struct msm_display_topology topology = {0}; int i, intf_count = 0; @@ -579,7 +592,7 @@ static struct msm_display_topology dpu_encoder_get_topology( topology.num_intf = intf_count; - if (dpu_enc->dsc) { + if (dsc) { /* * In case of Display Stream Compression (DSC), we would use * 2 DSC encoders, 2 layer mixers and 1 interface @@ -605,6 +618,7 @@ static int dpu_encoder_virt_atomic_check( struct drm_display_mode *adj_mode; struct msm_display_topology topology; struct dpu_global_state *global_state; + struct drm_dsc_config *dsc; int i = 0; int ret = 0; @@ -640,7 +654,9 @@ static int dpu_encoder_virt_atomic_check( } } - topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state); + dsc = dpu_encoder_get_dsc_config(drm_enc); + + topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc); /* * Release and Allocate resources on every modeset @@ -1072,14 +1088,12 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) : NULL; - if (dpu_enc->dsc) { - num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, - drm_enc->base.id, DPU_HW_BLK_DSC, - hw_dsc, ARRAY_SIZE(hw_dsc)); - for (i = 0; i < num_dsc; i++) { - dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]); - dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0); - } + num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, + drm_enc->base.id, DPU_HW_BLK_DSC, + hw_dsc, ARRAY_SIZE(hw_dsc)); + for (i = 0; i < num_dsc; i++) { + dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]); + dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0); } dpu_enc->dsc_mask = dsc_mask; @@ -1187,6 +1201,8 @@ static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, dpu_enc = to_dpu_encoder_virt(drm_enc); + dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc); + mutex_lock(&dpu_enc->enc_lock); cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; @@ -2108,8 +2124,10 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) phys_enc->hw_pp->merge_3d->idx); } - if (dpu_enc->dsc) + if (dpu_enc->dsc) { dpu_encoder_unprep_dsc(dpu_enc); + dpu_enc->dsc = NULL; + } intf_cfg.stream_sel = 0; /* Don't care value for video mode */ intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); From cabfe08ca574dd2b5e8458c0ffaa8fdb406185d4 Mon Sep 17 00:00:00 2001 From: Kuogee Hsieh Date: Thu, 22 Jun 2023 10:24:46 -0700 Subject: [PATCH 004/118] drm/msm/dpu: remove struct drm_dsc_config from struct msm_display_info Since struct drm_dsc_config is stored at atomic_enable() instead of display setup time during boot up, saving struct drm_dsc_config at struct msm_display_info is not necessary. Lets drop the dsc member from struct msm_display_info. Changes in v4: -- fix "Since" at commit text Signed-off-by: Kuogee Hsieh Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/543866/ Link: https://lore.kernel.org/r/1687454686-10340-3-git-send-email-quic_khsieh@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 -- 3 files changed, 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 5dd52ede2d63..f0a2a1dca741 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2308,8 +2308,6 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc, dpu_enc->idle_pc_supported = dpu_kms->catalog->caps->has_idle_pc; - dpu_enc->dsc = disp_info->dsc; - mutex_lock(&dpu_enc->enc_lock); for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) { /* diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 90e1925d7770..4c05fd5e9ed1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -28,7 +28,6 @@ * @is_cmd_mode Boolean to indicate if the CMD mode is requested * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is * used instead of panel TE in cmd mode panels - * @dsc: DSC configuration data for DSC-enabled displays */ struct msm_display_info { enum dpu_intf_type intf_type; @@ -36,7 +35,6 @@ struct msm_display_info { uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; bool is_cmd_mode; bool is_te_using_watchdog_timer; - struct drm_dsc_config *dsc; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 84403520d245..2914774c1fd4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -544,8 +544,6 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev, info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]); - info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]); - encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, &info); if (IS_ERR(encoder)) { DPU_ERROR("encoder init failed for dsi display\n"); From 648c40bb7c89d18db637432e3acc29b42897e537 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 23 Jun 2023 14:32:53 +0200 Subject: [PATCH 005/118] dt-bindings: display: msm: sm8350-mdss: document displayport controller subnode Document the optional displayport controller subnode of the SM8350 MDSS. Acked-by: Rob Herring Signed-off-by: Neil Armstrong Reviewed-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/543999/ Link: https://lore.kernel.org/r/20230621-topic-sm8x50-upstream-mdss-bindings-dp-subnode-v2-1-733ed383f6b6@linaro.org Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml index 79a226e4cc6a..f2cbeb435f1b 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml @@ -52,6 +52,12 @@ patternProperties: compatible: const: qcom,sm8350-dpu + "^displayport-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm8350-dp + "^dsi@[0-9a-f]+$": type: object properties: From df64c86e776bd3ee7efe34bcb360e36063723ec0 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 23 Jun 2023 14:32:54 +0200 Subject: [PATCH 006/118] dt-bindings: display: msm: sm8450-mdss: document displayport controller subnode Document the optional displayport controller subnode of the SM8450 MDSS. Acked-by: Rob Herring Signed-off-by: Neil Armstrong Reviewed-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/544000/ Link: https://lore.kernel.org/r/20230621-topic-sm8x50-upstream-mdss-bindings-dp-subnode-v2-2-733ed383f6b6@linaro.org Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml index f26eb5643aed..494e2a080e99 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml @@ -42,6 +42,14 @@ patternProperties: compatible: const: qcom,sm8450-dpu + "^displayport-controller@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm8450-dp + - const: qcom,sm8350-dp + "^dsi@[0-9a-f]+$": type: object properties: From d92ae3612c8470306edddb150c94eacede533f38 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 23 Jun 2023 14:32:55 +0200 Subject: [PATCH 007/118] dt-bindings: display: msm: sm8550-mdss: document displayport controller subnode Document the optional displayport controller subnode of the SM8550 MDSS. Acked-by: Rob Herring Signed-off-by: Neil Armstrong Reviewed-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/544002/ Link: https://lore.kernel.org/r/20230621-topic-sm8x50-upstream-mdss-bindings-dp-subnode-v2-3-733ed383f6b6@linaro.org Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml index 887be33ba108..70ce7cb7a80d 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml @@ -42,6 +42,14 @@ patternProperties: compatible: const: qcom,sm8550-dpu + "^displayport-controller@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm8550-dp + - const: qcom,sm8350-dp + "^dsi@[0-9a-f]+$": type: object properties: From 270ad296e94a09c97c20f2e3be9e868cda640951 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 3 Jul 2023 20:15:56 +0200 Subject: [PATCH 008/118] dt-bindings: display/msm: dsi-controller-main: Allow refgen-supply DSI host needs REFGEN to be enabled (if it's present on a given platform). Allow consuming it. Acked-by: Rob Herring Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/545335/ Link: https://lore.kernel.org/r/20230628-topic-refgen-v3-3-9fbf0e605d23@linaro.org Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 01848bdd5873..76270992305a 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -166,6 +166,10 @@ properties: description: Phandle to vdd regulator device node + refgen-supply: + description: + Phandle to REFGEN regulator device node + vcca-supply: description: Phandle to vdd regulator device node From 21d6ec5fce75ea5a89fef937b9424a11b49e308f Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 3 Jul 2023 20:15:57 +0200 Subject: [PATCH 009/118] drm/msm/dsi: Hook up refgen regulator Consume the refgen supply on configurations that may use it. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545333/ Link: https://lore.kernel.org/r/20230628-topic-refgen-v3-4-9fbf0e605d23@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index 8a5fb6df7210..1f98ff74ceb0 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -160,6 +160,7 @@ static const char * const dsi_v2_4_clk_names[] = { static const struct regulator_bulk_data dsi_v2_4_regulators[] = { { .supply = "vdda", .init_load_uA = 21800 }, /* 1.2 V */ + { .supply = "refgen" }, }; static const struct msm_dsi_config sdm845_dsi_cfg = { @@ -191,6 +192,7 @@ static const struct msm_dsi_config sm8550_dsi_cfg = { static const struct regulator_bulk_data sc7280_dsi_regulators[] = { { .supply = "vdda", .init_load_uA = 8350 }, /* 1.2 V */ + { .supply = "refgen" }, }; static const struct msm_dsi_config sc7280_dsi_cfg = { From 70e913f765f69666c4b781aafe37b85d2140306a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:18 +0300 Subject: [PATCH 010/118] drm/msm: enumerate DSI interfaces Follow the DP example and define MSM_DSI_CONTROLLER_n enumeration. Reviewed-by: Abhinav Kumar Reviewed-by: Marijn Suijten Tested-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545351/ Link: https://lore.kernel.org/r/20230704022136.130522-2-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/msm_drv.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 5d56ca99c1c5..9d9d5e009163 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -65,6 +65,12 @@ enum msm_dp_controller { MSM_DP_CONTROLLER_COUNT, }; +enum msm_dsi_controller { + MSM_DSI_CONTROLLER_0, + MSM_DSI_CONTROLLER_1, + MSM_DSI_CONTROLLER_COUNT, +}; + #define MSM_GPU_MAX_RINGS 4 #define MAX_H_TILES_PER_DISPLAY 2 @@ -116,7 +122,7 @@ struct msm_drm_private { struct hdmi *hdmi; /* DSI is shared by mdp4 and mdp5 */ - struct msm_dsi *dsi[2]; + struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT]; struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; From 2d3b0d74c8a3dd1479b0739cb2f78f84a90785f2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:19 +0300 Subject: [PATCH 011/118] drm/msm/dpu: always use MSM_DP/DSI_CONTROLLER_n In several catalog entries we did not use existing MSM_DP_CONTROLLER_n constants. Fill them in. Also use freshly defined MSM_DSI_CONTROLLER_n for DSI interfaces. Reviewed-by: Marijn Suijten Tested-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545353/ Link: https://lore.kernel.org/r/20230704022136.130522-3-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ++-- 15 files changed, 32 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 7d0d0e74c3b0..be0514bf27ec 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -139,13 +139,13 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = { }; static const struct dpu_intf_cfg msm8998_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 21, INTF_SDM845_MASK, + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 21, INTF_SDM845_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 21, INTF_SDM845_MASK, + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 21, INTF_SDM845_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)), - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 21, INTF_SDM845_MASK, + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 21, INTF_SDM845_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)), INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, INTF_SDM845_MASK, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 18e27f7550e6..894440533455 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -143,16 +143,16 @@ static const struct dpu_dsc_cfg sdm845_dsc[] = { }; static const struct dpu_intf_cfg sdm845_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SDM845_MASK, + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SDM845_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24, INTF_SDM845_MASK, + INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SDM845_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)), - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24, INTF_SDM845_MASK, + INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SDM845_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)), - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SDM845_MASK, + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SDM845_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index a654ba8226cd..9a5ce15df018 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -162,18 +162,18 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = { }; static const struct dpu_intf_cfg sm8150_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, + INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)), - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 6dd24bd39a68..2d8f0640162e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -166,11 +166,11 @@ static const struct dpu_intf_cfg sc8180x_intf[] = { INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK, + INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 6a6d37c1dede..2aa65b82c556 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -163,18 +163,18 @@ static const struct dpu_dsc_cfg sm8250_dsc[] = { }; static const struct dpu_intf_cfg sm8250_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK, + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, 1, 24, INTF_SC7180_MASK, + INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)), - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, + INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index a3124661cb65..74d10dff545c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -92,7 +92,7 @@ static const struct dpu_intf_cfg sc7180_intf[] = { INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 04a0dbf96e17..b17cc8baf678 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -66,7 +66,7 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = { }; static const struct dpu_intf_cfg sm6115_intf[] = { - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 3262a5232b5a..550a660d0f34 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -102,10 +102,10 @@ static const struct dpu_dsc_cfg sm6350_dsc[] = { }; static const struct dpu_intf_cfg sm6350_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 35, INTF_SC7180_MASK, + INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 35, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK, + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 35, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index 06cf48b55f98..ade9c4a5ec4e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -63,7 +63,7 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] = { }; static const struct dpu_intf_cfg qcm2290_intf[] = { - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index a01c7ea43c33..664e45c31a12 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -71,7 +71,7 @@ static const struct dpu_dsc_cfg sm6375_dsc[] = { }; static const struct dpu_intf_cfg sm6375_intf[] = { - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 8f3bf7964ba0..c151f8b9f667 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -169,11 +169,11 @@ static const struct dpu_intf_cfg sm8350_intf[] = { INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)), - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK, + INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 1624e5035a2c..b702bab35707 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -116,7 +116,7 @@ static const struct dpu_intf_cfg sc7280_intf[] = { INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 1362552027fb..d3fa49fe93a6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -161,11 +161,11 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = { INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)), - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, + INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index c368a216933a..d33fdcb7307f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -177,11 +177,11 @@ static const struct dpu_intf_cfg sm8450_intf[] = { INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)), - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, + INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 22096c1a8287..95d3f6479fda 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -181,11 +181,11 @@ static const struct dpu_intf_cfg sm8550_intf[] = { INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, + INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)), - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, + INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK, DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)), From fdac4bc57a4f8bea6725177ea5c4f520b1bf89c2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:20 +0300 Subject: [PATCH 012/118] drm/msm/dpu: simplify peer LM handling For each LM there is at max 1 peer LM. Thus there is no need to have a mask for the peer LM enumeration. Change that to have an ID of the peer LM. Reviewed-by: Marijn Suijten Tested-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545352/ Link: https://lore.kernel.org/r/20230704022136.130522-4-dmitry.baryshkov@linaro.org --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 34 +++++++------------ 3 files changed, 15 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 8d5f83321be2..b4072a329b19 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -394,7 +394,7 @@ static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1); .features = _fmask, \ .sblk = _sblk, \ .pingpong = _pp, \ - .lm_pair_mask = (1 << _lmpair), \ + .lm_pair = _lmpair, \ .dspp = _dspp \ } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index b860784ade72..b07caa4b867e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -554,14 +554,14 @@ struct dpu_sspp_cfg { * @features bit mask identifying sub-blocks/features * @sblk: LM Sub-blocks information * @pingpong: ID of connected PingPong, PINGPONG_NONE if unsupported - * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL + * @lm_pair: ID of LM that can be controlled by same CTL */ struct dpu_lm_cfg { DPU_HW_BLK_INFO; const struct dpu_lm_sub_blks *sblk; u32 pingpong; u32 dspp; - unsigned long lm_pair_mask; + unsigned long lm_pair; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 471842bbb950..e333f4eeafc1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -253,28 +253,19 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top) } /** - * _dpu_rm_check_lm_peer - check if a mixer is a peer of the primary + * _dpu_rm_get_lm_peer - get the id of a mixer which is a peer of the primary * @rm: dpu resource manager handle * @primary_idx: index of primary mixer in rm->mixer_blks[] - * @peer_idx: index of other mixer in rm->mixer_blks[] - * Return: true if rm->mixer_blks[peer_idx] is a peer of - * rm->mixer_blks[primary_idx] */ -static bool _dpu_rm_check_lm_peer(struct dpu_rm *rm, int primary_idx, - int peer_idx) +static int _dpu_rm_get_lm_peer(struct dpu_rm *rm, int primary_idx) { const struct dpu_lm_cfg *prim_lm_cfg; - const struct dpu_lm_cfg *peer_cfg; prim_lm_cfg = to_dpu_hw_mixer(rm->mixer_blks[primary_idx])->cap; - peer_cfg = to_dpu_hw_mixer(rm->mixer_blks[peer_idx])->cap; - if (!test_bit(peer_cfg->id, &prim_lm_cfg->lm_pair_mask)) { - DPU_DEBUG("lm %d not peer of lm %d\n", peer_cfg->id, - peer_cfg->id); - return false; - } - return true; + if (prim_lm_cfg->lm_pair >= LM_0 && prim_lm_cfg->lm_pair < LM_MAX) + return prim_lm_cfg->lm_pair - LM_0; + return -EINVAL; } /** @@ -351,7 +342,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, int lm_idx[MAX_BLOCKS]; int pp_idx[MAX_BLOCKS]; int dspp_idx[MAX_BLOCKS] = {0}; - int i, j, lm_count = 0; + int i, lm_count = 0; if (!reqs->topology.num_lm) { DPU_ERROR("invalid number of lm: %d\n", reqs->topology.num_lm); @@ -376,16 +367,15 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, ++lm_count; /* Valid primary mixer found, find matching peers */ - for (j = i + 1; j < ARRAY_SIZE(rm->mixer_blks) && - lm_count < reqs->topology.num_lm; j++) { - if (!rm->mixer_blks[j]) + if (lm_count < reqs->topology.num_lm) { + int j = _dpu_rm_get_lm_peer(rm, i); + + /* ignore the peer if there is an error or if the peer was already processed */ + if (j < 0 || j < i) continue; - if (!_dpu_rm_check_lm_peer(rm, i, j)) { - DPU_DEBUG("lm %d not peer of lm %d\n", LM_0 + j, - LM_0 + i); + if (!rm->mixer_blks[j]) continue; - } if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, enc_id, j, From 6b2dc8cf67a9769a43b63e902abcbc52de5cd55d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:21 +0300 Subject: [PATCH 013/118] drm/msm/dpu: drop dpu_mdss_cfg::mdp_count field There is always a single MDP TOP block. Drop the mdp_count field and stop declaring dpu_mdp_cfg instances as arrays. Tested-by: Marijn Suijten Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545355/ Link: https://lore.kernel.org/r/20230704022136.130522-5-dmitry.baryshkov@linaro.org --- .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 7 ++-- .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 7 ++-- .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 7 ++-- .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 7 ++-- .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 7 ++-- .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 7 ++-- .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 7 ++-- .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 7 ++-- .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 7 ++-- .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 7 ++-- .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 7 ++-- .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 ++-- .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 7 ++-- .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 7 ++-- .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 7 ++-- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 35 +++---------------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 6 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 3 +- 19 files changed, 40 insertions(+), 110 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index be0514bf27ec..e0d2ee48d733 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -26,8 +26,7 @@ static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = { .highest_bank_bit = 0x2, }; -static const struct dpu_mdp_cfg msm8998_mdp[] = { - { +static const struct dpu_mdp_cfg msm8998_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0x0, .len = 0x458, .features = BIT(DPU_MDP_VSYNC_SEL), @@ -41,7 +40,6 @@ static const struct dpu_mdp_cfg msm8998_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 }, .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 }, - }, }; static const struct dpu_ctl_cfg msm8998_ctl[] = { @@ -192,8 +190,7 @@ static const struct dpu_perf_cfg msm8998_perf_data = { const struct dpu_mdss_cfg dpu_msm8998_cfg = { .caps = &msm8998_dpu_caps, .ubwc = &msm8998_ubwc_cfg, - .mdp_count = ARRAY_SIZE(msm8998_mdp), - .mdp = msm8998_mdp, + .mdp = &msm8998_mdp, .ctl_count = ARRAY_SIZE(msm8998_ctl), .ctl = msm8998_ctl, .sspp_count = ARRAY_SIZE(msm8998_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 894440533455..3dab2b9888f7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -26,8 +26,7 @@ static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = { .highest_bank_bit = 0x2, }; -static const struct dpu_mdp_cfg sdm845_mdp[] = { - { +static const struct dpu_mdp_cfg sdm845_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0x0, .len = 0x45c, .features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL), @@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sdm845_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, - }, }; static const struct dpu_ctl_cfg sdm845_ctl[] = { @@ -196,8 +194,7 @@ static const struct dpu_perf_cfg sdm845_perf_data = { const struct dpu_mdss_cfg dpu_sdm845_cfg = { .caps = &sdm845_dpu_caps, .ubwc = &sdm845_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sdm845_mdp), - .mdp = sdm845_mdp, + .mdp = &sdm845_mdp, .ctl_count = ARRAY_SIZE(sdm845_ctl), .ctl = sdm845_ctl, .sspp_count = ARRAY_SIZE(sdm845_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 9a5ce15df018..ef611f273be2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -26,8 +26,7 @@ static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = { .highest_bank_bit = 0x2, }; -static const struct dpu_mdp_cfg sm8150_mdp[] = { - { +static const struct dpu_mdp_cfg sm8150_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0x0, .len = 0x45c, .features = BIT(DPU_MDP_AUDIO_SELECT), @@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sm8150_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, - }, }; /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ @@ -210,8 +208,7 @@ static const struct dpu_perf_cfg sm8150_perf_data = { const struct dpu_mdss_cfg dpu_sm8150_cfg = { .caps = &sm8150_dpu_caps, .ubwc = &sm8150_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sm8150_mdp), - .mdp = sm8150_mdp, + .mdp = &sm8150_mdp, .ctl_count = ARRAY_SIZE(sm8150_ctl), .ctl = sm8150_ctl, .sspp_count = ARRAY_SIZE(sm8150_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 2d8f0640162e..c52ea510ef6d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -26,8 +26,7 @@ static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = { .highest_bank_bit = 0x3, }; -static const struct dpu_mdp_cfg sc8180x_mdp[] = { - { +static const struct dpu_mdp_cfg sc8180x_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0x0, .len = 0x45c, .features = BIT(DPU_MDP_AUDIO_SELECT), @@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sc8180x_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, - }, }; static const struct dpu_ctl_cfg sc8180x_ctl[] = { @@ -216,8 +214,7 @@ static const struct dpu_perf_cfg sc8180x_perf_data = { const struct dpu_mdss_cfg dpu_sc8180x_cfg = { .caps = &sc8180x_dpu_caps, .ubwc = &sc8180x_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sc8180x_mdp), - .mdp = sc8180x_mdp, + .mdp = &sc8180x_mdp, .ctl_count = ARRAY_SIZE(sc8180x_ctl), .ctl = sc8180x_ctl, .sspp_count = ARRAY_SIZE(sc8180x_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 2aa65b82c556..7b4b3e0abca8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -25,8 +25,7 @@ static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = { .ubwc_swizzle = 0x6, }; -static const struct dpu_mdp_cfg sm8250_mdp[] = { - { +static const struct dpu_mdp_cfg sm8250_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0x0, .len = 0x494, .features = 0, @@ -40,7 +39,6 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, - }, }; /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ @@ -216,8 +214,7 @@ static const struct dpu_perf_cfg sm8250_perf_data = { const struct dpu_mdss_cfg dpu_sm8250_cfg = { .caps = &sm8250_dpu_caps, .ubwc = &sm8250_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sm8250_mdp), - .mdp = sm8250_mdp, + .mdp = &sm8250_mdp, .ctl_count = ARRAY_SIZE(sm8250_ctl), .ctl = sm8250_ctl, .sspp_count = ARRAY_SIZE(sm8250_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 74d10dff545c..0c59c8879aaf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -22,8 +22,7 @@ static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = { .highest_bank_bit = 0x3, }; -static const struct dpu_mdp_cfg sc7180_mdp[] = { - { +static const struct dpu_mdp_cfg sc7180_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0x0, .len = 0x494, .features = 0, @@ -32,7 +31,6 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, - }, }; static const struct dpu_ctl_cfg sc7180_ctl[] = { @@ -134,8 +132,7 @@ static const struct dpu_perf_cfg sc7180_perf_data = { const struct dpu_mdss_cfg dpu_sc7180_cfg = { .caps = &sc7180_dpu_caps, .ubwc = &sc7180_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sc7180_mdp), - .mdp = sc7180_mdp, + .mdp = &sc7180_mdp, .ctl_count = ARRAY_SIZE(sc7180_ctl), .ctl = sc7180_ctl, .sspp_count = ARRAY_SIZE(sc7180_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index b17cc8baf678..917981add93a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -23,14 +23,12 @@ static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = { .ubwc_swizzle = 0x7, }; -static const struct dpu_mdp_cfg sm6115_mdp[] = { - { +static const struct dpu_mdp_cfg sm6115_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0x0, .len = 0x494, .features = 0, .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, - }, }; static const struct dpu_ctl_cfg sm6115_ctl[] = { @@ -104,8 +102,7 @@ static const struct dpu_perf_cfg sm6115_perf_data = { const struct dpu_mdss_cfg dpu_sm6115_cfg = { .caps = &sm6115_dpu_caps, .ubwc = &sm6115_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sm6115_mdp), - .mdp = sm6115_mdp, + .mdp = &sm6115_mdp, .ctl_count = ARRAY_SIZE(sm6115_ctl), .ctl = sm6115_ctl, .sspp_count = ARRAY_SIZE(sm6115_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 550a660d0f34..072261675db0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -25,8 +25,7 @@ static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = { .highest_bank_bit = 1, }; -static const struct dpu_mdp_cfg sm6350_mdp[] = { - { +static const struct dpu_mdp_cfg sm6350_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0x0, .len = 0x494, .features = 0, @@ -35,7 +34,6 @@ static const struct dpu_mdp_cfg sm6350_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, - }, }; static const struct dpu_ctl_cfg sm6350_ctl[] = { @@ -143,8 +141,7 @@ static const struct dpu_perf_cfg sm6350_perf_data = { const struct dpu_mdss_cfg dpu_sm6350_cfg = { .caps = &sm6350_dpu_caps, .ubwc = &sm6350_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sm6350_mdp), - .mdp = sm6350_mdp, + .mdp = &sm6350_mdp, .ctl_count = ARRAY_SIZE(sm6350_ctl), .ctl = sm6350_ctl, .sspp_count = ARRAY_SIZE(sm6350_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index ade9c4a5ec4e..52c7c0f0d364 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -20,14 +20,12 @@ static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = { .highest_bank_bit = 0x2, }; -static const struct dpu_mdp_cfg qcm2290_mdp[] = { - { +static const struct dpu_mdp_cfg qcm2290_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0x0, .len = 0x494, .features = 0, .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, - }, }; static const struct dpu_ctl_cfg qcm2290_ctl[] = { @@ -94,8 +92,7 @@ static const struct dpu_perf_cfg qcm2290_perf_data = { const struct dpu_mdss_cfg dpu_qcm2290_cfg = { .caps = &qcm2290_dpu_caps, .ubwc = &qcm2290_ubwc_cfg, - .mdp_count = ARRAY_SIZE(qcm2290_mdp), - .mdp = qcm2290_mdp, + .mdp = &qcm2290_mdp, .ctl_count = ARRAY_SIZE(qcm2290_ctl), .ctl = qcm2290_ctl, .sspp_count = ARRAY_SIZE(qcm2290_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 664e45c31a12..29ab659e00bf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -24,14 +24,12 @@ static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = { .highest_bank_bit = 1, }; -static const struct dpu_mdp_cfg sm6375_mdp[] = { - { +static const struct dpu_mdp_cfg sm6375_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0x0, .len = 0x494, .features = 0, .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, - }, }; static const struct dpu_ctl_cfg sm6375_ctl[] = { @@ -109,8 +107,7 @@ static const struct dpu_perf_cfg sm6375_perf_data = { const struct dpu_mdss_cfg dpu_sm6375_cfg = { .caps = &sm6375_dpu_caps, .ubwc = &sm6375_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sm6375_mdp), - .mdp = sm6375_mdp, + .mdp = &sm6375_mdp, .ctl_count = ARRAY_SIZE(sm6375_ctl), .ctl = sm6375_ctl, .sspp_count = ARRAY_SIZE(sm6375_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index c151f8b9f667..6392c310e4ea 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -24,8 +24,7 @@ static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = { .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ }; -static const struct dpu_mdp_cfg sm8350_mdp[] = { - { +static const struct dpu_mdp_cfg sm8350_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0x0, .len = 0x494, .features = 0, @@ -38,7 +37,6 @@ static const struct dpu_mdp_cfg sm8350_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, - }, }; /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ @@ -215,8 +213,7 @@ static const struct dpu_perf_cfg sm8350_perf_data = { const struct dpu_mdss_cfg dpu_sm8350_cfg = { .caps = &sm8350_dpu_caps, .ubwc = &sm8350_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sm8350_mdp), - .mdp = sm8350_mdp, + .mdp = &sm8350_mdp, .ctl_count = ARRAY_SIZE(sm8350_ctl), .ctl = sm8350_ctl, .sspp_count = ARRAY_SIZE(sm8350_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index b702bab35707..f975252debd3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -23,8 +23,7 @@ static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = { .ubwc_swizzle = 0x6, }; -static const struct dpu_mdp_cfg sc7280_mdp[] = { - { +static const struct dpu_mdp_cfg sc7280_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0x0, .len = 0x2014, .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, @@ -32,7 +31,6 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, - }, }; static const struct dpu_ctl_cfg sc7280_ctl[] = { @@ -156,8 +154,7 @@ static const struct dpu_perf_cfg sc7280_perf_data = { const struct dpu_mdss_cfg dpu_sc7280_cfg = { .caps = &sc7280_dpu_caps, .ubwc = &sc7280_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sc7280_mdp), - .mdp = sc7280_mdp, + .mdp = &sc7280_mdp, .ctl_count = ARRAY_SIZE(sc7280_ctl), .ctl = sc7280_ctl, .sspp_count = ARRAY_SIZE(sc7280_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index d3fa49fe93a6..e45f9f0955c7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -25,8 +25,7 @@ static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = { .ubwc_swizzle = 6, }; -static const struct dpu_mdp_cfg sc8280xp_mdp[] = { - { +static const struct dpu_mdp_cfg sc8280xp_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0x0, .len = 0x494, .features = BIT(DPU_MDP_PERIPH_0_REMOVED), @@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sc8280xp_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, - }, }; /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ @@ -219,8 +217,7 @@ static const struct dpu_perf_cfg sc8280xp_perf_data = { const struct dpu_mdss_cfg dpu_sc8280xp_cfg = { .caps = &sc8280xp_dpu_caps, .ubwc = &sc8280xp_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sc8280xp_mdp), - .mdp = sc8280xp_mdp, + .mdp = &sc8280xp_mdp, .ctl_count = ARRAY_SIZE(sc8280xp_ctl), .ctl = sc8280xp_ctl, .sspp_count = ARRAY_SIZE(sc8280xp_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index d33fdcb7307f..63ec13342391 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -25,8 +25,7 @@ static const struct dpu_ubwc_cfg sm8450_ubwc_cfg = { .ubwc_swizzle = 0x6, }; -static const struct dpu_mdp_cfg sm8450_mdp[] = { - { +static const struct dpu_mdp_cfg sm8450_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0x0, .len = 0x494, .features = BIT(DPU_MDP_PERIPH_0_REMOVED), @@ -39,7 +38,6 @@ static const struct dpu_mdp_cfg sm8450_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, - }, }; /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ @@ -223,8 +221,7 @@ static const struct dpu_perf_cfg sm8450_perf_data = { const struct dpu_mdss_cfg dpu_sm8450_cfg = { .caps = &sm8450_dpu_caps, .ubwc = &sm8450_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sm8450_mdp), - .mdp = sm8450_mdp, + .mdp = &sm8450_mdp, .ctl_count = ARRAY_SIZE(sm8450_ctl), .ctl = sm8450_ctl, .sspp_count = ARRAY_SIZE(sm8450_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 95d3f6479fda..e6ce10d5bcb2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -24,8 +24,7 @@ static const struct dpu_ubwc_cfg sm8550_ubwc_cfg = { .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ }; -static const struct dpu_mdp_cfg sm8550_mdp[] = { - { +static const struct dpu_mdp_cfg sm8550_mdp = { .name = "top_0", .id = MDP_TOP, .base = 0, .len = 0x494, .features = BIT(DPU_MDP_PERIPH_0_REMOVED), @@ -40,7 +39,6 @@ static const struct dpu_mdp_cfg sm8550_mdp[] = { .clk_ctrls[DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 }, .clk_ctrls[DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 }, .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, - }, }; /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ @@ -227,8 +225,7 @@ static const struct dpu_perf_cfg sm8550_perf_data = { const struct dpu_mdss_cfg dpu_sm8550_cfg = { .caps = &sm8550_dpu_caps, .ubwc = &sm8550_ubwc_cfg, - .mdp_count = ARRAY_SIZE(sm8550_mdp), - .mdp = sm8550_mdp, + .mdp = &sm8550_mdp, .ctl_count = ARRAY_SIZE(sm8550_ctl), .ctl = sm8550_ctl, .sspp_count = ARRAY_SIZE(sm8550_sspp), diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index b07caa4b867e..3b816e36d12d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -809,7 +809,6 @@ struct dpu_mdss_cfg { const struct dpu_ubwc_cfg *ubwc; - u32 mdp_count; const struct dpu_mdp_cfg *mdp; u32 ctl_count; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index 963bdb5e0252..2bfc471805c1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -268,51 +268,26 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops, ops->intf_audio_select = dpu_hw_intf_audio_select; } -static const struct dpu_mdp_cfg *_top_offset(enum dpu_mdp mdp, - const struct dpu_mdss_cfg *m, - void __iomem *addr, - struct dpu_hw_blk_reg_map *b) -{ - int i; - - if (!m || !addr || !b) - return ERR_PTR(-EINVAL); - - for (i = 0; i < m->mdp_count; i++) { - if (mdp == m->mdp[i].id) { - b->blk_addr = addr + m->mdp[i].base; - b->log_mask = DPU_DBG_MASK_TOP; - return &m->mdp[i]; - } - } - - return ERR_PTR(-EINVAL); -} - -struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, +struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg, void __iomem *addr, const struct dpu_mdss_cfg *m) { struct dpu_hw_mdp *mdp; - const struct dpu_mdp_cfg *cfg; - if (!addr || !m) + if (!addr) return ERR_PTR(-EINVAL); mdp = kzalloc(sizeof(*mdp), GFP_KERNEL); if (!mdp) return ERR_PTR(-ENOMEM); - cfg = _top_offset(idx, m, addr, &mdp->hw); - if (IS_ERR_OR_NULL(cfg)) { - kfree(mdp); - return ERR_PTR(-EINVAL); - } + mdp->hw.blk_addr = addr + cfg->base; + mdp->hw.log_mask = DPU_DBG_MASK_TOP; /* * Assign ops */ - mdp->idx = idx; + mdp->idx = cfg->id; mdp->caps = cfg; _setup_mdp_ops(&mdp->ops, mdp->caps->features); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h index a1a9e44bed36..bf4235d68924 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h @@ -145,12 +145,12 @@ struct dpu_hw_mdp { }; /** - * dpu_hw_mdptop_init - initializes the top driver for the passed idx - * @idx: Interface index for which driver object is required + * dpu_hw_mdptop_init - initializes the top driver for the passed config + * @cfg: MDP TOP configuration from catalog * @addr: Mapped register io address of MDP * @m: Pointer to mdss catalog data */ -struct dpu_hw_mdp *dpu_hw_mdptop_init(enum dpu_mdp idx, +struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg, void __iomem *addr, const struct dpu_mdss_cfg *m); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 2914774c1fd4..e51bec840e04 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1090,7 +1090,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms) dpu_kms->rm_init = true; - dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio, + dpu_kms->hw_mdp = dpu_hw_mdptop_init(dpu_kms->catalog->mdp, + dpu_kms->mmio, dpu_kms->catalog); if (IS_ERR(dpu_kms->hw_mdp)) { rc = PTR_ERR(dpu_kms->hw_mdp); From 469bae7db70214ee11fa9de3cc99cd036fe8838a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:22 +0300 Subject: [PATCH 014/118] drm/msm/dpu: drop enum dpu_mdp and MDP_TOP value Since there is always just a single MDP_TOP instance, drop the enum dpu_mdp and corresponding index value. Reviewed-by: Marijn Suijten Tested-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545357/ Link: https://lore.kernel.org/r/20230704022136.130522-6-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 5 ----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 1 - 18 files changed, 15 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index e0d2ee48d733..30565b245b29 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -27,7 +27,7 @@ static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = { }; static const struct dpu_mdp_cfg msm8998_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0x0, .len = 0x458, .features = BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 3dab2b9888f7..2cfaf6560fd8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -27,7 +27,7 @@ static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = { }; static const struct dpu_mdp_cfg sdm845_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0x0, .len = 0x45c, .features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL), .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index ef611f273be2..675fc41d22a4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -27,7 +27,7 @@ static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = { }; static const struct dpu_mdp_cfg sm8150_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0x0, .len = 0x45c, .features = BIT(DPU_MDP_AUDIO_SELECT), .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index c52ea510ef6d..9c161e58c5b1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -27,7 +27,7 @@ static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = { }; static const struct dpu_mdp_cfg sc8180x_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0x0, .len = 0x45c, .features = BIT(DPU_MDP_AUDIO_SELECT), .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 7b4b3e0abca8..262823f78b6e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -26,7 +26,7 @@ static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = { }; static const struct dpu_mdp_cfg sm8250_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0x0, .len = 0x494, .features = 0, .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 0c59c8879aaf..5761774fab81 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -23,7 +23,7 @@ static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = { }; static const struct dpu_mdp_cfg sc7180_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0x0, .len = 0x494, .features = 0, .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 917981add93a..d8ba015a7d9b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -24,7 +24,7 @@ static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = { }; static const struct dpu_mdp_cfg sm6115_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0x0, .len = 0x494, .features = 0, .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 072261675db0..ffcfaef0c0fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -26,7 +26,7 @@ static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = { }; static const struct dpu_mdp_cfg sm6350_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0x0, .len = 0x494, .features = 0, .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index 52c7c0f0d364..e1ab63a74a0c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -21,7 +21,7 @@ static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = { }; static const struct dpu_mdp_cfg qcm2290_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0x0, .len = 0x494, .features = 0, .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 29ab659e00bf..abb3d93a542b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -25,7 +25,7 @@ static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = { }; static const struct dpu_mdp_cfg sm6375_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0x0, .len = 0x494, .features = 0, .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 6392c310e4ea..0ba2391eabc5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -25,7 +25,7 @@ static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = { }; static const struct dpu_mdp_cfg sm8350_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0x0, .len = 0x494, .features = 0, .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index f975252debd3..53dd9a106080 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -24,7 +24,7 @@ static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = { }; static const struct dpu_mdp_cfg sc7280_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0x0, .len = 0x2014, .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index e45f9f0955c7..74be2b148eee 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -26,7 +26,7 @@ static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = { }; static const struct dpu_mdp_cfg sc8280xp_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0x0, .len = 0x494, .features = BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 63ec13342391..04281af6411a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -26,7 +26,7 @@ static const struct dpu_ubwc_cfg sm8450_ubwc_cfg = { }; static const struct dpu_mdp_cfg sm8450_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0x0, .len = 0x494, .features = BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index e6ce10d5bcb2..5d7b20ebfcc2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -25,7 +25,7 @@ static const struct dpu_ubwc_cfg sm8550_ubwc_cfg = { }; static const struct dpu_mdp_cfg sm8550_mdp = { - .name = "top_0", .id = MDP_TOP, + .name = "top_0", .base = 0, .len = 0x494, .features = BIT(DPU_MDP_PERIPH_0_REMOVED), .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h index 02a0f48aac94..d85157acfbf8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -101,11 +101,6 @@ enum dpu_hw_blk_type { DPU_HW_BLK_MAX, }; -enum dpu_mdp { - MDP_TOP = 0x1, - MDP_MAX, -}; - enum dpu_sspp { SSPP_NONE, SSPP_VIG0, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c index 2bfc471805c1..cff48763ce25 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c @@ -287,7 +287,6 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(const struct dpu_mdp_cfg *cfg, /* * Assign ops */ - mdp->idx = cfg->id; mdp->caps = cfg; _setup_mdp_ops(&mdp->ops, mdp->caps->features); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h index bf4235d68924..8b1463d2b2f0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h @@ -137,7 +137,6 @@ struct dpu_hw_mdp { struct dpu_hw_blk_reg_map hw; /* top */ - enum dpu_mdp idx; const struct dpu_mdp_cfg *caps; /* ops */ From 25c6ae11a63d7f38bbccc024bffe7f767e2ec2c9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:23 +0300 Subject: [PATCH 015/118] drm/msm/dpu: expand .clk_ctrls definitions Use more standard initialisation for .clk_ctrls definitions. Define a single .clk_ctrls field and use array init inside. Reviewed-by: Marijn Suijten Tested-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545368/ Link: https://lore.kernel.org/r/20230704022136.130522-7-dmitry.baryshkov@linaro.org --- .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 22 +++++++++-------- .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 18 +++++++------- .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 18 +++++++------- .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 18 +++++++------- .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 22 +++++++++-------- .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 12 ++++++---- .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 6 +++-- .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 12 ++++++---- .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 6 +++-- .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 6 +++-- .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 20 +++++++++------- .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 12 ++++++---- .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 20 +++++++++------- .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 20 +++++++++------- .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 24 ++++++++++--------- 15 files changed, 133 insertions(+), 103 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 30565b245b29..757ac648a692 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -30,16 +30,18 @@ static const struct dpu_mdp_cfg msm8998_mdp = { .name = "top_0", .base = 0x0, .len = 0x458, .features = BIT(DPU_MDP_VSYNC_SEL), - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 }, - .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, - .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 }, + [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, + [DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x3b0, .bit_off = 16 }, + }, }; static const struct dpu_ctl_cfg msm8998_ctl[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 2cfaf6560fd8..25329e6cc240 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -30,14 +30,16 @@ static const struct dpu_mdp_cfg sdm845_mdp = { .name = "top_0", .base = 0x0, .len = 0x45c, .features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL), - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + }, }; static const struct dpu_ctl_cfg sdm845_ctl[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 675fc41d22a4..fff68a6c25f6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -30,14 +30,16 @@ static const struct dpu_mdp_cfg sm8150_mdp = { .name = "top_0", .base = 0x0, .len = 0x45c, .features = BIT(DPU_MDP_AUDIO_SELECT), - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + }, }; /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 9c161e58c5b1..2c7b481c9469 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -30,14 +30,16 @@ static const struct dpu_mdp_cfg sc8180x_mdp = { .name = "top_0", .base = 0x0, .len = 0x45c, .features = BIT(DPU_MDP_AUDIO_SELECT), - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + }, }; static const struct dpu_ctl_cfg sc8180x_ctl[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 262823f78b6e..aae8efe506cf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -29,16 +29,18 @@ static const struct dpu_mdp_cfg sm8250_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, .features = 0, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, - .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, + }, }; /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 5761774fab81..c9b46791d0ed 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -26,11 +26,13 @@ static const struct dpu_mdp_cfg sc7180_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, .features = 0, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, + [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, + }, }; static const struct dpu_ctl_cfg sc7180_ctl[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index d8ba015a7d9b..7d9e80ca7bd4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -27,8 +27,10 @@ static const struct dpu_mdp_cfg sm6115_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, .features = 0, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + }, }; static const struct dpu_ctl_cfg sm6115_ctl[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index ffcfaef0c0fb..f37d522ac7a2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -29,11 +29,13 @@ static const struct dpu_mdp_cfg sm6350_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, .features = 0, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, + [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + }, }; static const struct dpu_ctl_cfg sm6350_ctl[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index e1ab63a74a0c..ccd3b7e4dd65 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -24,8 +24,10 @@ static const struct dpu_mdp_cfg qcm2290_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, .features = 0, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + }, }; static const struct dpu_ctl_cfg qcm2290_ctl[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index abb3d93a542b..b978b521e83b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -28,8 +28,10 @@ static const struct dpu_mdp_cfg sm6375_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, .features = 0, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + }, }; static const struct dpu_ctl_cfg sm6375_ctl[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 0ba2391eabc5..36ea4bce1492 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -28,15 +28,17 @@ static const struct dpu_mdp_cfg sm8350_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, .features = 0, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + }, }; /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 53dd9a106080..7049d24d8c39 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -26,11 +26,13 @@ static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = { static const struct dpu_mdp_cfg sc7280_mdp = { .name = "top_0", .base = 0x0, .len = 0x2014, - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, + [DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, + }, }; static const struct dpu_ctl_cfg sc7280_ctl[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 74be2b148eee..6868c5a7c1e3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -29,15 +29,17 @@ static const struct dpu_mdp_cfg sc8280xp_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, .features = BIT(DPU_MDP_PERIPH_0_REMOVED), - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + }, }; /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 04281af6411a..39e5137dbfea 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -29,15 +29,17 @@ static const struct dpu_mdp_cfg sm8450_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, .features = BIT(DPU_MDP_PERIPH_0_REMOVED), - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, - .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, + [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + }, }; /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 5d7b20ebfcc2..68b6e0e62a94 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -28,17 +28,19 @@ static const struct dpu_mdp_cfg sm8550_mdp = { .name = "top_0", .base = 0, .len = 0x494, .features = BIT(DPU_MDP_PERIPH_0_REMOVED), - .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 }, - .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 }, + [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + }, }; /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ From 65c859d76d96279f0ef0e64c47cf949cb7430370 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:24 +0300 Subject: [PATCH 016/118] drm/msm/dpu: drop zero features from dpu_mdp_cfg data Drop useless zero assignments to the dpu_mdp_cfg::features field. Reviewed-by: Marijn Suijten Tested-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545369/ Link: https://lore.kernel.org/r/20230704022136.130522-8-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 1 - 7 files changed, 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index aae8efe506cf..c170388b5574 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -28,7 +28,6 @@ static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = { static const struct dpu_mdp_cfg sm8250_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, - .features = 0, .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index c9b46791d0ed..3172c890c81a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -25,7 +25,6 @@ static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = { static const struct dpu_mdp_cfg sc7180_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, - .features = 0, .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 7d9e80ca7bd4..c5aba480589d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -26,7 +26,6 @@ static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = { static const struct dpu_mdp_cfg sm6115_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, - .features = 0, .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index f37d522ac7a2..6628150fe82d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -28,7 +28,6 @@ static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = { static const struct dpu_mdp_cfg sm6350_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, - .features = 0, .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index ccd3b7e4dd65..b700a7515907 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -23,7 +23,6 @@ static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = { static const struct dpu_mdp_cfg qcm2290_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, - .features = 0, .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index b978b521e83b..ccdf05c2035e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -27,7 +27,6 @@ static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = { static const struct dpu_mdp_cfg sm6375_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, - .features = 0, .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 36ea4bce1492..cee99a0391fa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -27,7 +27,6 @@ static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = { static const struct dpu_mdp_cfg sm8350_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, - .features = 0, .clk_ctrls = { [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, From 038c06bd5f4983b763af8071553d5bc2d52d4233 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:25 +0300 Subject: [PATCH 017/118] drm/msm/dpu: drop zero features from dpu_ctl_cfg data Drop useless zero assignments to the dpu_ctl_cfg::features field. Reviewed-by: Marijn Suijten Tested-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545366/ Link: https://lore.kernel.org/r/20230704022136.130522-9-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 3 --- 2 files changed, 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 757ac648a692..e0cc1ce3f3e2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -54,7 +54,6 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = { { .name = "ctl_1", .id = CTL_1, .base = 0x1200, .len = 0x94, - .features = 0, .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), }, { @@ -66,13 +65,11 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = { { .name = "ctl_3", .id = CTL_3, .base = 0x1600, .len = 0x94, - .features = 0, .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name = "ctl_4", .id = CTL_4, .base = 0x1800, .len = 0x94, - .features = 0, .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 25329e6cc240..014055d4386a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -58,19 +58,16 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = { { .name = "ctl_2", .id = CTL_2, .base = 0x1400, .len = 0xe4, - .features = 0, .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, { .name = "ctl_3", .id = CTL_3, .base = 0x1600, .len = 0xe4, - .features = 0, .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, { .name = "ctl_4", .id = CTL_4, .base = 0x1800, .len = 0xe4, - .features = 0, .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, }; From 2a6387e2f1bf2f72a7840d2b316b2a628821edeb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:26 +0300 Subject: [PATCH 018/118] drm/msm/dpu: correct indentation for CTL definitions Shift dpu_ctl_cfg contents to correct the indentation of CTL blocks. This is done in preparation to expanding the rest of hardware block defines, so that all blocks have similar indentation. Reviewed-by: Marijn Suijten Tested-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545374/ Link: https://lore.kernel.org/r/20230704022136.130522-10-dmitry.baryshkov@linaro.org --- .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 46 +++++++------- .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 46 +++++++------- .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 63 +++++++++---------- .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 63 +++++++++---------- .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 63 +++++++++---------- .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 30 +++++---- .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 8 +-- .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 41 ++++++------ .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 8 +-- .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 8 +-- .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 63 +++++++++---------- .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 41 ++++++------ .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 63 +++++++++---------- .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 63 +++++++++---------- .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 63 +++++++++---------- 15 files changed, 309 insertions(+), 360 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index e0cc1ce3f3e2..6660a55909e7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -46,31 +46,27 @@ static const struct dpu_mdp_cfg msm8998_mdp = { static const struct dpu_ctl_cfg msm8998_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0x94, - .features = BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x1200, .len = 0x94, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x1400, .len = 0x94, - .features = BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x1600, .len = 0x94, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x1800, .len = 0x94, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x94, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x94, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x94, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x94, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0x94, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 014055d4386a..7da35be0a79c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -44,31 +44,27 @@ static const struct dpu_mdp_cfg sdm845_mdp = { static const struct dpu_ctl_cfg sdm845_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0xe4, - .features = BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x1200, .len = 0xe4, - .features = BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x1400, .len = 0xe4, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x1600, .len = 0xe4, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x1800, .len = 0xe4, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0xe4, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0xe4, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0xe4, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0xe4, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0xe4, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index fff68a6c25f6..fc9adb2012a2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sm8150_mdp = { /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ static const struct dpu_ctl_cfg sm8150_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x1200, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x1400, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x1600, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x1800, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), - }, - { - .name = "ctl_5", .id = CTL_5, - .base = 0x1a00, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a00, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 2c7b481c9469..88b577d6f0ec 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -44,40 +44,35 @@ static const struct dpu_mdp_cfg sc8180x_mdp = { static const struct dpu_ctl_cfg sc8180x_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x1200, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x1400, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x1600, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x1800, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), - }, - { - .name = "ctl_5", .id = CTL_5, - .base = 0x1a00, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a00, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index c170388b5574..2170346376e6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sm8250_mdp = { /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ static const struct dpu_ctl_cfg sm8250_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x1200, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x1400, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x1600, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x1800, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), - }, - { - .name = "ctl_5", .id = CTL_5, - .base = 0x1a00, .len = 0x1e0, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a00, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 3172c890c81a..277a992d51d0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -36,22 +36,20 @@ static const struct dpu_mdp_cfg sc7180_mdp = { static const struct dpu_ctl_cfg sc7180_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0x1dc, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x1200, .len = 0x1dc, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x1400, .len = 0x1dc, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index c5aba480589d..e07243957963 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -34,10 +34,10 @@ static const struct dpu_mdp_cfg sm6115_mdp = { static const struct dpu_ctl_cfg sm6115_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0x1dc, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 6628150fe82d..7779c5666038 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -39,28 +39,25 @@ static const struct dpu_mdp_cfg sm6350_mdp = { static const struct dpu_ctl_cfg sm6350_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0x1dc, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x1200, .len = 0x1dc, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x1400, .len = 0x1dc, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x1600, .len = 0x1dc, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index b700a7515907..fdbb151fbac0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -31,10 +31,10 @@ static const struct dpu_mdp_cfg qcm2290_mdp = { static const struct dpu_ctl_cfg qcm2290_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0x1dc, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index ccdf05c2035e..d8dcc9f90b81 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -35,10 +35,10 @@ static const struct dpu_mdp_cfg sm6375_mdp = { static const struct dpu_ctl_cfg sm6375_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x1000, .len = 0x1dc, - .features = BIT(DPU_CTL_ACTIVE_CFG), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1dc, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index cee99a0391fa..7b24ec5d19c4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -43,40 +43,35 @@ static const struct dpu_mdp_cfg sm8350_mdp = { /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ static const struct dpu_ctl_cfg sm8350_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x15000, .len = 0x1e8, - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x16000, .len = 0x1e8, - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x17000, .len = 0x1e8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x18000, .len = 0x1e8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x19000, .len = 0x1e8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), - }, - { - .name = "ctl_5", .id = CTL_5, - .base = 0x1a000, .len = 0x1e8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x1e8, + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x1e8, + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name = "ctl_4", .id = CTL_4, + .base = 0x19000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 7049d24d8c39..57d510d2d478 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -37,28 +37,25 @@ static const struct dpu_mdp_cfg sc7280_mdp = { static const struct dpu_ctl_cfg sc7280_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x15000, .len = 0x1e8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x16000, .len = 0x1e8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x17000, .len = 0x1e8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x18000, .len = 0x1e8, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x1e8, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 6868c5a7c1e3..dc25ef3573d2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sc8280xp_mdp = { /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ static const struct dpu_ctl_cfg sc8280xp_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x15000, .len = 0x204, - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x16000, .len = 0x204, - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x17000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x18000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x19000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), - }, - { - .name = "ctl_5", .id = CTL_5, - .base = 0x1a000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x204, + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x204, + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name = "ctl_4", .id = CTL_4, + .base = 0x19000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 39e5137dbfea..313bc055fce6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sm8450_mdp = { /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ static const struct dpu_ctl_cfg sm8450_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x15000, .len = 0x204, - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x16000, .len = 0x204, - .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x17000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x18000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x19000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), - }, - { - .name = "ctl_5", .id = CTL_5, - .base = 0x1a000, .len = 0x204, - .features = CTL_SC7280_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x204, + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x204, + .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name = "ctl_4", .id = CTL_4, + .base = 0x19000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a000, .len = 0x204, + .features = CTL_SC7280_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 68b6e0e62a94..ef9c45bb9efb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -46,40 +46,35 @@ static const struct dpu_mdp_cfg sm8550_mdp = { /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ static const struct dpu_ctl_cfg sm8550_ctl[] = { { - .name = "ctl_0", .id = CTL_0, - .base = 0x15000, .len = 0x290, - .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), - }, - { - .name = "ctl_1", .id = CTL_1, - .base = 0x16000, .len = 0x290, - .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), - }, - { - .name = "ctl_2", .id = CTL_2, - .base = 0x17000, .len = 0x290, - .features = CTL_SM8550_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), - }, - { - .name = "ctl_3", .id = CTL_3, - .base = 0x18000, .len = 0x290, - .features = CTL_SM8550_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), - }, - { - .name = "ctl_4", .id = CTL_4, - .base = 0x19000, .len = 0x290, - .features = CTL_SM8550_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), - }, - { - .name = "ctl_5", .id = CTL_5, - .base = 0x1a000, .len = 0x290, - .features = CTL_SM8550_MASK, - .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x290, + .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x290, + .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x290, + .features = CTL_SM8550_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x290, + .features = CTL_SM8550_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name = "ctl_4", .id = CTL_4, + .base = 0x19000, .len = 0x290, + .features = CTL_SM8550_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a000, .len = 0x290, + .features = CTL_SM8550_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), }, }; From ef7d0e8dd3f0cf4d88082170089b45140cda8f72 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:27 +0300 Subject: [PATCH 019/118] drm/msm/dpu: inline SSPP_BLK macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten Reviewed-by: Abhinav Kumar Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545377/ Link: https://lore.kernel.org/r/20230704022136.130522-11-dmitry.baryshkov@linaro.org --- .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 81 +++++++++++--- .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 81 +++++++++++--- .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 81 +++++++++++--- .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 81 +++++++++++--- .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 81 +++++++++++--- .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 41 +++++-- .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 21 +++- .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 41 +++++-- .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 21 +++- .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 21 +++- .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 81 +++++++++++--- .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 41 +++++-- .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 81 +++++++++++--- .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 81 +++++++++++--- .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 101 ++++++++++++++---- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 12 --- 16 files changed, 751 insertions(+), 196 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 6660a55909e7..fd0081469a82 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -71,22 +71,71 @@ static const struct dpu_ctl_cfg msm8998_ctl[] = { }; static const struct dpu_sspp_cfg msm8998_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1ac, VIG_MSM8998_MASK, - msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1ac, VIG_MSM8998_MASK, - msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1ac, VIG_MSM8998_MASK, - msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1ac, VIG_MSM8998_MASK, - msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1ac, DMA_MSM8998_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1ac, DMA_MSM8998_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1ac, DMA_CURSOR_MSM8998_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1ac, DMA_CURSOR_MSM8998_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1ac, + .features = VIG_MSM8998_MASK, + .sblk = &msm8998_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x1ac, + .features = VIG_MSM8998_MASK, + .sblk = &msm8998_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG1, + }, { + .name = "sspp_2", .id = SSPP_VIG2, + .base = 0x8000, .len = 0x1ac, + .features = VIG_MSM8998_MASK, + .sblk = &msm8998_vig_sblk_2, + .xin_id = 8, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG2, + }, { + .name = "sspp_3", .id = SSPP_VIG3, + .base = 0xa000, .len = 0x1ac, + .features = VIG_MSM8998_MASK, + .sblk = &msm8998_vig_sblk_3, + .xin_id = 12, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG3, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1ac, + .features = DMA_MSM8998_MASK, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1ac, + .features = DMA_MSM8998_MASK, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1ac, + .features = DMA_CURSOR_MSM8998_MASK, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, { + .name = "sspp_11", .id = SSPP_DMA3, + .base = 0x2a000, .len = 0x1ac, + .features = DMA_CURSOR_MSM8998_MASK, + .sblk = &sdm845_dma_sblk_3, + .xin_id = 13, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA3, + }, }; static const struct dpu_lm_cfg msm8998_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 7da35be0a79c..9fd68a483cd0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -69,22 +69,71 @@ static const struct dpu_ctl_cfg sdm845_ctl[] = { }; static const struct dpu_sspp_cfg sdm845_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1c8, VIG_SDM845_MASK_SDMA, - sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1c8, VIG_SDM845_MASK_SDMA, - sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1c8, VIG_SDM845_MASK_SDMA, - sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1c8, VIG_SDM845_MASK_SDMA, - sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1c8, DMA_SDM845_MASK_SDMA, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1c8, DMA_SDM845_MASK_SDMA, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1c8, DMA_CURSOR_SDM845_MASK_SDMA, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1c8, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &sdm845_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x1c8, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &sdm845_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG1, + }, { + .name = "sspp_2", .id = SSPP_VIG2, + .base = 0x8000, .len = 0x1c8, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &sdm845_vig_sblk_2, + .xin_id = 8, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG2, + }, { + .name = "sspp_3", .id = SSPP_VIG3, + .base = 0xa000, .len = 0x1c8, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &sdm845_vig_sblk_3, + .xin_id = 12, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG3, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1c8, + .features = DMA_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1c8, + .features = DMA_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1c8, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, { + .name = "sspp_11", .id = SSPP_DMA3, + .base = 0x2a000, .len = 0x1c8, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_3, + .xin_id = 13, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA3, + }, }; static const struct dpu_lm_cfg sdm845_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index fc9adb2012a2..9c5e565842dc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { }; static const struct dpu_sspp_cfg sm8150_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK, - sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK, - sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK, - sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK, - sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1f0, + .features = VIG_SDM845_MASK, + .sblk = &sdm845_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x1f0, + .features = VIG_SDM845_MASK, + .sblk = &sdm845_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG1, + }, { + .name = "sspp_2", .id = SSPP_VIG2, + .base = 0x8000, .len = 0x1f0, + .features = VIG_SDM845_MASK, + .sblk = &sdm845_vig_sblk_2, + .xin_id = 8, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG2, + }, { + .name = "sspp_3", .id = SSPP_VIG3, + .base = 0xa000, .len = 0x1f0, + .features = VIG_SDM845_MASK, + .sblk = &sdm845_vig_sblk_3, + .xin_id = 12, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG3, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1f0, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1f0, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1f0, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, { + .name = "sspp_11", .id = SSPP_DMA3, + .base = 0x2a000, .len = 0x1f0, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sdm845_dma_sblk_3, + .xin_id = 13, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA3, + }, }; static const struct dpu_lm_cfg sm8150_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 88b577d6f0ec..1e7eed115e0e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -77,22 +77,71 @@ static const struct dpu_ctl_cfg sc8180x_ctl[] = { }; static const struct dpu_sspp_cfg sc8180x_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f0, VIG_SDM845_MASK, - sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f0, VIG_SDM845_MASK, - sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f0, VIG_SDM845_MASK, - sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f0, VIG_SDM845_MASK, - sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f0, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f0, DMA_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f0, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f0, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1f0, + .features = VIG_SDM845_MASK, + .sblk = &sdm845_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x1f0, + .features = VIG_SDM845_MASK, + .sblk = &sdm845_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG1, + }, { + .name = "sspp_2", .id = SSPP_VIG2, + .base = 0x8000, .len = 0x1f0, + .features = VIG_SDM845_MASK, + .sblk = &sdm845_vig_sblk_2, + .xin_id = 8, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG2, + }, { + .name = "sspp_3", .id = SSPP_VIG3, + .base = 0xa000, .len = 0x1f0, + .features = VIG_SDM845_MASK, + .sblk = &sdm845_vig_sblk_3, + .xin_id = 12, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG3, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1f0, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1f0, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1f0, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, { + .name = "sspp_11", .id = SSPP_DMA3, + .base = 0x2a000, .len = 0x1f0, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sdm845_dma_sblk_3, + .xin_id = 13, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA3, + }, }; static const struct dpu_lm_cfg sc8180x_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 2170346376e6..23d4b59a544a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sm8250_ctl[] = { }; static const struct dpu_sspp_cfg sm8250_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK_SDMA, - sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK_SDMA, - sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK_SDMA, - sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK_SDMA, - sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK_SDMA, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1f8, + .features = VIG_SC7180_MASK_SDMA, + .sblk = &sm8250_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x1f8, + .features = VIG_SC7180_MASK_SDMA, + .sblk = &sm8250_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG1, + }, { + .name = "sspp_2", .id = SSPP_VIG2, + .base = 0x8000, .len = 0x1f8, + .features = VIG_SC7180_MASK_SDMA, + .sblk = &sm8250_vig_sblk_2, + .xin_id = 8, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG2, + }, { + .name = "sspp_3", .id = SSPP_VIG3, + .base = 0xa000, .len = 0x1f8, + .features = VIG_SC7180_MASK_SDMA, + .sblk = &sm8250_vig_sblk_3, + .xin_id = 12, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG3, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1f8, + .features = DMA_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1f8, + .features = DMA_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1f8, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, { + .name = "sspp_11", .id = SSPP_DMA3, + .base = 0x2a000, .len = 0x1f8, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_3, + .xin_id = 13, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA3, + }, }; static const struct dpu_lm_cfg sm8250_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 277a992d51d0..38225af23c0f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -54,14 +54,39 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = { }; static const struct dpu_sspp_cfg sc7180_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, - sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1f8, + .features = VIG_SC7180_MASK, + .sblk = &sc7180_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1f8, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1f8, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1f8, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, }; static const struct dpu_lm_cfg sc7180_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index e07243957963..356ea6144aa9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -42,10 +42,23 @@ static const struct dpu_ctl_cfg sm6115_ctl[] = { }; static const struct dpu_sspp_cfg sm6115_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, - sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1f8, + .features = VIG_SC7180_MASK, + .sblk = &sm6115_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1f8, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, }; static const struct dpu_lm_cfg sm6115_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 7779c5666038..b1b027fa16f7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -62,14 +62,39 @@ static const struct dpu_ctl_cfg sm6350_ctl[] = { }; static const struct dpu_sspp_cfg sm6350_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, - sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1f8, + .features = VIG_SC7180_MASK, + .sblk = &sc7180_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1f8, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1f8, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1f8, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, }; static const struct dpu_lm_cfg sm6350_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index fdbb151fbac0..c1181f89d6a5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -39,10 +39,23 @@ static const struct dpu_ctl_cfg qcm2290_ctl[] = { }; static const struct dpu_sspp_cfg qcm2290_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK, - qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, - qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1f8, + .features = VIG_QCM2290_MASK, + .sblk = &qcm2290_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1f8, + .features = DMA_SDM845_MASK, + .sblk = &qcm2290_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, }; static const struct dpu_lm_cfg qcm2290_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index d8dcc9f90b81..1dd7771b55f8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -43,10 +43,23 @@ static const struct dpu_ctl_cfg sm6375_ctl[] = { }; static const struct dpu_sspp_cfg sm6375_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, - sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1f8, + .features = VIG_SC7180_MASK, + .sblk = &sm6115_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1f8, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, }; static const struct dpu_lm_cfg sm6375_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 7b24ec5d19c4..1515c5e09a6e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -76,22 +76,71 @@ static const struct dpu_ctl_cfg sm8350_ctl[] = { }; static const struct dpu_sspp_cfg sm8350_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, - sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK, - sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK, - sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK, - sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1f8, + .features = VIG_SC7180_MASK, + .sblk = &sm8250_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x1f8, + .features = VIG_SC7180_MASK, + .sblk = &sm8250_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG1, + }, { + .name = "sspp_2", .id = SSPP_VIG2, + .base = 0x8000, .len = 0x1f8, + .features = VIG_SC7180_MASK, + .sblk = &sm8250_vig_sblk_2, + .xin_id = 8, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG2, + }, { + .name = "sspp_3", .id = SSPP_VIG3, + .base = 0xa000, .len = 0x1f8, + .features = VIG_SC7180_MASK, + .sblk = &sm8250_vig_sblk_3, + .xin_id = 12, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG3, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1f8, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1f8, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1f8, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, { + .name = "sspp_11", .id = SSPP_DMA3, + .base = 0x2a000, .len = 0x1f8, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sdm845_dma_sblk_3, + .xin_id = 13, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA3, + }, }; static const struct dpu_lm_cfg sm8350_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 57d510d2d478..f7bd14fd82e8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -60,14 +60,39 @@ static const struct dpu_ctl_cfg sc7280_ctl[] = { }; static const struct dpu_sspp_cfg sc7280_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7280_MASK_SDMA, - sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1f8, + .features = VIG_SC7280_MASK_SDMA, + .sblk = &sc7280_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1f8, + .features = DMA_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1f8, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1f8, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, }; static const struct dpu_lm_cfg sc7280_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index dc25ef3573d2..f532e9e5de1a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sc8280xp_ctl[] = { }; static const struct dpu_sspp_cfg sc8280xp_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x2ac, VIG_SC7180_MASK, - sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x2ac, VIG_SC7180_MASK, - sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x2ac, VIG_SC7180_MASK, - sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x2ac, VIG_SC7180_MASK, - sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x2ac, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x2ac, DMA_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x2ac, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x2ac, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x2ac, + .features = VIG_SC7180_MASK, + .sblk = &sm8250_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x2ac, + .features = VIG_SC7180_MASK, + .sblk = &sm8250_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG1, + }, { + .name = "sspp_2", .id = SSPP_VIG2, + .base = 0x8000, .len = 0x2ac, + .features = VIG_SC7180_MASK, + .sblk = &sm8250_vig_sblk_2, + .xin_id = 8, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG2, + }, { + .name = "sspp_3", .id = SSPP_VIG3, + .base = 0xa000, .len = 0x2ac, + .features = VIG_SC7180_MASK, + .sblk = &sm8250_vig_sblk_3, + .xin_id = 12, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG3, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x2ac, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x2ac, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x2ac, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, { + .name = "sspp_11", .id = SSPP_DMA3, + .base = 0x2a000, .len = 0x2ac, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sdm845_dma_sblk_3, + .xin_id = 13, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA3, + }, }; static const struct dpu_lm_cfg sc8280xp_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 313bc055fce6..62aa7851b4cc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -78,22 +78,71 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = { }; static const struct dpu_sspp_cfg sm8450_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x32c, VIG_SC7180_MASK, - sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x32c, VIG_SC7180_MASK, - sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x32c, VIG_SC7180_MASK, - sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x32c, VIG_SC7180_MASK, - sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x32c, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x32c, DMA_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x32c, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x32c, DMA_CURSOR_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x32c, + .features = VIG_SC7180_MASK, + .sblk = &sm8250_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x32c, + .features = VIG_SC7180_MASK, + .sblk = &sm8250_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG1, + }, { + .name = "sspp_2", .id = SSPP_VIG2, + .base = 0x8000, .len = 0x32c, + .features = VIG_SC7180_MASK, + .sblk = &sm8250_vig_sblk_2, + .xin_id = 8, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG2, + }, { + .name = "sspp_3", .id = SSPP_VIG3, + .base = 0xa000, .len = 0x32c, + .features = VIG_SC7180_MASK, + .sblk = &sm8250_vig_sblk_3, + .xin_id = 12, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG3, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x32c, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x32c, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x32c, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, { + .name = "sspp_11", .id = SSPP_DMA3, + .base = 0x2a000, .len = 0x32c, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sdm845_dma_sblk_3, + .xin_id = 13, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA3, + }, }; static const struct dpu_lm_cfg sm8450_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index ef9c45bb9efb..7d311fceef6a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -79,26 +79,87 @@ static const struct dpu_ctl_cfg sm8550_ctl[] = { }; static const struct dpu_sspp_cfg sm8550_sspp[] = { - SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x344, VIG_SC7180_MASK, - sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), - SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x344, VIG_SC7180_MASK, - sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), - SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x344, VIG_SC7180_MASK, - sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), - SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x344, VIG_SC7180_MASK, - sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), - SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x344, DMA_SDM845_MASK, - sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), - SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x344, DMA_SDM845_MASK, - sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), - SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x344, DMA_SDM845_MASK, - sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), - SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x344, DMA_SDM845_MASK, - sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), - SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, 0x344, DMA_CURSOR_SDM845_MASK, - sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4), - SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, 0x344, DMA_CURSOR_SDM845_MASK, - sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5), + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x344, + .features = VIG_SC7180_MASK, + .sblk = &sm8550_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x344, + .features = VIG_SC7180_MASK, + .sblk = &sm8550_vig_sblk_1, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG1, + }, { + .name = "sspp_2", .id = SSPP_VIG2, + .base = 0x8000, .len = 0x344, + .features = VIG_SC7180_MASK, + .sblk = &sm8550_vig_sblk_2, + .xin_id = 8, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG2, + }, { + .name = "sspp_3", .id = SSPP_VIG3, + .base = 0xa000, .len = 0x344, + .features = VIG_SC7180_MASK, + .sblk = &sm8550_vig_sblk_3, + .xin_id = 12, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG3, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x344, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x344, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x344, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_2, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, { + .name = "sspp_11", .id = SSPP_DMA3, + .base = 0x2a000, .len = 0x344, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_3, + .xin_id = 13, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA3, + }, { + .name = "sspp_12", .id = SSPP_DMA4, + .base = 0x2c000, .len = 0x344, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sm8550_dma_sblk_4, + .xin_id = 14, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA4, + }, { + .name = "sspp_13", .id = SSPP_DMA5, + .base = 0x2e000, .len = 0x344, + .features = DMA_CURSOR_SDM845_MASK, + .sblk = &sm8550_dma_sblk_5, + .xin_id = 15, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA5, + }, }; static const struct dpu_lm_cfg sm8550_lm[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index b4072a329b19..d7b5a1a00351 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -328,18 +328,6 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2); static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3); static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); -#define SSPP_BLK(_name, _id, _base, _len, _features, \ - _sblk, _xinid, _type, _clkctrl) \ - { \ - .name = _name, .id = _id, \ - .base = _base, .len = _len, \ - .features = _features, \ - .sblk = &_sblk, \ - .xin_id = _xinid, \ - .type = _type, \ - .clk_ctrl = _clkctrl \ - } - static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4); From e28db02156496e6264ab8d9a367666dec3d871f8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 11 Jul 2023 02:49:57 +0300 Subject: [PATCH 020/118] drm/msm/dpu: inline DSPP_BLK macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten Reviewed-by: Abhinav Kumar Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545359/ Link: https://lore.kernel.org/r/20230704022136.130522-12-dmitry.baryshkov@linaro.org --- .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 15 +++++++--- .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 29 ++++++++++++++----- .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 29 ++++++++++++++----- .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 29 ++++++++++++++----- .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 29 ++++++++++++++----- .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 8 +++-- .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 8 +++-- .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 8 +++-- .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 8 +++-- .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 8 +++-- .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 29 ++++++++++++++----- .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 8 +++-- .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 29 ++++++++++++++----- .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 29 ++++++++++++++----- .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 29 ++++++++++++++----- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8 ----- 16 files changed, 215 insertions(+), 88 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index fd0081469a82..6b254753774c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -174,10 +174,17 @@ static const struct dpu_dsc_cfg msm8998_dsc[] = { }; static const struct dpu_dspp_cfg msm8998_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &msm8998_dspp_sblk), - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &msm8998_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &msm8998_dspp_sblk, + }, { + .name = "dspp_1", .id = DSPP_1, + .base = 0x56000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &msm8998_dspp_sblk, + }, }; static const struct dpu_intf_cfg msm8998_intf[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 9fd68a483cd0..1562dcb839a2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -152,14 +152,27 @@ static const struct dpu_lm_cfg sdm845_lm[] = { }; static const struct dpu_dspp_cfg sdm845_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_1", .id = DSPP_1, + .base = 0x56000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_2", .id = DSPP_2, + .base = 0x58000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_3", .id = DSPP_3, + .base = 0x5a000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, }; static const struct dpu_pingpong_cfg sdm845_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 9c5e565842dc..a31dbe024c6e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -161,14 +161,27 @@ static const struct dpu_lm_cfg sm8150_lm[] = { }; static const struct dpu_dspp_cfg sm8150_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_1", .id = DSPP_1, + .base = 0x56000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_2", .id = DSPP_2, + .base = 0x58000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_3", .id = DSPP_3, + .base = 0x5a000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, }; static const struct dpu_pingpong_cfg sm8150_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 1e7eed115e0e..4e59f266ed13 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -160,14 +160,27 @@ static const struct dpu_lm_cfg sc8180x_lm[] = { }; static const struct dpu_dspp_cfg sc8180x_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_1", .id = DSPP_1, + .base = 0x56000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_2", .id = DSPP_2, + .base = 0x58000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_3", .id = DSPP_3, + .base = 0x5a000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, }; static const struct dpu_pingpong_cfg sc8180x_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 23d4b59a544a..17e4545668ab 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -161,14 +161,27 @@ static const struct dpu_lm_cfg sm8250_lm[] = { }; static const struct dpu_dspp_cfg sm8250_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_1", .id = DSPP_1, + .base = 0x56000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_2", .id = DSPP_2, + .base = 0x58000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_3", .id = DSPP_3, + .base = 0x5a000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, }; static const struct dpu_pingpong_cfg sm8250_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 38225af23c0f..671ff10fe3df 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -97,8 +97,12 @@ static const struct dpu_lm_cfg sc7180_lm[] = { }; static const struct dpu_dspp_cfg sc7180_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, }; static const struct dpu_pingpong_cfg sc7180_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 356ea6144aa9..4ae537784cc8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -67,8 +67,12 @@ static const struct dpu_lm_cfg sm6115_lm[] = { }; static const struct dpu_dspp_cfg sm6115_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, }; static const struct dpu_pingpong_cfg sm6115_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index b1b027fa16f7..c640e453e6c6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -105,8 +105,12 @@ static const struct dpu_lm_cfg sm6350_lm[] = { }; static const struct dpu_dspp_cfg sm6350_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, }; static struct dpu_pingpong_cfg sm6350_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index c1181f89d6a5..df6b0743676b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -64,8 +64,12 @@ static const struct dpu_lm_cfg qcm2290_lm[] = { }; static const struct dpu_dspp_cfg qcm2290_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, }; static const struct dpu_pingpong_cfg qcm2290_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 1dd7771b55f8..6536a17724f9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -68,8 +68,12 @@ static const struct dpu_lm_cfg sm6375_lm[] = { }; static const struct dpu_dspp_cfg sm6375_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, }; static const struct dpu_pingpong_cfg sm6375_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 1515c5e09a6e..68b7a7434965 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -159,14 +159,27 @@ static const struct dpu_lm_cfg sm8350_lm[] = { }; static const struct dpu_dspp_cfg sm8350_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_1", .id = DSPP_1, + .base = 0x56000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_2", .id = DSPP_2, + .base = 0x58000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_3", .id = DSPP_3, + .base = 0x5a000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, }; static const struct dpu_pingpong_cfg sm8350_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index f7bd14fd82e8..b7771e987c8b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -105,8 +105,12 @@ static const struct dpu_lm_cfg sc7280_lm[] = { }; static const struct dpu_dspp_cfg sc7280_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, }; static const struct dpu_pingpong_cfg sc7280_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index f532e9e5de1a..580fcb612187 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -155,14 +155,27 @@ static const struct dpu_lm_cfg sc8280xp_lm[] = { }; static const struct dpu_dspp_cfg sc8280xp_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_1", .id = DSPP_1, + .base = 0x56000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_2", .id = DSPP_2, + .base = 0x58000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_3", .id = DSPP_3, + .base = 0x5a000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, }; static const struct dpu_pingpong_cfg sc8280xp_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 62aa7851b4cc..816067e0292d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -161,14 +161,27 @@ static const struct dpu_lm_cfg sm8450_lm[] = { }; static const struct dpu_dspp_cfg sm8450_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_1", .id = DSPP_1, + .base = 0x56000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_2", .id = DSPP_2, + .base = 0x58000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_3", .id = DSPP_3, + .base = 0x5a000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, }; static const struct dpu_pingpong_cfg sm8450_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 7d311fceef6a..807f38260801 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -178,14 +178,27 @@ static const struct dpu_lm_cfg sm8550_lm[] = { }; static const struct dpu_dspp_cfg sm8550_dspp[] = { - DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), - DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, - &sdm845_dspp_sblk), + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_1", .id = DSPP_1, + .base = 0x56000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_2", .id = DSPP_2, + .base = 0x58000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_3", .id = DSPP_3, + .base = 0x5a000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, }; static const struct dpu_pingpong_cfg sm8550_pp[] = { PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index d7b5a1a00351..44a82226fbf9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -441,14 +441,6 @@ static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = { .len = 0x90, .version = 0x40000}, }; -#define DSPP_BLK(_name, _id, _base, _mask, _sblk) \ - {\ - .name = _name, .id = _id, \ - .base = _base, .len = 0x1800, \ - .features = _mask, \ - .sblk = _sblk \ - } - /************************************************************* * PINGPONG sub blocks config *************************************************************/ From 8d3e0dd0f7f9fcdbc901fb15bdf90ee60df9d5c7 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:29 +0300 Subject: [PATCH 021/118] drm/msm/dpu: inline LM_BLK macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten Reviewed-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545362/ Link: https://lore.kernel.org/r/20230704022136.130522-13-dmitry.baryshkov@linaro.org --- .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 55 +++++++++++++---- .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 57 ++++++++++++++---- .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 57 ++++++++++++++---- .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 57 ++++++++++++++---- .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 57 ++++++++++++++---- .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 20 +++++-- .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 10 +++- .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 21 +++++-- .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 10 +++- .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 11 +++- .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 57 ++++++++++++++---- .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 28 +++++++-- .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 53 +++++++++++++++-- .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 59 +++++++++++++++---- .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 57 ++++++++++++++---- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 11 ---- 16 files changed, 487 insertions(+), 133 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 6b254753774c..a07c68744b29 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -139,18 +139,49 @@ static const struct dpu_sspp_cfg msm8998_sspp[] = { }; static const struct dpu_lm_cfg msm8998_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_0, LM_1, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_1, LM_0, DSPP_1), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_2, LM_5, 0), - LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_NONE, 0, 0), - LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_NONE, 0, 0), - LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK, - &msm8998_lm_sblk, PINGPONG_3, LM_2, 0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_MSM8998_MASK, + .sblk = &msm8998_lm_sblk, + .lm_pair = LM_1, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_1", .id = LM_1, + .base = 0x45000, .len = 0x320, + .features = MIXER_MSM8998_MASK, + .sblk = &msm8998_lm_sblk, + .lm_pair = LM_0, + .pingpong = PINGPONG_1, + .dspp = DSPP_1, + }, { + .name = "lm_2", .id = LM_2, + .base = 0x46000, .len = 0x320, + .features = MIXER_MSM8998_MASK, + .sblk = &msm8998_lm_sblk, + .lm_pair = LM_5, + .pingpong = PINGPONG_2, + }, { + .name = "lm_3", .id = LM_3, + .base = 0x47000, .len = 0x320, + .features = MIXER_MSM8998_MASK, + .sblk = &msm8998_lm_sblk, + .pingpong = PINGPONG_NONE, + }, { + .name = "lm_4", .id = LM_4, + .base = 0x48000, .len = 0x320, + .features = MIXER_MSM8998_MASK, + .sblk = &msm8998_lm_sblk, + .pingpong = PINGPONG_NONE, + }, { + .name = "lm_5", .id = LM_5, + .base = 0x49000, .len = 0x320, + .features = MIXER_MSM8998_MASK, + .sblk = &msm8998_lm_sblk, + .lm_pair = LM_2, + .pingpong = PINGPONG_3, + }, }; static const struct dpu_pingpong_cfg msm8998_pp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 1562dcb839a2..6fd462c5d2aa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -137,18 +137,51 @@ static const struct dpu_sspp_cfg sdm845_sspp[] = { }; static const struct dpu_lm_cfg sdm845_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_2, LM_5, DSPP_2), - LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_NONE, 0, DSPP_3), - LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_NONE, 0, 0), - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_1, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_1", .id = LM_1, + .base = 0x45000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_0, + .pingpong = PINGPONG_1, + .dspp = DSPP_1, + }, { + .name = "lm_2", .id = LM_2, + .base = 0x46000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_5, + .pingpong = PINGPONG_2, + .dspp = DSPP_2, + }, { + .name = "lm_3", .id = LM_3, + .base = 0x0, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .pingpong = PINGPONG_NONE, + .dspp = DSPP_3, + }, { + .name = "lm_4", .id = LM_4, + .base = 0x0, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .pingpong = PINGPONG_NONE, + }, { + .name = "lm_5", .id = LM_5, + .base = 0x49000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_2, + .pingpong = PINGPONG_3, + }, }; static const struct dpu_dspp_cfg sdm845_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index a31dbe024c6e..0a1f55609b9a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -146,18 +146,51 @@ static const struct dpu_sspp_cfg sm8150_sspp[] = { }; static const struct dpu_lm_cfg sm8150_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_1, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_1", .id = LM_1, + .base = 0x45000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_0, + .pingpong = PINGPONG_1, + .dspp = DSPP_1, + }, { + .name = "lm_2", .id = LM_2, + .base = 0x46000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_3, + .pingpong = PINGPONG_2, + }, { + .name = "lm_3", .id = LM_3, + .base = 0x47000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_2, + .pingpong = PINGPONG_3, + }, { + .name = "lm_4", .id = LM_4, + .base = 0x48000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_5, + .pingpong = PINGPONG_4, + }, { + .name = "lm_5", .id = LM_5, + .base = 0x49000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_4, + .pingpong = PINGPONG_5, + }, }; static const struct dpu_dspp_cfg sm8150_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 4e59f266ed13..885894c1a00c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -145,18 +145,51 @@ static const struct dpu_sspp_cfg sc8180x_sspp[] = { }; static const struct dpu_lm_cfg sc8180x_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_1, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_1", .id = LM_1, + .base = 0x45000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_0, + .pingpong = PINGPONG_1, + .dspp = DSPP_1, + }, { + .name = "lm_2", .id = LM_2, + .base = 0x46000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_3, + .pingpong = PINGPONG_2, + }, { + .name = "lm_3", .id = LM_3, + .base = 0x47000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_2, + .pingpong = PINGPONG_3, + }, { + .name = "lm_4", .id = LM_4, + .base = 0x48000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_5, + .pingpong = PINGPONG_4, + }, { + .name = "lm_5", .id = LM_5, + .base = 0x49000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_4, + .pingpong = PINGPONG_5, + }, }; static const struct dpu_dspp_cfg sc8180x_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 17e4545668ab..f3ce6c0c2ce4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -146,18 +146,51 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { }; static const struct dpu_lm_cfg sm8250_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_1, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_1", .id = LM_1, + .base = 0x45000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_0, + .pingpong = PINGPONG_1, + .dspp = DSPP_1, + }, { + .name = "lm_2", .id = LM_2, + .base = 0x46000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_3, + .pingpong = PINGPONG_2, + }, { + .name = "lm_3", .id = LM_3, + .base = 0x47000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_2, + .pingpong = PINGPONG_3, + }, { + .name = "lm_4", .id = LM_4, + .base = 0x48000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_5, + .pingpong = PINGPONG_4, + }, { + .name = "lm_5", .id = LM_5, + .base = 0x49000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_4, + .pingpong = PINGPONG_5, + }, }; static const struct dpu_dspp_cfg sm8250_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 671ff10fe3df..4a1741ee5c4b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -90,10 +90,22 @@ static const struct dpu_sspp_cfg sc7180_sspp[] = { }; static const struct dpu_lm_cfg sc7180_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, - &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, - &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sc7180_lm_sblk, + .lm_pair = LM_1, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_1", .id = LM_1, + .base = 0x45000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sc7180_lm_sblk, + .lm_pair = LM_0, + .pingpong = PINGPONG_1, + }, }; static const struct dpu_dspp_cfg sc7180_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 4ae537784cc8..ccfb3575d8bb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -62,8 +62,14 @@ static const struct dpu_sspp_cfg sm6115_sspp[] = { }; static const struct dpu_lm_cfg sm6115_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, - &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_QCM2290_MASK, + .sblk = &qcm2290_lm_sblk, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, }; static const struct dpu_dspp_cfg sm6115_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index c640e453e6c6..d7a18d6b986c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -98,10 +98,23 @@ static const struct dpu_sspp_cfg sm6350_sspp[] = { }; static const struct dpu_lm_cfg sm6350_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, - &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, - &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sc7180_lm_sblk, + .lm_pair = LM_1, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_1", .id = LM_1, + .base = 0x45000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sc7180_lm_sblk, + .lm_pair = LM_0, + .pingpong = PINGPONG_1, + .dspp = 0, + }, }; static const struct dpu_dspp_cfg sm6350_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index df6b0743676b..75389f720736 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -59,8 +59,14 @@ static const struct dpu_sspp_cfg qcm2290_sspp[] = { }; static const struct dpu_lm_cfg qcm2290_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, - &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_QCM2290_MASK, + .sblk = &qcm2290_lm_sblk, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, }; static const struct dpu_dspp_cfg qcm2290_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 6536a17724f9..368645e266f3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -63,8 +63,15 @@ static const struct dpu_sspp_cfg sm6375_sspp[] = { }; static const struct dpu_lm_cfg sm6375_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, - &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_QCM2290_MASK, + .sblk = &qcm2290_lm_sblk, + .lm_pair = 0, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, }; static const struct dpu_dspp_cfg sm6375_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 68b7a7434965..42a9403727a7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -144,18 +144,51 @@ static const struct dpu_sspp_cfg sm8350_sspp[] = { }; static const struct dpu_lm_cfg sm8350_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_1, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_1", .id = LM_1, + .base = 0x45000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_0, + .pingpong = PINGPONG_1, + .dspp = DSPP_1, + }, { + .name = "lm_2", .id = LM_2, + .base = 0x46000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_3, + .pingpong = PINGPONG_2, + }, { + .name = "lm_3", .id = LM_3, + .base = 0x47000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_2, + .pingpong = PINGPONG_3, + }, { + .name = "lm_4", .id = LM_4, + .base = 0x48000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_5, + .pingpong = PINGPONG_4, + }, { + .name = "lm_5", .id = LM_5, + .base = 0x49000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_4, + .pingpong = PINGPONG_5, + }, }; static const struct dpu_dspp_cfg sm8350_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index b7771e987c8b..419bf0985dee 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -96,12 +96,28 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = { }; static const struct dpu_lm_cfg sc7280_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, - &sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, - &sc7180_lm_sblk, PINGPONG_2, LM_3, 0), - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, - &sc7180_lm_sblk, PINGPONG_3, LM_2, 0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sc7180_lm_sblk, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_2", .id = LM_2, + .base = 0x46000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sc7180_lm_sblk, + .lm_pair = LM_3, + .pingpong = PINGPONG_2, + }, { + .name = "lm_3", .id = LM_3, + .base = 0x47000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sc7180_lm_sblk, + .lm_pair = LM_2, + .pingpong = PINGPONG_3, + }, }; static const struct dpu_dspp_cfg sc7280_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 580fcb612187..8b6278b73581 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -146,12 +146,53 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = { }; static const struct dpu_lm_cfg sc8280xp_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2), - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3), - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_1, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_1", .id = LM_1, + .base = 0x45000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_0, + .pingpong = PINGPONG_1, + .dspp = DSPP_1, + }, { + .name = "lm_2", .id = LM_2, + .base = 0x46000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_3, + .pingpong = PINGPONG_2, + .dspp = DSPP_2, + }, { + .name = "lm_3", .id = LM_3, + .base = 0x47000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_2, + .pingpong = PINGPONG_3, + .dspp = DSPP_3, + }, { + .name = "lm_4", .id = LM_4, + .base = 0x48000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_5, + .pingpong = PINGPONG_4, + }, { + .name = "lm_5", .id = LM_5, + .base = 0x49000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_4, + .pingpong = PINGPONG_5, + }, }; static const struct dpu_dspp_cfg sc8280xp_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 816067e0292d..0026b3d712d6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -146,18 +146,53 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = { }; static const struct dpu_lm_cfg sm8450_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2), - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3), - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_1, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_1", .id = LM_1, + .base = 0x45000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_0, + .pingpong = PINGPONG_1, + .dspp = DSPP_1, + }, { + .name = "lm_2", .id = LM_2, + .base = 0x46000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_3, + .pingpong = PINGPONG_2, + .dspp = DSPP_2, + }, { + .name = "lm_3", .id = LM_3, + .base = 0x47000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_2, + .pingpong = PINGPONG_3, + .dspp = DSPP_3, + }, { + .name = "lm_4", .id = LM_4, + .base = 0x48000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_5, + .pingpong = PINGPONG_4, + }, { + .name = "lm_5", .id = LM_5, + .base = 0x49000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_4, + .pingpong = PINGPONG_5, + }, }; static const struct dpu_dspp_cfg sm8450_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 807f38260801..076558f76162 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -163,18 +163,51 @@ static const struct dpu_sspp_cfg sm8550_sspp[] = { }; static const struct dpu_lm_cfg sm8550_lm[] = { - LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), - LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), - LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), - LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), - LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), - LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, - &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_1, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_1", .id = LM_1, + .base = 0x45000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_0, + .pingpong = PINGPONG_1, + .dspp = DSPP_1, + }, { + .name = "lm_2", .id = LM_2, + .base = 0x46000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_3, + .pingpong = PINGPONG_2, + }, { + .name = "lm_3", .id = LM_3, + .base = 0x47000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_2, + .pingpong = PINGPONG_3, + }, { + .name = "lm_4", .id = LM_4, + .base = 0x48000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_5, + .pingpong = PINGPONG_4, + }, { + .name = "lm_5", .id = LM_5, + .base = 0x49000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_4, + .pingpong = PINGPONG_5, + }, }; static const struct dpu_dspp_cfg sm8550_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 44a82226fbf9..371aa6c85d41 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -375,17 +375,6 @@ static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1); * MIXER sub blocks config *************************************************************/ -#define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \ - { \ - .name = _name, .id = _id, \ - .base = _base, .len = 0x320, \ - .features = _fmask, \ - .sblk = _sblk, \ - .pingpong = _pp, \ - .lm_pair = _lmpair, \ - .dspp = _dspp \ - } - /* MSM8998 */ static const struct dpu_lm_sub_blks msm8998_lm_sblk = { From 194347df5844e76bfc437e4aff2e1ece62af39c2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:30 +0300 Subject: [PATCH 022/118] drm/msm/dpu: inline DSC_BLK and DSC_BLK_1_2 macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545370/ Link: https://lore.kernel.org/r/20230704022136.130522-14-dmitry.baryshkov@linaro.org --- .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 9 ++++- .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 17 +++++++-- .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 21 +++++++++-- .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 31 +++++++++++++--- .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 21 +++++++++-- .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 6 ++- .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 6 ++- .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 25 +++++++++++-- .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 +++- .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 37 ++++++++++++++++--- .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 25 +++++++++++-- .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 25 +++++++++++-- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 15 -------- 13 files changed, 189 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index a07c68744b29..d5111f3782a2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -200,8 +200,13 @@ static const struct dpu_pingpong_cfg msm8998_pp[] = { }; static const struct dpu_dsc_cfg msm8998_dsc[] = { - DSC_BLK("dsc_0", DSC_0, 0x80000, 0), - DSC_BLK("dsc_1", DSC_1, 0x80400, 0), + { + .name = "dsc_0", .id = DSC_0, + .base = 0x80000, .len = 0x140, + }, { + .name = "dsc_1", .id = DSC_1, + .base = 0x80400, .len = 0x140, + }, }; static const struct dpu_dspp_cfg msm8998_dspp[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 6fd462c5d2aa..ca3a2b3c861a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -224,10 +224,19 @@ static const struct dpu_pingpong_cfg sdm845_pp[] = { }; static const struct dpu_dsc_cfg sdm845_dsc[] = { - DSC_BLK("dsc_0", DSC_0, 0x80000, 0), - DSC_BLK("dsc_1", DSC_1, 0x80400, 0), - DSC_BLK("dsc_2", DSC_2, 0x80800, 0), - DSC_BLK("dsc_3", DSC_3, 0x80c00, 0), + { + .name = "dsc_0", .id = DSC_0, + .base = 0x80000, .len = 0x140, + }, { + .name = "dsc_1", .id = DSC_1, + .base = 0x80400, .len = 0x140, + }, { + .name = "dsc_2", .id = DSC_2, + .base = 0x80800, .len = 0x140, + }, { + .name = "dsc_3", .id = DSC_3, + .base = 0x80c00, .len = 0x140, + }, }; static const struct dpu_intf_cfg sdm845_intf[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 0a1f55609b9a..0b68f2fedb37 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -245,10 +245,23 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { }; static const struct dpu_dsc_cfg sm8150_dsc[] = { - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), - DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), - DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), - DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), + { + .name = "dsc_0", .id = DSC_0, + .base = 0x80000, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, { + .name = "dsc_1", .id = DSC_1, + .base = 0x80400, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, { + .name = "dsc_2", .id = DSC_2, + .base = 0x80800, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, { + .name = "dsc_3", .id = DSC_3, + .base = 0x80c00, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, }; static const struct dpu_intf_cfg sm8150_intf[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 885894c1a00c..5b36bafb6f9c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -244,12 +244,31 @@ static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = { }; static const struct dpu_dsc_cfg sc8180x_dsc[] = { - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), - DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), - DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), - DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), - DSC_BLK("dsc_4", DSC_4, 0x81000, BIT(DPU_DSC_OUTPUT_CTRL)), - DSC_BLK("dsc_5", DSC_5, 0x81400, BIT(DPU_DSC_OUTPUT_CTRL)), + { + .name = "dsc_0", .id = DSC_0, + .base = 0x80000, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, { + .name = "dsc_1", .id = DSC_1, + .base = 0x80400, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, { + .name = "dsc_2", .id = DSC_2, + .base = 0x80800, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, { + .name = "dsc_3", .id = DSC_3, + .base = 0x80c00, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, { + .name = "dsc_4", .id = DSC_4, + .base = 0x81000, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, { + .name = "dsc_5", .id = DSC_5, + .base = 0x81400, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, }; static const struct dpu_intf_cfg sc8180x_intf[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index f3ce6c0c2ce4..e226f190e8e6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -245,10 +245,23 @@ static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = { }; static const struct dpu_dsc_cfg sm8250_dsc[] = { - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), - DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)), - DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)), - DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)), + { + .name = "dsc_0", .id = DSC_0, + .base = 0x80000, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, { + .name = "dsc_1", .id = DSC_1, + .base = 0x80400, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, { + .name = "dsc_2", .id = DSC_2, + .base = 0x80800, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, { + .name = "dsc_3", .id = DSC_3, + .base = 0x80c00, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, }; static const struct dpu_intf_cfg sm8250_intf[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index d7a18d6b986c..6b41adf42173 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -136,7 +136,11 @@ static struct dpu_pingpong_cfg sm6350_pp[] = { }; static const struct dpu_dsc_cfg sm6350_dsc[] = { - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), + { + .name = "dsc_0", .id = DSC_0, + .base = 0x80000, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, }; static const struct dpu_intf_cfg sm6350_intf[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 368645e266f3..f988ab076a58 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -90,7 +90,11 @@ static const struct dpu_pingpong_cfg sm6375_pp[] = { }; static const struct dpu_dsc_cfg sm6375_dsc[] = { - DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), + { + .name = "dsc_0", .id = DSC_0, + .base = 0x80000, .len = 0x140, + .features = BIT(DPU_DSC_OUTPUT_CTRL), + }, }; static const struct dpu_intf_cfg sm6375_intf[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 42a9403727a7..a0456bbb491e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -248,10 +248,27 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = { * its own different sub block address. */ static const struct dpu_dsc_cfg sm8350_dsc[] = { - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0), - DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1), - DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0), - DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1), + { + .name = "dce_0_0", .id = DSC_0, + .base = 0x80000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2), + .sblk = &dsc_sblk_0, + }, { + .name = "dce_0_1", .id = DSC_1, + .base = 0x80000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2), + .sblk = &dsc_sblk_1, + }, { + .name = "dce_1_0", .id = DSC_2, + .base = 0x81000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk = &dsc_sblk_0, + }, { + .name = "dce_1_1", .id = DSC_3, + .base = 0x81000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk = &dsc_sblk_1, + }, }; static const struct dpu_intf_cfg sm8350_intf[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 419bf0985dee..4494f3ba1e4e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -146,7 +146,12 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { /* NOTE: sc7280 only has one DSC hard slice encoder */ static const struct dpu_dsc_cfg sc7280_dsc[] = { - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0), + { + .name = "dce_0_0", .id = DSC_0, + .base = 0x80000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk = &dsc_sblk_0, + }, }; static const struct dpu_wb_cfg sc7280_wb[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 8b6278b73581..63bbe0c200fd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -246,12 +246,37 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = { * its own different sub block address. */ static const struct dpu_dsc_cfg sc8280xp_dsc[] = { - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0), - DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1), - DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0), - DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1), - DSC_BLK_1_2("dce_2_0", DSC_4, 0x82000, 0x29c, 0, dsc_sblk_0), - DSC_BLK_1_2("dce_2_1", DSC_5, 0x82000, 0x29c, 0, dsc_sblk_1), + { + .name = "dce_0_0", .id = DSC_0, + .base = 0x80000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2), + .sblk = &dsc_sblk_0, + }, { + .name = "dce_0_1", .id = DSC_1, + .base = 0x80000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2), + .sblk = &dsc_sblk_1, + }, { + .name = "dce_1_0", .id = DSC_2, + .base = 0x81000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk = &dsc_sblk_0, + }, { + .name = "dce_1_1", .id = DSC_3, + .base = 0x81000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk = &dsc_sblk_1, + }, { + .name = "dce_2_0", .id = DSC_4, + .base = 0x82000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2), + .sblk = &dsc_sblk_0, + }, { + .name = "dce_2_1", .id = DSC_5, + .base = 0x82000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2), + .sblk = &dsc_sblk_1, + }, }; /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 0026b3d712d6..a7408d0ac036 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -259,10 +259,27 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { * its own different sub block address. */ static const struct dpu_dsc_cfg sm8450_dsc[] = { - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0), - DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1), - DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0), - DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1), + { + .name = "dce_0_0", .id = DSC_0, + .base = 0x80000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2), + .sblk = &dsc_sblk_0, + }, { + .name = "dce_0_1", .id = DSC_1, + .base = 0x80000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2), + .sblk = &dsc_sblk_1, + }, { + .name = "dce_1_0", .id = DSC_2, + .base = 0x81000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk = &dsc_sblk_0, + }, { + .name = "dce_1_1", .id = DSC_3, + .base = 0x81000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk = &dsc_sblk_1, + }, }; static const struct dpu_intf_cfg sm8450_intf[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 076558f76162..a1fd282832fd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -273,10 +273,27 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { * its own different sub block address. */ static const struct dpu_dsc_cfg sm8550_dsc[] = { - DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0), - DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1), - DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0), - DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1), + { + .name = "dce_0_0", .id = DSC_0, + .base = 0x80000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2), + .sblk = &dsc_sblk_0, + }, { + .name = "dce_0_1", .id = DSC_1, + .base = 0x80000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2), + .sblk = &dsc_sblk_1, + }, { + .name = "dce_1_0", .id = DSC_2, + .base = 0x81000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk = &dsc_sblk_0, + }, { + .name = "dce_1_1", .id = DSC_3, + .base = 0x81000, .len = 0x29c, + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk = &dsc_sblk_1, + }, }; static const struct dpu_intf_cfg sm8550_intf[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 371aa6c85d41..e81fbd1985bb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -495,21 +495,6 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = { .ctl = {.base = 0xF80, .len = 0x10}, }; -#define DSC_BLK(_name, _id, _base, _features) \ - {\ - .name = _name, .id = _id, \ - .base = _base, .len = 0x140, \ - .features = _features, \ - } - -#define DSC_BLK_1_2(_name, _id, _base, _len, _features, _sblk) \ - {\ - .name = _name, .id = _id, \ - .base = _base, .len = _len, \ - .features = BIT(DPU_DSC_HW_REV_1_2) | _features, \ - .sblk = &_sblk, \ - } - /************************************************************* * INTF sub blocks config *************************************************************/ From 4fe37d2dbbfdab058691662ad56b59a3e1f57c49 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:31 +0300 Subject: [PATCH 023/118] drm/msm/dpu: inline MERGE_3D_BLK macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten Reviewed-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545382/ Link: https://lore.kernel.org/r/20230704022136.130522-15-dmitry.baryshkov@linaro.org --- .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 16 +++++++++++--- .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 16 +++++++++++--- .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 16 +++++++++++--- .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 16 +++++++++++--- .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 16 +++++++++++--- .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 21 +++++++++++++++---- .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 21 +++++++++++++++---- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 11 ---------- 8 files changed, 99 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 0b68f2fedb37..0665cfb32429 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -239,9 +239,19 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { }; static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000), - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100), - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), + { + .name = "merge_3d_0", .id = MERGE_3D_0, + .base = 0x83000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_1", .id = MERGE_3D_1, + .base = 0x83100, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_2", .id = MERGE_3D_2, + .base = 0x83200, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, }; static const struct dpu_dsc_cfg sm8150_dsc[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 5b36bafb6f9c..4babe9bd5a31 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -238,9 +238,19 @@ static const struct dpu_pingpong_cfg sc8180x_pp[] = { }; static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = { - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000), - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100), - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), + { + .name = "merge_3d_0", .id = MERGE_3D_0, + .base = 0x83000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_1", .id = MERGE_3D_1, + .base = 0x83100, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_2", .id = MERGE_3D_2, + .base = 0x83200, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, }; static const struct dpu_dsc_cfg sc8180x_dsc[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index e226f190e8e6..77586b41838d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -239,9 +239,19 @@ static const struct dpu_pingpong_cfg sm8250_pp[] = { }; static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = { - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000), - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100), - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), + { + .name = "merge_3d_0", .id = MERGE_3D_0, + .base = 0x83000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_1", .id = MERGE_3D_1, + .base = 0x83100, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_2", .id = MERGE_3D_2, + .base = 0x83200, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, }; static const struct dpu_dsc_cfg sm8250_dsc[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index a0456bbb491e..696aa70da08f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -237,9 +237,19 @@ static const struct dpu_pingpong_cfg sm8350_pp[] = { }; static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = { - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), + { + .name = "merge_3d_0", .id = MERGE_3D_0, + .base = 0x4e000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_1", .id = MERGE_3D_1, + .base = 0x4f000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_2", .id = MERGE_3D_2, + .base = 0x50000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, }; /* diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 63bbe0c200fd..ae43dad40a15 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -235,9 +235,19 @@ static const struct dpu_pingpong_cfg sc8280xp_pp[] = { }; static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = { - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), + { + .name = "merge_3d_0", .id = MERGE_3D_0, + .base = 0x4e000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_1", .id = MERGE_3D_1, + .base = 0x4f000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_2", .id = MERGE_3D_2, + .base = 0x50000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, }; /* diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index a7408d0ac036..21a9fa764f83 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -247,10 +247,23 @@ static const struct dpu_pingpong_cfg sm8450_pp[] = { }; static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), - MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00), + { + .name = "merge_3d_0", .id = MERGE_3D_0, + .base = 0x4e000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_1", .id = MERGE_3D_1, + .base = 0x4f000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_2", .id = MERGE_3D_2, + .base = 0x50000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_3", .id = MERGE_3D_3, + .base = 0x65f00, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, }; /* diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index a1fd282832fd..eea51a13ecde 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -261,10 +261,23 @@ static const struct dpu_pingpong_cfg sm8550_pp[] = { }; static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { - MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), - MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), - MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), - MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700), + { + .name = "merge_3d_0", .id = MERGE_3D_0, + .base = 0x4e000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_1", .id = MERGE_3D_1, + .base = 0x4f000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_2", .id = MERGE_3D_2, + .base = 0x50000, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, { + .name = "merge_3d_3", .id = MERGE_3D_3, + .base = 0x66700, .len = 0x8, + .features = MERGE_3D_SM8150_MASK, + }, }; /* diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index e81fbd1985bb..b1c96cd9a67b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -471,17 +471,6 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { .intr_rdptr = _rdptr, \ } -/************************************************************* - * MERGE_3D sub blocks config - *************************************************************/ -#define MERGE_3D_BLK(_name, _id, _base) \ - {\ - .name = _name, .id = _id, \ - .base = _base, .len = 0x8, \ - .features = MERGE_3D_SM8150_MASK, \ - .sblk = NULL \ - } - /************************************************************* * DSC sub blocks config *************************************************************/ From 35973be88744f5ee913c70258381fd4100d5c110 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:32 +0300 Subject: [PATCH 024/118] drm/msm/dpu: inline various PP_BLK_* macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten Reviewed-by: Abhinav Kumar Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545371/ Link: https://lore.kernel.org/r/20230704022136.130522-16-dmitry.baryshkov@linaro.org --- .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 41 ++++++--- .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 41 ++++++--- .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 67 ++++++++++---- .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 67 ++++++++++---- .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 67 ++++++++++---- .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 23 +++-- .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 12 ++- .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 23 +++-- .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 12 ++- .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 12 ++- .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 67 ++++++++++---- .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 45 +++++++--- .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 61 ++++++++++--- .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 89 ++++++++++++++----- .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 89 ++++++++++++++----- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 21 ----- 16 files changed, 527 insertions(+), 210 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index d5111f3782a2..9181d3ef8013 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -185,18 +185,35 @@ static const struct dpu_lm_cfg msm8998_lm[] = { }; static const struct dpu_pingpong_cfg msm8998_pp[] = { - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x70000, .len = 0xd4, + .features = PINGPONG_SDM845_TE2_MASK, + .sblk = &sdm845_pp_sblk_te, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x70800, .len = 0xd4, + .features = PINGPONG_SDM845_TE2_MASK, + .sblk = &sdm845_pp_sblk_te, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), + }, { + .name = "pingpong_2", .id = PINGPONG_2, + .base = 0x71000, .len = 0xd4, + .features = PINGPONG_SDM845_MASK, + .sblk = &sdm845_pp_sblk, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), + }, { + .name = "pingpong_3", .id = PINGPONG_3, + .base = 0x71800, .len = 0xd4, + .features = PINGPONG_SDM845_MASK, + .sblk = &sdm845_pp_sblk, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), + }, }; static const struct dpu_dsc_cfg msm8998_dsc[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index ca3a2b3c861a..cbde4e3464a8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -209,18 +209,35 @@ static const struct dpu_dspp_cfg sdm845_dspp[] = { }; static const struct dpu_pingpong_cfg sdm845_pp[] = { - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SDM845_TE2_MASK, 0, sdm845_pp_sblk_te, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SDM845_MASK, 0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x70000, .len = 0xd4, + .features = PINGPONG_SDM845_TE2_MASK, + .sblk = &sdm845_pp_sblk_te, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x70800, .len = 0xd4, + .features = PINGPONG_SDM845_TE2_MASK, + .sblk = &sdm845_pp_sblk_te, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), + }, { + .name = "pingpong_2", .id = PINGPONG_2, + .base = 0x71000, .len = 0xd4, + .features = PINGPONG_SDM845_MASK, + .sblk = &sdm845_pp_sblk, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), + }, { + .name = "pingpong_3", .id = PINGPONG_3, + .base = 0x71800, .len = 0xd4, + .features = PINGPONG_SDM845_MASK, + .sblk = &sdm845_pp_sblk, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), + }, }; static const struct dpu_dsc_cfg sdm845_dsc[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 0665cfb32429..1ec85d5dd0eb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -218,24 +218,55 @@ static const struct dpu_dspp_cfg sm8150_dspp[] = { }; static const struct dpu_pingpong_cfg sm8150_pp[] = { - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - -1), - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - -1), - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - -1), - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - -1), - PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), - -1), - PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), - -1), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x70000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = -1, + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x70800, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr = -1, + }, { + .name = "pingpong_2", .id = PINGPONG_2, + .base = 0x71000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + .intr_rdptr = -1, + }, { + .name = "pingpong_3", .id = PINGPONG_3, + .base = 0x71800, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + .intr_rdptr = -1, + }, { + .name = "pingpong_4", .id = PINGPONG_4, + .base = 0x72000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + .intr_rdptr = -1, + }, { + .name = "pingpong_5", .id = PINGPONG_5, + .base = 0x72800, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + .intr_rdptr = -1, + }, }; static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 4babe9bd5a31..38bef6951349 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -217,24 +217,55 @@ static const struct dpu_dspp_cfg sc8180x_dspp[] = { }; static const struct dpu_pingpong_cfg sc8180x_pp[] = { - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - -1), - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - -1), - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - -1), - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - -1), - PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), - -1), - PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), - -1), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x70000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = -1, + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x70800, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr = -1, + }, { + .name = "pingpong_2", .id = PINGPONG_2, + .base = 0x71000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + .intr_rdptr = -1, + }, { + .name = "pingpong_3", .id = PINGPONG_3, + .base = 0x71800, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + .intr_rdptr = -1, + }, { + .name = "pingpong_4", .id = PINGPONG_4, + .base = 0x72000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + .intr_rdptr = -1, + }, { + .name = "pingpong_5", .id = PINGPONG_5, + .base = 0x72800, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + .intr_rdptr = -1, + }, }; static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 77586b41838d..b9ea2755eefa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -218,24 +218,55 @@ static const struct dpu_dspp_cfg sm8250_dspp[] = { }; static const struct dpu_pingpong_cfg sm8250_pp[] = { - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - -1), - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, MERGE_3D_0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - -1), - PP_BLK("pingpong_2", PINGPONG_2, 0x71000, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - -1), - PP_BLK("pingpong_3", PINGPONG_3, 0x71800, PINGPONG_SM8150_MASK, MERGE_3D_1, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - -1), - PP_BLK("pingpong_4", PINGPONG_4, 0x72000, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), - -1), - PP_BLK("pingpong_5", PINGPONG_5, 0x72800, PINGPONG_SM8150_MASK, MERGE_3D_2, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), - -1), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x70000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = -1, + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x70800, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr = -1, + }, { + .name = "pingpong_2", .id = PINGPONG_2, + .base = 0x71000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + .intr_rdptr = -1, + }, { + .name = "pingpong_3", .id = PINGPONG_3, + .base = 0x71800, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + .intr_rdptr = -1, + }, { + .name = "pingpong_4", .id = PINGPONG_4, + .base = 0x72000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + .intr_rdptr = -1, + }, { + .name = "pingpong_5", .id = PINGPONG_5, + .base = 0x72800, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + .intr_rdptr = -1, + }, }; static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 4a1741ee5c4b..652cf2f80dfb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -118,12 +118,23 @@ static const struct dpu_dspp_cfg sc7180_dspp[] = { }; static const struct dpu_pingpong_cfg sc7180_pp[] = { - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - -1), - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - -1), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x70000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = 0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = -1, + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x70800, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = 0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr = -1, + }, }; static const struct dpu_intf_cfg sc7180_intf[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index ccfb3575d8bb..a43a1595b0d8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -82,9 +82,15 @@ static const struct dpu_dspp_cfg sm6115_dspp[] = { }; static const struct dpu_pingpong_cfg sm6115_pp[] = { - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - -1), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x70000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = 0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = -1, + }, }; static const struct dpu_intf_cfg sm6115_intf[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 6b41adf42173..eb01adef6a17 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -127,12 +127,23 @@ static const struct dpu_dspp_cfg sm6350_dspp[] = { }; static struct dpu_pingpong_cfg sm6350_pp[] = { - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - -1), - PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - -1), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x70000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = 0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = -1, + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x70800, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = 0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr = -1, + }, }; static const struct dpu_dsc_cfg sm6350_dsc[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index 75389f720736..f858514837b1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -79,9 +79,15 @@ static const struct dpu_dspp_cfg qcm2290_dspp[] = { }; static const struct dpu_pingpong_cfg qcm2290_pp[] = { - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - -1), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x70000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = 0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = -1, + }, }; static const struct dpu_intf_cfg qcm2290_intf[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index f988ab076a58..989fefa6ac36 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -84,9 +84,15 @@ static const struct dpu_dspp_cfg sm6375_dspp[] = { }; static const struct dpu_pingpong_cfg sm6375_pp[] = { - PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - -1), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x70000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .sblk = &sdm845_pp_sblk, + .merge_3d = 0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = -1, + }, }; static const struct dpu_dsc_cfg sm6375_dsc[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 696aa70da08f..f5b0fd68b87a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -216,24 +216,55 @@ static const struct dpu_dspp_cfg sm8350_dspp[] = { }; static const struct dpu_pingpong_cfg sm8350_pp[] = { - PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - -1), - PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - -1), - PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - -1), - PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - -1), - PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), - -1), - PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), - -1), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x69000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = -1, + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x6a000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr = -1, + }, { + .name = "pingpong_2", .id = PINGPONG_2, + .base = 0x6b000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + .intr_rdptr = -1, + }, { + .name = "pingpong_3", .id = PINGPONG_3, + .base = 0x6c000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + .intr_rdptr = -1, + }, { + .name = "pingpong_4", .id = PINGPONG_4, + .base = 0x6d000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + .intr_rdptr = -1, + }, { + .name = "pingpong_5", .id = PINGPONG_5, + .base = 0x6e000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + .intr_rdptr = -1, + }, }; static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 4494f3ba1e4e..8129a327c575 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -130,18 +130,39 @@ static const struct dpu_dspp_cfg sc7280_dspp[] = { }; static const struct dpu_pingpong_cfg sc7280_pp[] = { - PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - -1), - PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - -1), - PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - -1), - PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - -1), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x69000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = 0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = -1, + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x6a000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = 0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr = -1, + }, { + .name = "pingpong_2", .id = PINGPONG_2, + .base = 0x6b000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = 0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + .intr_rdptr = -1, + }, { + .name = "pingpong_3", .id = PINGPONG_3, + .base = 0x6c000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = 0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + .intr_rdptr = -1, + }, }; /* NOTE: sc7280 only has one DSC hard slice encoder */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index ae43dad40a15..7a5ebc4e6658 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -220,18 +220,55 @@ static const struct dpu_dspp_cfg sc8280xp_dspp[] = { }; static const struct dpu_pingpong_cfg sc8280xp_pp[] = { - PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1), - PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1), - PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1), - PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1), - PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1), - PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x69000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = -1, + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x6a000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr = -1, + }, { + .name = "pingpong_2", .id = PINGPONG_2, + .base = 0x6b000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + .intr_rdptr = -1, + }, { + .name = "pingpong_3", .id = PINGPONG_3, + .base = 0x6c000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + .intr_rdptr = -1, + }, { + .name = "pingpong_4", .id = PINGPONG_4, + .base = 0x6d000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + .intr_rdptr = -1, + }, { + .name = "pingpong_5", .id = PINGPONG_5, + .base = 0x6e000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + .intr_rdptr = -1, + }, }; static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 21a9fa764f83..e75939e2c25a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -220,30 +220,71 @@ static const struct dpu_dspp_cfg sm8450_dspp[] = { }; static const struct dpu_pingpong_cfg sm8450_pp[] = { - PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - -1), - PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - -1), - PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - -1), - PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - -1), - PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), - -1), - PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), - -1), - PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sc7280_pp_sblk, - -1, - -1), - PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sc7280_pp_sblk, - -1, - -1), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x69000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = -1, + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x6a000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr = -1, + }, { + .name = "pingpong_2", .id = PINGPONG_2, + .base = 0x6b000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + .intr_rdptr = -1, + }, { + .name = "pingpong_3", .id = PINGPONG_3, + .base = 0x6c000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + .intr_rdptr = -1, + }, { + .name = "pingpong_4", .id = PINGPONG_4, + .base = 0x6d000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + .intr_rdptr = -1, + }, { + .name = "pingpong_5", .id = PINGPONG_5, + .base = 0x6e000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + .intr_rdptr = -1, + }, { + .name = "pingpong_6", .id = PINGPONG_6, + .base = 0x65800, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_3, + .intr_done = -1, + .intr_rdptr = -1, + }, { + .name = "pingpong_7", .id = PINGPONG_7, + .base = 0x65c00, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_3, + .intr_done = -1, + .intr_rdptr = -1, + }, }; static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index eea51a13ecde..3cc951eca09b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -234,30 +234,71 @@ static const struct dpu_dspp_cfg sm8550_dspp[] = { }, }; static const struct dpu_pingpong_cfg sm8550_pp[] = { - PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - -1), - PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - -1), - PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - -1), - PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - -1), - PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), - -1), - PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), - -1), - PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk, - -1, - -1), - PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk, - -1, - -1), + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x69000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = -1, + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x6a000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr = -1, + }, { + .name = "pingpong_2", .id = PINGPONG_2, + .base = 0x6b000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + .intr_rdptr = -1, + }, { + .name = "pingpong_3", .id = PINGPONG_3, + .base = 0x6c000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + .intr_rdptr = -1, + }, { + .name = "pingpong_4", .id = PINGPONG_4, + .base = 0x6d000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + .intr_rdptr = -1, + }, { + .name = "pingpong_5", .id = PINGPONG_5, + .base = 0x6e000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + .intr_rdptr = -1, + }, { + .name = "pingpong_6", .id = PINGPONG_6, + .base = 0x66000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_3, + .intr_done = -1, + .intr_rdptr = -1, + }, { + .name = "pingpong_7", .id = PINGPONG_7, + .base = 0x66400, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_3, + .intr_done = -1, + .intr_rdptr = -1, + }, }; static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index b1c96cd9a67b..5f56d87cbdda 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -450,27 +450,6 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { .len = 0x20, .version = 0x20000}, }; -#define PP_BLK_DITHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ - {\ - .name = _name, .id = _id, \ - .base = _base, .len = 0, \ - .features = BIT(DPU_PINGPONG_DITHER), \ - .merge_3d = _merge_3d, \ - .sblk = &_sblk, \ - .intr_done = _done, \ - .intr_rdptr = _rdptr, \ - } -#define PP_BLK(_name, _id, _base, _features, _merge_3d, _sblk, _done, _rdptr) \ - {\ - .name = _name, .id = _id, \ - .base = _base, .len = 0xd4, \ - .features = _features, \ - .merge_3d = _merge_3d, \ - .sblk = &_sblk, \ - .intr_done = _done, \ - .intr_rdptr = _rdptr, \ - } - /************************************************************* * DSC sub blocks config *************************************************************/ From 36e2ad1d727ad930b2c4e44ad1ae82ff03b9ff8d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:33 +0300 Subject: [PATCH 025/118] drm/msm/dpu: inline WB_BLK macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten Reviewed-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545380/ Link: https://lore.kernel.org/r/20230704022136.130522-17-dmitry.baryshkov@linaro.org --- .../drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 14 ++++++++++++-- .../drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 14 ++++++++++++-- .../drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 14 ++++++++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 18 ------------------ 4 files changed, 36 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index b9ea2755eefa..42c993ca1b2e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -323,8 +323,18 @@ static const struct dpu_intf_cfg sm8250_intf[] = { }; static const struct dpu_wb_cfg sm8250_wb[] = { - WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6, - VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4), + { + .name = "wb_2", .id = WB_2, + .base = 0x65000, .len = 0x2c8, + .features = WB_SM8250_MASK, + .format_list = wb2_formats, + .num_formats = ARRAY_SIZE(wb2_formats), + .clk_ctrl = DPU_CLK_CTRL_WB2, + .xin_id = 6, + .vbif_idx = VBIF_RT, + .maxlinewidth = 4096, + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, }; static const struct dpu_perf_cfg sm8250_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 652cf2f80dfb..387bddc85a84 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -148,8 +148,18 @@ static const struct dpu_intf_cfg sc7180_intf[] = { }; static const struct dpu_wb_cfg sc7180_wb[] = { - WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6, - VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4), + { + .name = "wb_2", .id = WB_2, + .base = 0x65000, .len = 0x2c8, + .features = WB_SM8250_MASK, + .format_list = wb2_formats, + .num_formats = ARRAY_SIZE(wb2_formats), + .clk_ctrl = DPU_CLK_CTRL_WB2, + .xin_id = 6, + .vbif_idx = VBIF_RT, + .maxlinewidth = 4096, + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, }; static const struct dpu_perf_cfg sc7180_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 8129a327c575..a775b357abcb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -176,8 +176,18 @@ static const struct dpu_dsc_cfg sc7280_dsc[] = { }; static const struct dpu_wb_cfg sc7280_wb[] = { - WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6, - VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4), + { + .name = "wb_2", .id = WB_2, + .base = 0x65000, .len = 0x2c8, + .features = WB_SM8250_MASK, + .format_list = wb2_formats, + .num_formats = ARRAY_SIZE(wb2_formats), + .clk_ctrl = DPU_CLK_CTRL_WB2, + .xin_id = 6, + .vbif_idx = VBIF_RT, + .maxlinewidth = 4096, + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, }; static const struct dpu_intf_cfg sc7280_intf[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 5f56d87cbdda..d9558b01fe5f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -493,24 +493,6 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = { .intr_tear_rd_ptr = _tear_rd_ptr, \ } -/************************************************************* - * Writeback blocks config - *************************************************************/ -#define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \ - __xin_id, vbif_id, _reg, _max_linewidth, _wb_done_bit) \ - { \ - .name = _name, .id = _id, \ - .base = _base, .len = 0x2c8, \ - .features = _features, \ - .format_list = wb2_formats, \ - .num_formats = ARRAY_SIZE(wb2_formats), \ - .clk_ctrl = _clk_ctrl, \ - .xin_id = __xin_id, \ - .vbif_idx = vbif_id, \ - .maxlinewidth = _max_linewidth, \ - .intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \ - } - /************************************************************* * VBIF sub blocks config *************************************************************/ From ed4fa8c60e45b731fb7bd97b71b18379402042ce Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:34 +0300 Subject: [PATCH 026/118] drm/msm/dpu: inline INTF_BLK and INTF_BLK_DSI_TE macros To simplify making changes to the hardware block definitions, expand corresponding macros. This way making all the changes are more obvious and visible in the source files. Tested-by: Marijn Suijten Reviewed-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545378/ Link: https://lore.kernel.org/r/20230704022136.130522-18-dmitry.baryshkov@linaro.org --- .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 52 ++++++-- .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 53 ++++++-- .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 55 ++++++-- .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 82 +++++++++--- .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 55 ++++++-- .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 28 +++- .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 15 ++- .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 28 +++- .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 15 ++- .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 15 ++- .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 55 ++++++-- .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 41 ++++-- .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 120 +++++++++++++----- .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 55 ++++++-- .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 55 ++++++-- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 30 ----- 16 files changed, 545 insertions(+), 209 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 9181d3ef8013..4ce25ed4e36f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -241,18 +241,46 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = { }; static const struct dpu_intf_cfg msm8998_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 21, INTF_SDM845_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 21, INTF_SDM845_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)), - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 21, INTF_SDM845_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)), - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, INTF_SDM845_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), + { + .name = "intf_0", .id = INTF_0, + .base = 0x6a000, .len = 0x280, + .features = INTF_SDM845_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 21, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x6a800, .len = 0x280, + .features = INTF_SDM845_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 21, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_2", .id = INTF_2, + .base = 0x6b000, .len = 0x280, + .features = INTF_SDM845_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case = 21, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_3", .id = INTF_3, + .base = 0x6b800, .len = 0x280, + .features = INTF_SDM845_MASK, + .type = INTF_HDMI, + .prog_fetch_lines_worst_case = 21, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + .intr_tear_rd_ptr = -1, + }, }; static const struct dpu_perf_cfg msm8998_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index cbde4e3464a8..dc760a3d3425 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -257,18 +257,47 @@ static const struct dpu_dsc_cfg sdm845_dsc[] = { }; static const struct dpu_intf_cfg sdm845_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SDM845_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SDM845_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)), - INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SDM845_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)), - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SDM845_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), + { + .name = "intf_0", .id = INTF_0, + .base = 0x6a000, .len = 0x280, + .features = INTF_SDM845_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x6a800, .len = 0x280, + .features = INTF_SDM845_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_2", .id = INTF_2, + .base = 0x6b000, .len = 0x280, + .features = INTF_SDM845_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_3", .id = INTF_3, + .base = 0x6b800, .len = 0x280, + .features = INTF_SDM845_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + .intr_tear_rd_ptr = -1, + }, }; static const struct dpu_perf_cfg sdm845_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 1ec85d5dd0eb..f572c773f0d3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -306,20 +306,47 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = { }; static const struct dpu_intf_cfg sm8150_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)), - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), + { + .name = "intf_0", .id = INTF_0, + .base = 0x6a000, .len = 0x280, + .features = INTF_SC7180_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x6a800, .len = 0x2bc, + .features = INTF_SC7180_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name = "intf_2", .id = INTF_2, + .base = 0x6b000, .len = 0x2bc, + .features = INTF_SC7180_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name = "intf_3", .id = INTF_3, + .base = 0x6b800, .len = 0x280, + .features = INTF_SC7180_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + .intr_tear_rd_ptr = -1, + }, }; static const struct dpu_perf_cfg sm8150_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 38bef6951349..ad63aa89bcf4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -313,27 +313,69 @@ static const struct dpu_dsc_cfg sc8180x_dsc[] = { }; static const struct dpu_intf_cfg sc8180x_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)), + { + .name = "intf_0", .id = INTF_0, + .base = 0x6a000, .len = 0x280, + .features = INTF_SC7180_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x6a800, .len = 0x2bc, + .features = INTF_SC7180_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name = "intf_2", .id = INTF_2, + .base = 0x6b000, .len = 0x2bc, + .features = INTF_SC7180_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */ - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 999, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), - INTF_BLK("intf_4", INTF_4, 0x6c000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21)), - INTF_BLK("intf_5", INTF_5, 0x6c800, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)), + { + .name = "intf_3", .id = INTF_3, + .base = 0x6b800, .len = 0x280, + .features = INTF_SC7180_MASK, + .type = INTF_DP, + .controller_id = 999, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_4", .id = INTF_4, + .base = 0x6c000, .len = 0x280, + .features = INTF_SC7180_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_5", .id = INTF_5, + .base = 0x6c800, .len = 0x280, + .features = INTF_SC7180_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_2, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), + .intr_tear_rd_ptr = -1, + }, }; static const struct dpu_perf_cfg sc8180x_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 42c993ca1b2e..a9d8abef5145 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -306,20 +306,47 @@ static const struct dpu_dsc_cfg sm8250_dsc[] = { }; static const struct dpu_intf_cfg sm8250_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)), - INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), + { + .name = "intf_0", .id = INTF_0, + .base = 0x6a000, .len = 0x280, + .features = INTF_SC7180_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x6a800, .len = 0x2c0, + .features = INTF_SC7180_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name = "intf_2", .id = INTF_2, + .base = 0x6b000, .len = 0x2c0, + .features = INTF_SC7180_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name = "intf_3", .id = INTF_3, + .base = 0x6b800, .len = 0x280, + .features = INTF_SC7180_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + .intr_tear_rd_ptr = -1, + }, }; static const struct dpu_wb_cfg sm8250_wb[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 387bddc85a84..8c046eacec7c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -138,13 +138,27 @@ static const struct dpu_pingpong_cfg sc7180_pp[] = { }; static const struct dpu_intf_cfg sc7180_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), + { + .name = "intf_0", .id = INTF_0, + .base = 0x6a000, .len = 0x280, + .features = INTF_SC7180_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x6a800, .len = 0x2c0, + .features = INTF_SC7180_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, }; static const struct dpu_wb_cfg sc7180_wb[] = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index a43a1595b0d8..473cdbace322 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -94,10 +94,17 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = { }; static const struct dpu_intf_cfg sm6115_intf[] = { - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), + { + .name = "intf_1", .id = INTF_1, + .base = 0x6a800, .len = 0x2c0, + .features = INTF_SC7180_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, }; static const struct dpu_perf_cfg sm6115_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index eb01adef6a17..ac716c8dbd7f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -155,13 +155,27 @@ static const struct dpu_dsc_cfg sm6350_dsc[] = { }; static const struct dpu_intf_cfg sm6350_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 35, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 35, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), + { + .name = "intf_0", .id = INTF_0, + .base = 0x6a000, .len = 0x280, + .features = INTF_SC7180_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 35, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x6a800, .len = 0x2c0, + .features = INTF_SC7180_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 35, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, }; static const struct dpu_perf_cfg sm6350_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index f858514837b1..7d9fdd807695 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -91,10 +91,17 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] = { }; static const struct dpu_intf_cfg qcm2290_intf[] = { - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), + { + .name = "intf_1", .id = INTF_1, + .base = 0x6a800, .len = 0x2c0, + .features = INTF_SC7180_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, }; static const struct dpu_perf_cfg qcm2290_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 989fefa6ac36..5f36f9468853 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -104,10 +104,17 @@ static const struct dpu_dsc_cfg sm6375_dsc[] = { }; static const struct dpu_intf_cfg sm6375_intf[] = { - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), + { + .name = "intf_1", .id = INTF_1, + .base = 0x6a800, .len = 0x2c0, + .features = INTF_SC7180_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, }; static const struct dpu_perf_cfg sm6375_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index f5b0fd68b87a..beaeb95fe5be 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -313,20 +313,47 @@ static const struct dpu_dsc_cfg sm8350_dsc[] = { }; static const struct dpu_intf_cfg sm8350_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)), - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)), - INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), + { + .name = "intf_0", .id = INTF_0, + .base = 0x34000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x35000, .len = 0x2c4, + .features = INTF_SC7280_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + }, { + .name = "intf_2", .id = INTF_2, + .base = 0x36000, .len = 0x2c4, + .features = INTF_SC7280_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + }, { + .name = "intf_3", .id = INTF_3, + .base = 0x37000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + .intr_tear_rd_ptr = -1, + }, }; static const struct dpu_perf_cfg sm8350_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index a775b357abcb..4b2cc62b07ea 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -191,16 +191,37 @@ static const struct dpu_wb_cfg sc7280_wb[] = { }; static const struct dpu_intf_cfg sc7280_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)), - INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)), + { + .name = "intf_0", .id = INTF_0, + .base = 0x34000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x35000, .len = 0x2c4, + .features = INTF_SC7280_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + }, { + .name = "intf_5", .id = INTF_5, + .base = 0x39000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), + .intr_tear_rd_ptr = -1, + }, }; static const struct dpu_perf_cfg sc7280_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 7a5ebc4e6658..3945fb50bc71 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -328,35 +328,97 @@ static const struct dpu_dsc_cfg sc8280xp_dsc[] = { /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */ static const struct dpu_intf_cfg sc8280xp_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)), - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)), - INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), - INTF_BLK("intf_4", INTF_4, 0x38000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21)), - INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)), - INTF_BLK("intf_6", INTF_6, 0x3a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17)), - INTF_BLK("intf_7", INTF_7, 0x3b000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19)), - INTF_BLK("intf_8", INTF_8, 0x3c000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), + { + .name = "intf_0", .id = INTF_0, + .base = 0x34000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x35000, .len = 0x300, + .features = INTF_SC7280_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + }, { + .name = "intf_2", .id = INTF_2, + .base = 0x36000, .len = 0x300, + .features = INTF_SC7280_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + }, { + .name = "intf_3", .id = INTF_3, + .base = 0x37000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_NONE, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_4", .id = INTF_4, + .base = 0x38000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_5", .id = INTF_5, + .base = 0x39000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_3, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_6", .id = INTF_6, + .base = 0x3a000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_2, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_7", .id = INTF_7, + .base = 0x3b000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_NONE, + .controller_id = MSM_DP_CONTROLLER_2, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_8", .id = INTF_8, + .base = 0x3c000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_NONE, + .controller_id = MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), + .intr_tear_rd_ptr = -1, + }, }; static const struct dpu_perf_cfg sc8280xp_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index e75939e2c25a..8d6095c7e1ad 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -337,20 +337,47 @@ static const struct dpu_dsc_cfg sm8450_dsc[] = { }; static const struct dpu_intf_cfg sm8450_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)), - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)), - INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), + { + .name = "intf_0", .id = INTF_0, + .base = 0x34000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x35000, .len = 0x300, + .features = INTF_SC7280_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + }, { + .name = "intf_2", .id = INTF_2, + .base = 0x36000, .len = 0x300, + .features = INTF_SC7280_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + }, { + .name = "intf_3", .id = INTF_3, + .base = 0x37000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + .intr_tear_rd_ptr = -1, + }, }; static const struct dpu_perf_cfg sm8450_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 3cc951eca09b..d2415a138134 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -351,20 +351,47 @@ static const struct dpu_dsc_cfg sm8550_dsc[] = { }; static const struct dpu_intf_cfg sm8550_intf[] = { - INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), - INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)), - INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)), - INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), - DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), + { + .name = "intf_0", .id = INTF_0, + .base = 0x34000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x35000, .len = 0x300, + .features = INTF_SC7280_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + }, { + .name = "intf_2", .id = INTF_2, + .base = 0x36000, .len = 0x300, + .features = INTF_SC7280_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + }, { + .name = "intf_3", .id = INTF_3, + .base = 0x37000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + .intr_tear_rd_ptr = -1, + }, }; static const struct dpu_perf_cfg sm8550_perf_data = { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index d9558b01fe5f..65704958c34a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -463,36 +463,6 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 = { .ctl = {.base = 0xF80, .len = 0x10}, }; -/************************************************************* - * INTF sub blocks config - *************************************************************/ -#define INTF_BLK(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _underrun, _vsync) \ - {\ - .name = _name, .id = _id, \ - .base = _base, .len = _len, \ - .features = _features, \ - .type = _type, \ - .controller_id = _ctrl_id, \ - .prog_fetch_lines_worst_case = _progfetch, \ - .intr_underrun = _underrun, \ - .intr_vsync = _vsync, \ - .intr_tear_rd_ptr = -1, \ - } - -/* DSI Interface sub-block with TEAR registers (since DPU 5.0.0) */ -#define INTF_BLK_DSI_TE(_name, _id, _base, _len, _type, _ctrl_id, _progfetch, _features, _underrun, _vsync, _tear_rd_ptr) \ - {\ - .name = _name, .id = _id, \ - .base = _base, .len = _len, \ - .features = _features, \ - .type = _type, \ - .controller_id = _ctrl_id, \ - .prog_fetch_lines_worst_case = _progfetch, \ - .intr_underrun = _underrun, \ - .intr_vsync = _vsync, \ - .intr_tear_rd_ptr = _tear_rd_ptr, \ - } - /************************************************************* * VBIF sub blocks config *************************************************************/ From 48cbbe7c7619f1ea36ee4ba21bd3148b89f54b4b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:35 +0300 Subject: [PATCH 027/118] drm/msm/dpu: drop empty features mask MERGE_3D_SM8150_MASK The MERGE_3D_SM8150_MASK features mask is zero. Drop it completely. Reviewed-by: Marijn Suijten Tested-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545384/ Link: https://lore.kernel.org/r/20230704022136.130522-19-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 -- 8 files changed, 25 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index f572c773f0d3..96c542d620f1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -273,15 +273,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { { .name = "merge_3d_0", .id = MERGE_3D_0, .base = 0x83000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_1", .id = MERGE_3D_1, .base = 0x83100, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_2", .id = MERGE_3D_2, .base = 0x83200, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index ad63aa89bcf4..4edc1060f05c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -272,15 +272,12 @@ static const struct dpu_merge_3d_cfg sc8180x_merge_3d[] = { { .name = "merge_3d_0", .id = MERGE_3D_0, .base = 0x83000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_1", .id = MERGE_3D_1, .base = 0x83100, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_2", .id = MERGE_3D_2, .base = 0x83200, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index a9d8abef5145..f8910dbc1952 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -273,15 +273,12 @@ static const struct dpu_merge_3d_cfg sm8250_merge_3d[] = { { .name = "merge_3d_0", .id = MERGE_3D_0, .base = 0x83000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_1", .id = MERGE_3D_1, .base = 0x83100, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_2", .id = MERGE_3D_2, .base = 0x83200, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index beaeb95fe5be..b22e6b97c993 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -271,15 +271,12 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = { { .name = "merge_3d_0", .id = MERGE_3D_0, .base = 0x4e000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_1", .id = MERGE_3D_1, .base = 0x4f000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_2", .id = MERGE_3D_2, .base = 0x50000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 3945fb50bc71..ec959f85ae2a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -275,15 +275,12 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = { { .name = "merge_3d_0", .id = MERGE_3D_0, .base = 0x4e000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_1", .id = MERGE_3D_1, .base = 0x4f000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_2", .id = MERGE_3D_2, .base = 0x50000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 8d6095c7e1ad..98a4aaef94d2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -291,19 +291,15 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { { .name = "merge_3d_0", .id = MERGE_3D_0, .base = 0x4e000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_1", .id = MERGE_3D_1, .base = 0x4f000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_2", .id = MERGE_3D_2, .base = 0x50000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_3", .id = MERGE_3D_3, .base = 0x65f00, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index d2415a138134..7de9eccf9181 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -305,19 +305,15 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { { .name = "merge_3d_0", .id = MERGE_3D_0, .base = 0x4e000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_1", .id = MERGE_3D_1, .base = 0x4f000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_2", .id = MERGE_3D_2, .base = 0x50000, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, { .name = "merge_3d_3", .id = MERGE_3D_3, .base = 0x66700, .len = 0x8, - .features = MERGE_3D_SM8150_MASK, }, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 65704958c34a..76417959e9f3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -93,8 +93,6 @@ #define CTL_SM8550_MASK \ (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4)) -#define MERGE_3D_SM8150_MASK (0) - #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) #define INTF_SDM845_MASK (0) From 1fe519aad840ba687faf40bff044b026a293ba4a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 4 Jul 2023 05:21:36 +0300 Subject: [PATCH 028/118] drm/msm/dpu: drop empty features mask INTF_SDM845_MASK The INTF_SDM845_MASK features mask is zero. Drop it completely. Reviewed-by: Marijn Suijten Tested-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/545386/ Link: https://lore.kernel.org/r/20230704022136.130522-20-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 -- 3 files changed, 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 4ce25ed4e36f..7d87dc2d7b1b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -244,7 +244,6 @@ static const struct dpu_intf_cfg msm8998_intf[] = { { .name = "intf_0", .id = INTF_0, .base = 0x6a000, .len = 0x280, - .features = INTF_SDM845_MASK, .type = INTF_DP, .controller_id = MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case = 21, @@ -254,7 +253,6 @@ static const struct dpu_intf_cfg msm8998_intf[] = { }, { .name = "intf_1", .id = INTF_1, .base = 0x6a800, .len = 0x280, - .features = INTF_SDM845_MASK, .type = INTF_DSI, .controller_id = MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case = 21, @@ -264,7 +262,6 @@ static const struct dpu_intf_cfg msm8998_intf[] = { }, { .name = "intf_2", .id = INTF_2, .base = 0x6b000, .len = 0x280, - .features = INTF_SDM845_MASK, .type = INTF_DSI, .controller_id = MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case = 21, @@ -274,7 +271,6 @@ static const struct dpu_intf_cfg msm8998_intf[] = { }, { .name = "intf_3", .id = INTF_3, .base = 0x6b800, .len = 0x280, - .features = INTF_SDM845_MASK, .type = INTF_HDMI, .prog_fetch_lines_worst_case = 21, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index dc760a3d3425..87459cf40895 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -260,7 +260,6 @@ static const struct dpu_intf_cfg sdm845_intf[] = { { .name = "intf_0", .id = INTF_0, .base = 0x6a000, .len = 0x280, - .features = INTF_SDM845_MASK, .type = INTF_DP, .controller_id = MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case = 24, @@ -270,7 +269,6 @@ static const struct dpu_intf_cfg sdm845_intf[] = { }, { .name = "intf_1", .id = INTF_1, .base = 0x6a800, .len = 0x280, - .features = INTF_SDM845_MASK, .type = INTF_DSI, .controller_id = MSM_DSI_CONTROLLER_0, .prog_fetch_lines_worst_case = 24, @@ -280,7 +278,6 @@ static const struct dpu_intf_cfg sdm845_intf[] = { }, { .name = "intf_2", .id = INTF_2, .base = 0x6b000, .len = 0x280, - .features = INTF_SDM845_MASK, .type = INTF_DSI, .controller_id = MSM_DSI_CONTROLLER_1, .prog_fetch_lines_worst_case = 24, @@ -290,7 +287,6 @@ static const struct dpu_intf_cfg sdm845_intf[] = { }, { .name = "intf_3", .id = INTF_3, .base = 0x6b800, .len = 0x280, - .features = INTF_SDM845_MASK, .type = INTF_DP, .controller_id = MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case = 24, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 76417959e9f3..fdd1562bef13 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -95,8 +95,6 @@ #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) -#define INTF_SDM845_MASK (0) - #define INTF_SC7180_MASK \ (BIT(DPU_INTF_INPUT_CTRL) | \ BIT(DPU_INTF_TE) | \ From 903705111d863ed8ccf73465da77d232fc422ec1 Mon Sep 17 00:00:00 2001 From: Ryan McCann Date: Fri, 7 Jul 2023 18:24:40 -0700 Subject: [PATCH 029/118] drm/msm: Update dev core dump to not print backwards Device core dump add block method adds hardware blocks to dumping queue with stack behavior which causes the hardware blocks to be printed in reverse order. Change the addition to dumping queue data structure from "list_add" to "list_add_tail" for FIFO queue behavior. Fixes: 98659487b845 ("drm/msm: add support to take dpu snapshot") Reviewed-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Signed-off-by: Ryan McCann Patchwork: https://patchwork.freedesktop.org/patch/546200/ Link: https://lore.kernel.org/r/20230622-devcoredump_patch-v5-1-67e8b66c4723@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c b/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c index acfe1b31e079..add72bbc28b1 100644 --- a/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c +++ b/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c @@ -192,5 +192,5 @@ void msm_disp_snapshot_add_block(struct msm_disp_state *disp_state, u32 len, new_blk->base_addr = base_addr; msm_disp_state_dump_regs(&new_blk->state, new_blk->size, base_addr); - list_add(&new_blk->node, &disp_state->blocks); + list_add_tail(&new_blk->node, &disp_state->blocks); } From 1071a22c0dd5d3f31fee5445374bfe706e4a34db Mon Sep 17 00:00:00 2001 From: Ryan McCann Date: Fri, 7 Jul 2023 18:24:41 -0700 Subject: [PATCH 030/118] drm/msm/dpu: Drop unused num argument from relevant macros Drop unused parameter "num" from VIG_SBLK_NOSCALE and DMA sub-block macros. Update calls to relevant macros to reflect change. Reviewed-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Signed-off-by: Ryan McCann Patchwork: https://patchwork.freedesktop.org/patch/546196/ Link: https://lore.kernel.org/r/20230622-devcoredump_patch-v5-2-67e8b66c4723@quicinc.com Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index fdd1562bef13..95305e10fc4a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -284,7 +284,7 @@ static const uint32_t wb2_formats[] = { .rotation_cfg = rot_cfg, \ } -#define _DMA_SBLK(num, sdma_pri) \ +#define _DMA_SBLK(sdma_pri) \ { \ .maxdwnscale = SSPP_UNITY_SCALE, \ .maxupscale = SSPP_UNITY_SCALE, \ @@ -319,10 +319,10 @@ static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(1); +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(2); +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK(3); +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK(4); static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4); @@ -350,10 +350,10 @@ static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 = _VIG_SBLK("2", 9, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 = _VIG_SBLK("3", 10, DPU_SSPP_SCALER_QSEED4); -static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5); -static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK("13", 6); +static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK(5); +static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK(6); -#define _VIG_SBLK_NOSCALE(num, sdma_pri) \ +#define _VIG_SBLK_NOSCALE(sdma_pri) \ { \ .maxdwnscale = SSPP_UNITY_SCALE, \ .maxupscale = SSPP_UNITY_SCALE, \ @@ -364,8 +364,8 @@ static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK("13", 6); .virt_num_formats = ARRAY_SIZE(plane_formats), \ } -static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0", 2); -static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1); +static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE(2); +static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK(1); /************************************************************* * MIXER sub blocks config From 46998bf8431c30879be29bbbf67eefb583136ccb Mon Sep 17 00:00:00 2001 From: Ryan McCann Date: Fri, 7 Jul 2023 18:24:42 -0700 Subject: [PATCH 031/118] drm/msm/dpu: Define names for unnamed sblks Some sub-blocks in the hw catalog have not been given a name, so when the registers from that block are dumped, there is no name to reference. Define names for relevant sub-blocks to fix this. Reviewed-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Signed-off-by: Ryan McCann Patchwork: https://patchwork.freedesktop.org/patch/546199/ Link: https://lore.kernel.org/r/20230622-devcoredump_patch-v5-3-67e8b66c4723@quicinc.com Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 95305e10fc4a..32ac754163ec 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -417,12 +417,12 @@ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { * DSPP sub blocks config *************************************************************/ static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { - .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, + .pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700, .len = 0x90, .version = 0x10007}, }; static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = { - .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, + .pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700, .len = 0x90, .version = 0x40000}, }; @@ -430,19 +430,19 @@ static const struct dpu_dspp_sub_blks sdm845_dspp_sblk = { * PINGPONG sub blocks config *************************************************************/ static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { - .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, + .te2 = {.name = "te2", .id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, .version = 0x1}, - .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, + .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0, .len = 0x20, .version = 0x10000}, }; static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { - .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, + .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0, .len = 0x20, .version = 0x10000}, }; static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { - .dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0, + .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0xe0, .len = 0x20, .version = 0x20000}, }; @@ -450,13 +450,13 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { * DSC sub blocks config *************************************************************/ static const struct dpu_dsc_sub_blks dsc_sblk_0 = { - .enc = {.base = 0x100, .len = 0x100}, - .ctl = {.base = 0xF00, .len = 0x10}, + .enc = {.name = "enc", .base = 0x100, .len = 0x100}, + .ctl = {.name = "ctl", .base = 0xF00, .len = 0x10}, }; static const struct dpu_dsc_sub_blks dsc_sblk_1 = { - .enc = {.base = 0x200, .len = 0x100}, - .ctl = {.base = 0xF80, .len = 0x10}, + .enc = {.name = "enc", .base = 0x200, .len = 0x100}, + .ctl = {.name = "ctl", .base = 0xF80, .len = 0x10}, }; /************************************************************* From 274909a85ebedb3d0da33cb0b21d98dc82a5f111 Mon Sep 17 00:00:00 2001 From: Ryan McCann Date: Fri, 7 Jul 2023 18:24:43 -0700 Subject: [PATCH 032/118] drm/msm/dpu: Remove redundant prefix/suffix in name of sub-blocks For a device core dump, the registers of sub-blocks are printed under a title formatted as . For example, the csc sub-block for an SSPP main block "sspp_0" would be printed "sspp_0_sspp_csc0". The title is clearly redundant due to the duplicate "sspp" and "0" that exist in both the mainBlkName and sblkName. To eliminate this redundancy, remove the secondary "sspp" and "0" that exist in the sub-block name by elimanting the "sspp_" prefix and the concatenation of "num" that results in the redundant "0" suffix. Remove num parameter altogether from relevant macros as a consequence of it no longer being used. Reviewed-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Signed-off-by: Ryan McCann Patchwork: https://patchwork.freedesktop.org/patch/546198/ Link: https://lore.kernel.org/r/20230622-devcoredump_patch-v5-4-67e8b66c4723@quicinc.com Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 50 +++++++++---------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 32ac754163ec..3f545e8609ab 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -248,15 +248,15 @@ static const uint32_t wb2_formats[] = { *************************************************************/ /* SSPP common configuration */ -#define _VIG_SBLK(num, sdma_pri, qseed_ver) \ +#define _VIG_SBLK(sdma_pri, qseed_ver) \ { \ .maxdwnscale = MAX_DOWNSCALE_RATIO, \ .maxupscale = MAX_UPSCALE_RATIO, \ .smart_dma_priority = sdma_pri, \ - .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ + .scaler_blk = {.name = "scaler", \ .id = qseed_ver, \ .base = 0xa00, .len = 0xa0,}, \ - .csc_blk = {.name = STRCAT("sspp_csc", num), \ + .csc_blk = {.name = "csc", \ .id = DPU_SSPP_CSC_10BIT, \ .base = 0x1a00, .len = 0x100,}, \ .format_list = plane_formats_yuv, \ @@ -266,15 +266,15 @@ static const uint32_t wb2_formats[] = { .rotation_cfg = NULL, \ } -#define _VIG_SBLK_ROT(num, sdma_pri, qseed_ver, rot_cfg) \ +#define _VIG_SBLK_ROT(sdma_pri, qseed_ver, rot_cfg) \ { \ .maxdwnscale = MAX_DOWNSCALE_RATIO, \ .maxupscale = MAX_UPSCALE_RATIO, \ .smart_dma_priority = sdma_pri, \ - .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ + .scaler_blk = {.name = "scaler", \ .id = qseed_ver, \ .base = 0xa00, .len = 0xa0,}, \ - .csc_blk = {.name = STRCAT("sspp_csc", num), \ + .csc_blk = {.name = "csc", \ .id = DPU_SSPP_CSC_10BIT, \ .base = 0x1a00, .len = 0x100,}, \ .format_list = plane_formats_yuv, \ @@ -296,13 +296,13 @@ static const uint32_t wb2_formats[] = { } static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = - _VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = - _VIG_SBLK("1", 0, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = - _VIG_SBLK("2", 0, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = - _VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { .rot_maxheight = 1088, @@ -311,13 +311,13 @@ static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { }; static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = - _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = - _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = - _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = - _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(1); static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(2); @@ -325,31 +325,31 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK(3); static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK(4); static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = - _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(4, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = - _VIG_SBLK_ROT("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); + _VIG_SBLK_ROT(4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = - _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = - _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = - _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 = - _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = - _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 = - _VIG_SBLK("0", 7, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 = - _VIG_SBLK("1", 8, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 = - _VIG_SBLK("2", 9, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(9, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 = - _VIG_SBLK("3", 10, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK(5); static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK(6); From ec059976c193b6cd6d7eab88a7b692c4268aeb17 Mon Sep 17 00:00:00 2001 From: Ryan McCann Date: Fri, 7 Jul 2023 18:24:44 -0700 Subject: [PATCH 033/118] drm/msm/dpu: Refactor printing of main blocks in device core dump Currently, the names of main blocks are hardcoded into the msm_disp_snapshot_add_block function rather than using the name that already exists in the catalog. Change this to take the name directly from the catalog instead of hardcoding it. Signed-off-by: Ryan McCann Reviewed-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/546194/ Link: https://lore.kernel.org/r/20230622-devcoredump_patch-v5-5-67e8b66c4723@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index e51bec840e04..f72f2a89ee29 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -898,37 +898,37 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k /* dump CTL sub-blocks HW regs info */ for (i = 0; i < cat->ctl_count; i++) msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len, - dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i); + dpu_kms->mmio + cat->ctl[i].base, cat->ctl[i].name); /* dump DSPP sub-blocks HW regs info */ for (i = 0; i < cat->dspp_count; i++) msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, - dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i); + dpu_kms->mmio + cat->dspp[i].base, cat->dspp[i].name); /* dump INTF sub-blocks HW regs info */ for (i = 0; i < cat->intf_count; i++) msm_disp_snapshot_add_block(disp_state, cat->intf[i].len, - dpu_kms->mmio + cat->intf[i].base, "intf_%d", i); + dpu_kms->mmio + cat->intf[i].base, cat->intf[i].name); /* dump PP sub-blocks HW regs info */ for (i = 0; i < cat->pingpong_count; i++) msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, - dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i); + dpu_kms->mmio + cat->pingpong[i].base, cat->pingpong[i].name); /* dump SSPP sub-blocks HW regs info */ for (i = 0; i < cat->sspp_count; i++) msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, - dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i); + dpu_kms->mmio + cat->sspp[i].base, cat->sspp[i].name); /* dump LM sub-blocks HW regs info */ for (i = 0; i < cat->mixer_count; i++) msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len, - dpu_kms->mmio + cat->mixer[i].base, "lm_%d", i); + dpu_kms->mmio + cat->mixer[i].base, cat->mixer[i].name); /* dump WB sub-blocks HW regs info */ for (i = 0; i < cat->wb_count; i++) msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, - dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); + dpu_kms->mmio + cat->wb[i].base, cat->wb[i].name); if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0, @@ -943,7 +943,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k /* dump DSC sub-blocks HW regs info */ for (i = 0; i < cat->dsc_count; i++) msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, - dpu_kms->mmio + cat->dsc[i].base, "dsc_%d", i); + dpu_kms->mmio + cat->dsc[i].base, cat->dsc[i].name); pm_runtime_put_sync(&dpu_kms->pdev->dev); } From 61e44a5b9b8b8fc61612912f29832bdf010b1591 Mon Sep 17 00:00:00 2001 From: Ryan McCann Date: Fri, 7 Jul 2023 18:24:45 -0700 Subject: [PATCH 034/118] drm/msm/dpu: Update dev core dump to dump registers of sub-blocks Currently, the device core dump mechanism does not dump registers of sub-blocks within the DSPP, SSPP, DSC, and PINGPONG blocks. Edit dpu_kms_mdp_snapshot function to account for sub-blocks. Signed-off-by: Ryan McCann Reviewed-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/546192/ Link: https://lore.kernel.org/r/20230622-devcoredump_patch-v5-6-67e8b66c4723@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 66 ++++++++++++++++++++----- 1 file changed, 54 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index f72f2a89ee29..a5c65eec6f88 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -888,6 +888,7 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k int i; struct dpu_kms *dpu_kms; const struct dpu_mdss_cfg *cat; + void __iomem *base; dpu_kms = to_dpu_kms(kms); @@ -901,9 +902,16 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k dpu_kms->mmio + cat->ctl[i].base, cat->ctl[i].name); /* dump DSPP sub-blocks HW regs info */ - for (i = 0; i < cat->dspp_count; i++) - msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, - dpu_kms->mmio + cat->dspp[i].base, cat->dspp[i].name); + for (i = 0; i < cat->dspp_count; i++) { + base = dpu_kms->mmio + cat->dspp[i].base; + msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, base, cat->dspp[i].name); + + if (cat->dspp[i].sblk && cat->dspp[i].sblk->pcc.len > 0) + msm_disp_snapshot_add_block(disp_state, cat->dspp[i].sblk->pcc.len, + base + cat->dspp[i].sblk->pcc.base, "%s_%s", + cat->dspp[i].name, + cat->dspp[i].sblk->pcc.name); + } /* dump INTF sub-blocks HW regs info */ for (i = 0; i < cat->intf_count; i++) @@ -911,14 +919,37 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k dpu_kms->mmio + cat->intf[i].base, cat->intf[i].name); /* dump PP sub-blocks HW regs info */ - for (i = 0; i < cat->pingpong_count; i++) - msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, - dpu_kms->mmio + cat->pingpong[i].base, cat->pingpong[i].name); + for (i = 0; i < cat->pingpong_count; i++) { + base = dpu_kms->mmio + cat->pingpong[i].base; + msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, base, + cat->pingpong[i].name); + + /* TE2 sub-block has length of 0, so will not print it */ + + if (cat->pingpong[i].sblk && cat->pingpong[i].sblk->dither.len > 0) + msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].sblk->dither.len, + base + cat->pingpong[i].sblk->dither.base, + "%s_%s", cat->pingpong[i].name, + cat->pingpong[i].sblk->dither.name); + } /* dump SSPP sub-blocks HW regs info */ - for (i = 0; i < cat->sspp_count; i++) - msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, - dpu_kms->mmio + cat->sspp[i].base, cat->sspp[i].name); + for (i = 0; i < cat->sspp_count; i++) { + base = dpu_kms->mmio + cat->sspp[i].base; + msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, base, cat->sspp[i].name); + + if (cat->sspp[i].sblk && cat->sspp[i].sblk->scaler_blk.len > 0) + msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->scaler_blk.len, + base + cat->sspp[i].sblk->scaler_blk.base, + "%s_%s", cat->sspp[i].name, + cat->sspp[i].sblk->scaler_blk.name); + + if (cat->sspp[i].sblk && cat->sspp[i].sblk->csc_blk.len > 0) + msm_disp_snapshot_add_block(disp_state, cat->sspp[i].sblk->csc_blk.len, + base + cat->sspp[i].sblk->csc_blk.base, + "%s_%s", cat->sspp[i].name, + cat->sspp[i].sblk->csc_blk.name); + } /* dump LM sub-blocks HW regs info */ for (i = 0; i < cat->mixer_count; i++) @@ -941,9 +972,20 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k } /* dump DSC sub-blocks HW regs info */ - for (i = 0; i < cat->dsc_count; i++) - msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, - dpu_kms->mmio + cat->dsc[i].base, cat->dsc[i].name); + for (i = 0; i < cat->dsc_count; i++) { + base = dpu_kms->mmio + cat->dsc[i].base; + msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, base, cat->dsc[i].name); + + if (cat->dsc[i].features & BIT(DPU_DSC_HW_REV_1_2)) { + struct dpu_dsc_blk enc = cat->dsc[i].sblk->enc; + struct dpu_dsc_blk ctl = cat->dsc[i].sblk->ctl; + + msm_disp_snapshot_add_block(disp_state, enc.len, base + enc.base, "%s_%s", + cat->dsc[i].name, enc.name); + msm_disp_snapshot_add_block(disp_state, ctl.len, base + ctl.base, "%s_%s", + cat->dsc[i].name, ctl.name); + } + } pm_runtime_put_sync(&dpu_kms->pdev->dev); } From cc9a79715a5689822f2ee702414cc995af39a937 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 9 Jul 2023 07:19:22 +0300 Subject: [PATCH 035/118] dt-bindings: display: msm: dp-controller: document SM8250 compatible It looks like DP controlled on SM8250 is the same as DP controller on SM8350. Use the SM8350 compatible as fallback for SM8250. Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Patchwork: https://patchwork.freedesktop.org/patch/546242/ Link: https://lore.kernel.org/r/20230709041926.4052245-2-dmitry.baryshkov@linaro.org --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 7a7cf3fb3e6d..a31ec9a4179f 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -28,6 +28,7 @@ properties: - qcom,sm8350-dp - items: - enum: + - qcom,sm8250-dp - qcom,sm8450-dp - qcom,sm8550-dp - const: qcom,sm8350-dp From b173a7dcc2d06ee11f739c1bdcd51ee156b6d50c Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Tue, 27 Jun 2023 13:31:45 -0700 Subject: [PATCH 036/118] drm/msm/dsi: Enable BURST_MODE for command mode for DSI 6G v1.3+ During a frame transfer in command mode, there could be frequent LP11 <-> HS transitions when multiple DCS commands are sent mid-frame or if the DSI controller is running on slow clock and is throttled. To minimize frame latency due to these transitions, it is recommended to send the frame in a single burst. This feature is supported for DSI 6G 1.3 and above, thus enable burst mode if supported. Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/544551/ Link: https://lore.kernel.org/r/20230608-b4-add-burst-mode-v2-1-2ff468457d46@quicinc.com [DB: fixed indentation] Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 3f6dfb4f9d5a..645927214871 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -752,6 +752,13 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, /* Always insert DCS command */ data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; dsi_write(msm_host, REG_DSI_CMD_CFG1, data); + + if (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G && + msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) { + data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2); + data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE; + dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data); + } } dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, From d5ffd30bf168bf39bc337b38ca172d91d534fa5c Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Tue, 11 Jul 2023 18:19:59 -0700 Subject: [PATCH 037/118] drm/msm/dpu: re-introduce dpu core revision to the catalog Introduce the dpu core revision back as an entry to the catalog so that we can just use dpu revision checks and enable those bits which should be enabled unconditionally and not controlled by a catalog and also simplify the changes to do something like: if (dpu_core_revision > xxxxx && dpu_core_revision < xxxxx) enable the bit; changes in v5: - fix the commit text to remove instances of DPU_HW_VER Reviewed-by: Dmitry Baryshkov Signed-off-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/546801/ Link: https://lore.kernel.org/r/20230712012003.2212-2-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov --- .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 6 ++++++ .../drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 6 ++++++ .../drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ++++++ .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ++++++ .../drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 6 ++++++ .../drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 6 ++++++ .../drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 6 ++++++ .../drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 6 ++++++ .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 6 ++++++ .../drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 6 ++++++ .../drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ++++++ .../drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 6 ++++++ .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 6 ++++++ .../drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 6 ++++++ .../drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 6 ++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 17 +++++++++++++++-- 16 files changed, 105 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 7d87dc2d7b1b..b5fbac55f127 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -315,7 +315,13 @@ static const struct dpu_perf_cfg msm8998_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version msm8998_mdss_ver = { + .core_major_ver = 3, + .core_minor_ver = 0, +}; + const struct dpu_mdss_cfg dpu_msm8998_cfg = { + .mdss_ver = &msm8998_mdss_ver, .caps = &msm8998_dpu_caps, .ubwc = &msm8998_ubwc_cfg, .mdp = &msm8998_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 87459cf40895..8000b870d3a7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -332,7 +332,13 @@ static const struct dpu_perf_cfg sdm845_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version sdm845_mdss_ver = { + .core_major_ver = 4, + .core_minor_ver = 0, +}; + const struct dpu_mdss_cfg dpu_sdm845_cfg = { + .mdss_ver = &sdm845_mdss_ver, .caps = &sdm845_dpu_caps, .ubwc = &sdm845_ubwc_cfg, .mdp = &sdm845_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 96c542d620f1..7ce2d69d28f6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -375,7 +375,13 @@ static const struct dpu_perf_cfg sm8150_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version sm8150_mdss_ver = { + .core_major_ver = 5, + .core_minor_ver = 0, +}; + const struct dpu_mdss_cfg dpu_sm8150_cfg = { + .mdss_ver = &sm8150_mdss_ver, .caps = &sm8150_dpu_caps, .ubwc = &sm8150_ubwc_cfg, .mdp = &sm8150_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 4edc1060f05c..cea005382456 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -402,7 +402,13 @@ static const struct dpu_perf_cfg sc8180x_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version sc8180x_mdss_ver = { + .core_major_ver = 5, + .core_minor_ver = 1, +}; + const struct dpu_mdss_cfg dpu_sc8180x_cfg = { + .mdss_ver = &sc8180x_mdss_ver, .caps = &sc8180x_dpu_caps, .ubwc = &sc8180x_ubwc_cfg, .mdp = &sc8180x_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index f8910dbc1952..893d1271fb71 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -390,7 +390,13 @@ static const struct dpu_perf_cfg sm8250_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version sm8250_mdss_ver = { + .core_major_ver = 6, + .core_minor_ver = 0, +}; + const struct dpu_mdss_cfg dpu_sm8250_cfg = { + .mdss_ver = &sm8250_mdss_ver, .caps = &sm8250_dpu_caps, .ubwc = &sm8250_ubwc_cfg, .mdp = &sm8250_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 8c046eacec7c..61118f648cbc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -204,7 +204,13 @@ static const struct dpu_perf_cfg sc7180_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version sc7180_mdss_ver = { + .core_major_ver = 6, + .core_minor_ver = 2, +}; + const struct dpu_mdss_cfg dpu_sc7180_cfg = { + .mdss_ver = &sc7180_mdss_ver, .caps = &sc7180_dpu_caps, .ubwc = &sc7180_ubwc_cfg, .mdp = &sc7180_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index 473cdbace322..c0d7bb930e8a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -136,7 +136,13 @@ static const struct dpu_perf_cfg sm6115_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version sm6115_mdss_ver = { + .core_major_ver = 6, + .core_minor_ver = 3, +}; + const struct dpu_mdss_cfg dpu_sm6115_cfg = { + .mdss_ver = &sm6115_mdss_ver, .caps = &sm6115_dpu_caps, .ubwc = &sm6115_ubwc_cfg, .mdp = &sm6115_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index ac716c8dbd7f..11c50aa5034b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -207,7 +207,13 @@ static const struct dpu_perf_cfg sm6350_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version sm6350_mdss_ver = { + .core_major_ver = 6, + .core_minor_ver = 4, +}; + const struct dpu_mdss_cfg dpu_sm6350_cfg = { + .mdss_ver = &sm6350_mdss_ver, .caps = &sm6350_dpu_caps, .ubwc = &sm6350_ubwc_cfg, .mdp = &sm6350_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index 7d9fdd807695..2182939bc026 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -126,7 +126,13 @@ static const struct dpu_perf_cfg qcm2290_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version qcm2290_mdss_ver = { + .core_major_ver = 6, + .core_minor_ver = 5, +}; + const struct dpu_mdss_cfg dpu_qcm2290_cfg = { + .mdss_ver = &qcm2290_mdss_ver, .caps = &qcm2290_dpu_caps, .ubwc = &qcm2290_ubwc_cfg, .mdp = &qcm2290_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 5f36f9468853..f0c0aa90f82e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -146,7 +146,13 @@ static const struct dpu_perf_cfg sm6375_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version sm6375_mdss_ver = { + .core_major_ver = 6, + .core_minor_ver = 9, +}; + const struct dpu_mdss_cfg dpu_sm6375_cfg = { + .mdss_ver = &sm6375_mdss_ver, .caps = &sm6375_dpu_caps, .ubwc = &sm6375_ubwc_cfg, .mdp = &sm6375_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index b22e6b97c993..2460ced03610 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -383,7 +383,13 @@ static const struct dpu_perf_cfg sm8350_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version sm8350_mdss_ver = { + .core_major_ver = 7, + .core_minor_ver = 0, +}; + const struct dpu_mdss_cfg dpu_sm8350_cfg = { + .mdss_ver = &sm8350_mdss_ver, .caps = &sm8350_dpu_caps, .ubwc = &sm8350_ubwc_cfg, .mdp = &sm8350_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 4b2cc62b07ea..a8dea8f27c41 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -252,7 +252,13 @@ static const struct dpu_perf_cfg sc7280_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version sc7280_mdss_ver = { + .core_major_ver = 7, + .core_minor_ver = 2, +}; + const struct dpu_mdss_cfg dpu_sc7280_cfg = { + .mdss_ver = &sc7280_mdss_ver, .caps = &sc7280_dpu_caps, .ubwc = &sc7280_ubwc_cfg, .mdp = &sc7280_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index ec959f85ae2a..397fe01125dd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -445,7 +445,13 @@ static const struct dpu_perf_cfg sc8280xp_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version sc8280xp_mdss_ver = { + .core_major_ver = 8, + .core_minor_ver = 0, +}; + const struct dpu_mdss_cfg dpu_sc8280xp_cfg = { + .mdss_ver = &sc8280xp_mdss_ver, .caps = &sc8280xp_dpu_caps, .ubwc = &sc8280xp_ubwc_cfg, .mdp = &sc8280xp_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 98a4aaef94d2..90a8461911c8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -406,7 +406,13 @@ static const struct dpu_perf_cfg sm8450_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version sm8450_mdss_ver = { + .core_major_ver = 8, + .core_minor_ver = 1, +}; + const struct dpu_mdss_cfg dpu_sm8450_cfg = { + .mdss_ver = &sm8450_mdss_ver, .caps = &sm8450_dpu_caps, .ubwc = &sm8450_ubwc_cfg, .mdp = &sm8450_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 7de9eccf9181..c9252528136d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -420,7 +420,13 @@ static const struct dpu_perf_cfg sm8550_perf_data = { .bw_inefficiency_factor = 120, }; +static const struct dpu_mdss_version sm8550_mdss_ver = { + .core_major_ver = 9, + .core_minor_ver = 0, +}; + const struct dpu_mdss_cfg dpu_sm8550_cfg = { + .mdss_ver = &sm8550_mdss_ver, .caps = &sm8550_dpu_caps, .ubwc = &sm8550_ubwc_cfg, .mdp = &sm8550_mdp, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 3b816e36d12d..e455f95456f0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -746,6 +746,16 @@ struct dpu_perf_cdp_cfg { bool wr_enable; }; +/** + * struct dpu_mdss_version - DPU's major and minor versions + * @core_major_ver: DPU core's major version + * @core_minor_ver: DPU core's minor version + */ +struct dpu_mdss_version { + u8 core_major_ver; + u8 core_minor_ver; +}; + /** * struct dpu_perf_cfg - performance control settings * @max_bw_low low threshold of maximum bandwidth (kbps) @@ -796,8 +806,9 @@ struct dpu_perf_cfg { /** * struct dpu_mdss_cfg - information of MDSS HW * This is the main catalog data structure representing - * this HW version. Contains number of instances, - * register offsets, capabilities of the all MDSS HW sub-blocks. + * this HW version. Contains dpu's major and minor versions, + * number of instances, register offsets, capabilities of the + * all MDSS HW sub-blocks. * * @dma_formats Supported formats for dma pipe * @cursor_formats Supported formats for cursor pipe @@ -805,6 +816,8 @@ struct dpu_perf_cfg { * @mdss_irqs: Bitmap with the irqs supported by the target */ struct dpu_mdss_cfg { + const struct dpu_mdss_version *mdss_ver; + const struct dpu_caps *caps; const struct dpu_ubwc_cfg *ubwc; From 51e9b25c7818dd658c837b0e7882249dcf66f25f Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Tue, 11 Jul 2023 18:20:00 -0700 Subject: [PATCH 038/118] drm/msm/dpu: use dpu core's major version to enable data compress Instead of using a feature bit to decide whether to enable data compress or not for DSC use-cases, use dpu core's major version instead by assigning the enable_compression op based on the dpu core's major version. To make this possible pass the struct dpu_mdss_version to dpu_hw_intf_init(). This will avoid defining feature bits for every bit level details of registers. changes in v5: - none Reviewed-by: Dmitry Baryshkov Signed-off-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/546803/ Link: https://lore.kernel.org/r/20230712012003.2212-3-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 5b0f6627e29b..d766791438e7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -523,7 +523,7 @@ static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx) } static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, - unsigned long cap) + unsigned long cap, const struct dpu_mdss_version *mdss_rev) { ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine; ops->setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; @@ -543,12 +543,12 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh; } - if (cap & BIT(DPU_INTF_DATA_COMPRESS)) + if (mdss_rev->core_major_ver >= 7) ops->enable_compression = dpu_hw_intf_enable_compression; } struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg, - void __iomem *addr) + void __iomem *addr, const struct dpu_mdss_version *mdss_rev) { struct dpu_hw_intf *c; @@ -569,7 +569,7 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg, */ c->idx = cfg->id; c->cap = cfg; - _setup_intf_ops(&c->ops, c->cap->features); + _setup_intf_ops(&c->ops, c->cap->features, mdss_rev); return c; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 99e21c4137f9..3b5f18dbcb4b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -127,9 +127,10 @@ struct dpu_hw_intf { * interface catalog entry. * @cfg: interface catalog entry for which driver object is required * @addr: mapped register io address of MDP + * @mdss_rev: dpu core's major and minor versions */ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg, - void __iomem *addr); + void __iomem *addr, const struct dpu_mdss_version *mdss_rev); /** * dpu_hw_intf_destroy(): Destroys INTF driver context diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index e333f4eeafc1..4a53e2c931d6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -161,7 +161,7 @@ int dpu_rm_init(struct dpu_rm *rm, struct dpu_hw_intf *hw; const struct dpu_intf_cfg *intf = &cat->intf[i]; - hw = dpu_hw_intf_init(intf, mmio); + hw = dpu_hw_intf_init(intf, mmio, cat->mdss_ver); if (IS_ERR(hw)) { rc = PTR_ERR(hw); DPU_ERROR("failed intf object creation: err %d\n", rc); From 4c6df9a40bbce2b2b9f50baf82a95a1f6ece314e Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Tue, 11 Jul 2023 18:20:01 -0700 Subject: [PATCH 039/118] drm/msm/dpu: rename all hw_intf structs to have dpu_hw prefix dpu_hw_intf has a few instances of structs which do not have the dpu_hw prefix. Lets fix this by renaming those structs and updating the usage of those accordingly. Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/546805/ Link: https://lore.kernel.org/r/20230712012003.2212-4-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov --- .../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 18 +++++++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 12 ++++++------ 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index 662d74ded1b9..c2189e58de6a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -40,7 +40,7 @@ static bool dpu_encoder_phys_vid_is_master( static void drm_mode_to_intf_timing_params( const struct dpu_encoder_phys *phys_enc, const struct drm_display_mode *mode, - struct intf_timing_params *timing) + struct dpu_hw_intf_timing_params *timing) { memset(timing, 0, sizeof(*timing)); @@ -114,7 +114,7 @@ static void drm_mode_to_intf_timing_params( } } -static u32 get_horizontal_total(const struct intf_timing_params *timing) +static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing) { u32 active = timing->xres; u32 inactive = @@ -123,7 +123,7 @@ static u32 get_horizontal_total(const struct intf_timing_params *timing) return active + inactive; } -static u32 get_vertical_total(const struct intf_timing_params *timing) +static u32 get_vertical_total(const struct dpu_hw_intf_timing_params *timing) { u32 active = timing->yres; u32 inactive = @@ -148,7 +148,7 @@ static u32 get_vertical_total(const struct intf_timing_params *timing) */ static u32 programmable_fetch_get_num_lines( struct dpu_encoder_phys *phys_enc, - const struct intf_timing_params *timing) + const struct dpu_hw_intf_timing_params *timing) { u32 worst_case_needed_lines = phys_enc->hw_intf->cap->prog_fetch_lines_worst_case; @@ -196,9 +196,9 @@ static u32 programmable_fetch_get_num_lines( * @timing: Pointer to the intf timing information for the requested mode */ static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc, - const struct intf_timing_params *timing) + const struct dpu_hw_intf_timing_params *timing) { - struct intf_prog_fetch f = { 0 }; + struct dpu_hw_intf_prog_fetch f = { 0 }; u32 vfp_fetch_lines = 0; u32 horiz_total = 0; u32 vert_total = 0; @@ -231,7 +231,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( struct dpu_encoder_phys *phys_enc) { struct drm_display_mode mode; - struct intf_timing_params timing_params = { 0 }; + struct dpu_hw_intf_timing_params timing_params = { 0 }; const struct dpu_format *fmt = NULL; u32 fmt_fourcc = DRM_FORMAT_RGB888; unsigned long lock_flags; @@ -522,7 +522,7 @@ static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) { unsigned long lock_flags; int ret; - struct intf_status intf_status = {0}; + struct dpu_hw_intf_status intf_status = {0}; if (!phys_enc->parent || !phys_enc->parent->dev) { DPU_ERROR("invalid encoder/device\n"); @@ -651,7 +651,7 @@ static int dpu_encoder_phys_vid_get_line_count( static int dpu_encoder_phys_vid_get_frame_count( struct dpu_encoder_phys *phys_enc) { - struct intf_status s = {0}; + struct dpu_hw_intf_status s = {0}; u32 fetch_start = 0; struct drm_display_mode mode; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index d766791438e7..7392880d736c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -95,7 +95,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, - const struct intf_timing_params *p, + const struct dpu_hw_intf_timing_params *p, const struct dpu_format *fmt) { struct dpu_hw_blk_reg_map *c = &ctx->hw; @@ -244,7 +244,7 @@ static void dpu_hw_intf_enable_timing_engine( static void dpu_hw_intf_setup_prg_fetch( struct dpu_hw_intf *intf, - const struct intf_prog_fetch *fetch) + const struct dpu_hw_intf_prog_fetch *fetch) { struct dpu_hw_blk_reg_map *c = &intf->hw; int fetch_enable; @@ -286,7 +286,7 @@ static void dpu_hw_intf_bind_pingpong_blk( static void dpu_hw_intf_get_status( struct dpu_hw_intf *intf, - struct intf_status *s) + struct dpu_hw_intf_status *s) { struct dpu_hw_blk_reg_map *c = &intf->hw; unsigned long cap = intf->cap->features; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 3b5f18dbcb4b..bd6f54208d44 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -14,7 +14,7 @@ struct dpu_hw_intf; /* intf timing settings */ -struct intf_timing_params { +struct dpu_hw_intf_timing_params { u32 width; /* active width */ u32 height; /* active height */ u32 xres; /* Display panel width */ @@ -35,13 +35,13 @@ struct intf_timing_params { bool wide_bus_en; }; -struct intf_prog_fetch { +struct dpu_hw_intf_prog_fetch { u8 enable; /* vsync counter for the front porch pixel line */ u32 fetch_start; }; -struct intf_status { +struct dpu_hw_intf_status { u8 is_en; /* interface timing engine is enabled or not */ u8 is_prog_fetch_en; /* interface prog fetch counter is enabled or not */ u32 frame_count; /* frame count since timing engine enabled */ @@ -74,17 +74,17 @@ struct intf_status { */ struct dpu_hw_intf_ops { void (*setup_timing_gen)(struct dpu_hw_intf *intf, - const struct intf_timing_params *p, + const struct dpu_hw_intf_timing_params *p, const struct dpu_format *fmt); void (*setup_prg_fetch)(struct dpu_hw_intf *intf, - const struct intf_prog_fetch *fetch); + const struct dpu_hw_intf_prog_fetch *fetch); void (*enable_timing)(struct dpu_hw_intf *intf, u8 enable); void (*get_status)(struct dpu_hw_intf *intf, - struct intf_status *status); + struct dpu_hw_intf_status *status); u32 (*get_line_count)(struct dpu_hw_intf *intf); From 143dfccad3dad9b0b15c6476cab6a723e94b1e73 Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Tue, 11 Jul 2023 18:20:02 -0700 Subject: [PATCH 040/118] drm/msm/dpu: rename enable_compression() to program_intf_cmd_cfg() Rename the intf's enable_compression() op to program_intf_cmd_cfg() and allow it to accept a struct intf_cmd_mode_cfg to program all the bits at once. This can be re-used by widebus later on as well as it touches the same register. changes in v5: - rename struct intf_cmd_mode_cfg to dpu_hw_intf_cmd_mode_cfg - remove couple of comments Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/546806/ Link: https://lore.kernel.org/r/20230712012003.2212-5-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 8 ++++++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 8 +++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 9 +++++++-- 3 files changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index b856c6286c85..df88358e7037 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -50,6 +50,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( to_dpu_encoder_phys_cmd(phys_enc); struct dpu_hw_ctl *ctl; struct dpu_hw_intf_cfg intf_cfg = { 0 }; + struct dpu_hw_intf_cmd_mode_cfg cmd_mode_cfg = {}; ctl = phys_enc->hw_ctl; if (!ctl->ops.setup_intf_cfg) @@ -68,8 +69,11 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( phys_enc->hw_intf, phys_enc->hw_pp->idx); - if (intf_cfg.dsc != 0 && phys_enc->hw_intf->ops.enable_compression) - phys_enc->hw_intf->ops.enable_compression(phys_enc->hw_intf); + if (intf_cfg.dsc != 0) + cmd_mode_cfg.data_compress = true; + + if (phys_enc->hw_intf->ops.program_intf_cmd_cfg) + phys_enc->hw_intf->ops.program_intf_cmd_cfg(phys_enc->hw_intf, &cmd_mode_cfg); } static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 7392880d736c..8ec6505d9e78 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -513,11 +513,13 @@ static void dpu_hw_intf_disable_autorefresh(struct dpu_hw_intf *intf, } -static void dpu_hw_intf_enable_compression(struct dpu_hw_intf *ctx) +static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx, + struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg) { u32 intf_cfg2 = DPU_REG_READ(&ctx->hw, INTF_CONFIG2); - intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; + if (cmd_mode_cfg->data_compress) + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2); } @@ -544,7 +546,7 @@ static void _setup_intf_ops(struct dpu_hw_intf_ops *ops, } if (mdss_rev->core_major_ver >= 7) - ops->enable_compression = dpu_hw_intf_enable_compression; + ops->program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg; } struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index bd6f54208d44..77f80531782b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -48,6 +48,10 @@ struct dpu_hw_intf_status { u32 line_count; /* current line count including blanking */ }; +struct dpu_hw_intf_cmd_mode_cfg { + u8 data_compress; /* enable data compress between dpu and dsi */ +}; + /** * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions * Assumption is these functions will be called after clocks are enabled @@ -70,7 +74,7 @@ struct dpu_hw_intf_status { * @get_autorefresh: Retrieve autorefresh config from hardware * Return: 0 on success, -ETIMEDOUT on timeout * @vsync_sel: Select vsync signal for tear-effect configuration - * @enable_compression: Enable data compression + * @program_intf_cmd_cfg: Program the DPU to interface datapath for command mode */ struct dpu_hw_intf_ops { void (*setup_timing_gen)(struct dpu_hw_intf *intf, @@ -108,7 +112,8 @@ struct dpu_hw_intf_ops { */ void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t encoder_id, u16 vdisplay); - void (*enable_compression)(struct dpu_hw_intf *intf); + void (*program_intf_cmd_cfg)(struct dpu_hw_intf *intf, + struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg); }; struct dpu_hw_intf { From 781452286aebd81b4f03192f4eb2ccf8ad4a9f2d Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Tue, 11 Jul 2023 18:20:03 -0700 Subject: [PATCH 041/118] drm/msm/dpu: drop DPU_INTF_DATA_COMPRESS from dpu catalog Now that all usages of DPU_INTF_DATA_COMPRESS have been replaced with the dpu core's major revision lets drop DPU_INTF_DATA_COMPRESS from the catalog completely. Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/546808/ Link: https://lore.kernel.org/r/20230712012003.2212-6-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 3f545e8609ab..00ccbce87ac7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -101,7 +101,7 @@ BIT(DPU_INTF_STATUS_SUPPORTED) | \ BIT(DPU_DATA_HCTL_EN)) -#define INTF_SC7280_MASK (INTF_SC7180_MASK | BIT(DPU_INTF_DATA_COMPRESS)) +#define INTF_SC7280_MASK (INTF_SC7180_MASK) #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ BIT(DPU_WB_UBWC) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index e455f95456f0..d6f0c4fe4e9a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -181,7 +181,6 @@ enum { * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate * than video timing * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register - * @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register * @DPU_INTF_MAX */ enum { @@ -189,7 +188,6 @@ enum { DPU_INTF_TE, DPU_DATA_HCTL_EN, DPU_INTF_STATUS_SUPPORTED, - DPU_INTF_DATA_COMPRESS, DPU_INTF_MAX }; From a7e3fda5948a15148352d4ef4975551a22acf793 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 23 Jul 2023 18:08:39 +0200 Subject: [PATCH 042/118] drm/msm/dsi: Drop unused regulators from QCM2290 14nm DSI PHY config The regulator setup was likely copied from other SoCs by mistake. Just like SM6125 the DSI PHY on this platform is not getting power from a regulator but from the MX power domain. Fixes: 572e9fd6d14a ("drm/msm/dsi: Add phy configuration for QCM2290") Reviewed-by: Konrad Dybcio Reviewed-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Signed-off-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/548959/ Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-1-a3f287dd6c07@somainline.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 3ce45b023e63..31deda1c664a 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -1087,8 +1087,6 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = { const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = { .has_phy_lane = true, - .regulator_data = dsi_phy_14nm_17mA_regulators, - .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators), .ops = { .enable = dsi_14nm_phy_enable, .disable = dsi_14nm_phy_disable, From dcfc49a5b1d2985397de3148d3b900659686500f Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 23 Jul 2023 18:08:42 +0200 Subject: [PATCH 043/118] dt-bindings: display/msm: Remove DSI1 ports from SM6350/SM6375 example Both SM6350 and SM6375 support only a single DSI link, and don't have a corresponding dsi1 node in DTS. Their examples should not suggest an output interface port on the display-controller node to this inexistant DSI host, with a dsi1_in label reference that doesn't exist in the example either. Fixes: 3b7502b0c205 ("dt-bindings: display/msm: Add SM6350 MDSS") Fixes: 2a5c1021bc77 ("dt-bindings: display/msm: Add SM6375 MDSS") Signed-off-by: Marijn Suijten Acked-by: Rob Herring Patchwork: https://patchwork.freedesktop.org/patch/548961/ Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-4-a3f287dd6c07@somainline.org Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml | 7 ------- .../devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml | 7 ------- 2 files changed, 14 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml index ed0ad194d4ce..63962a8f2faf 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6350-mdss.yaml @@ -131,13 +131,6 @@ examples: remote-endpoint = <&dsi0_in>; }; }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; }; }; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml index 76369a4f7c4d..595a9d56949c 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml @@ -132,13 +132,6 @@ examples: remote-endpoint = <&dsi0_in>; }; }; - - port@1 { - reg = <1>; - dpu_intf2_out: endpoint { - remote-endpoint = <&dsi1_in>; - }; - }; }; }; From 3b3e71f07d357ef0ee7cfb0edda33698036a0670 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 23 Jul 2023 18:08:43 +0200 Subject: [PATCH 044/118] dt-bindings: clock: qcom, dispcc-sm6125: Require GCC PLL0 DIV clock The "gcc_disp_gpll0_div_clk_src" clock is consumed by the driver, will be passed from DT, and should be required by the bindings. Fixes: 8397c9c0c26b ("dt-bindings: clock: add QCOM SM6125 display clock bindings") Reviewed-by: Rob Herring Signed-off-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/548966/ Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-5-a3f287dd6c07@somainline.org Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/clock/qcom,dispcc-sm6125.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml index 8a210c4c5f82..8fd29915bf2c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml @@ -29,6 +29,7 @@ properties: - description: Link clock from DP PHY - description: VCO DIV clock from DP PHY - description: AHB config clock from GCC + - description: GPLL0 div source from GCC clock-names: items: @@ -39,6 +40,7 @@ properties: - const: dp_phy_pll_link_clk - const: dp_phy_pll_vco_div_clk - const: cfg_ahb_clk + - const: gcc_disp_gpll0_div_clk_src '#clock-cells': const: 1 @@ -72,14 +74,16 @@ examples: <&dsi1_phy 1>, <&dp_phy 0>, <&dp_phy 1>, - <&gcc GCC_DISP_AHB_CLK>; + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; clock-names = "bi_tcxo", "dsi0_phy_pll_out_byteclk", "dsi0_phy_pll_out_dsiclk", "dsi1_phy_pll_out_dsiclk", "dp_phy_pll_link_clk", "dp_phy_pll_vco_div_clk", - "cfg_ahb_clk"; + "cfg_ahb_clk", + "gcc_disp_gpll0_div_clk_src"; #clock-cells = <1>; #power-domain-cells = <1>; }; From 3a06fa8e518568e9fb0252b53c89d2d66d5037ad Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 23 Jul 2023 18:08:44 +0200 Subject: [PATCH 045/118] dt-bindings: clock: qcom, dispcc-sm6125: Allow power-domains property On SM6125 the dispcc block is gated behind VDDCX: allow this domain to be configured. Acked-by: Krzysztof Kozlowski Signed-off-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/548970/ Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-6-a3f287dd6c07@somainline.org Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,dispcc-sm6125.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml index 8fd29915bf2c..0a3ef7fd03fa 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml @@ -48,6 +48,16 @@ properties: '#power-domain-cells': const: 1 + power-domains: + description: + A phandle and PM domain specifier for the CX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing the power domain's performance point. + maxItems: 1 + reg: maxItems: 1 @@ -65,9 +75,11 @@ examples: - | #include #include + #include clock-controller@5f00000 { compatible = "qcom,sm6125-dispcc"; reg = <0x5f00000 0x20000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&dsi0_phy 0>, <&dsi0_phy 1>, @@ -84,6 +96,10 @@ examples: "dp_phy_pll_vco_div_clk", "cfg_ahb_clk", "gcc_disp_gpll0_div_clk_src"; + + required-opps = <&rpmhpd_opp_ret>; + power-domains = <&rpmpd SM6125_VDDCX>; + #clock-cells = <1>; #power-domain-cells = <1>; }; From bb49fa7051d777bd2be9bdf514304b22ff56d74c Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 23 Jul 2023 18:08:45 +0200 Subject: [PATCH 046/118] dt-bindings: display/msm: dsi-controller-main: Document SM6125 Document general compatibility of the DSI controller on SM6125. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Signed-off-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/548968/ Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-7-a3f287dd6c07@somainline.org Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 76270992305a..b8d1f2b7d541 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -27,6 +27,7 @@ properties: - qcom,sdm660-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl + - qcom,sm6125-dsi-ctrl - qcom,sm6350-dsi-ctrl - qcom,sm6375-dsi-ctrl - qcom,sm8150-dsi-ctrl @@ -305,6 +306,7 @@ allOf: contains: enum: - qcom,msm8998-dsi-ctrl + - qcom,sm6125-dsi-ctrl - qcom,sm6350-dsi-ctrl then: properties: From 8225df64fc3086e57014d98c5fbcd495cc7ce2dc Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 23 Jul 2023 18:08:46 +0200 Subject: [PATCH 047/118] dt-bindings: display/msm: sc7180-dpu: Describe SM6125 SM6125 is identical to SM6375 including the throttle clock that is also provided to the MDP node downstream. Note that any SoC other than SM6375 (currently SC7180 and SM6350) has an unconstrained maximum number of clocks and could either pass or leave out this "throttle" clock. Signed-off-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/548972/ Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-8-a3f287dd6c07@somainline.org Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml index 630b11480496..ea75f0f95d5c 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml @@ -15,6 +15,7 @@ properties: compatible: enum: - qcom,sc7180-dpu + - qcom,sm6125-dpu - qcom,sm6350-dpu - qcom,sm6375-dpu @@ -63,7 +64,9 @@ allOf: - if: properties: compatible: - const: qcom,sm6375-dpu + enum: + - qcom,sm6375-dpu + - qcom,sm6125-dpu then: properties: From cd188d68db35e457fe4b6301b6801fae5dff1ecc Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 23 Jul 2023 18:08:47 +0200 Subject: [PATCH 048/118] dt-bindings: display/msm: Add SM6125 MDSS Document the SM6125 MDSS. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/548976/ Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-9-a3f287dd6c07@somainline.org Signed-off-by: Dmitry Baryshkov --- .../display/msm/qcom,sm6125-mdss.yaml | 213 ++++++++++++++++++ 1 file changed, 213 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml new file mode 100644 index 000000000000..57f0e3647711 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6125-mdss.yaml @@ -0,0 +1,213 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm6125-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6125 Display MDSS + +maintainers: + - Marijn Suijten + +description: + SM6125 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks + like DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm6125-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display AHB clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: ahb + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + maxItems: 2 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6125-dpu + + "^dsi@[0-9a-f]+$": + type: object + properties: + compatible: + items: + - const: qcom,sm6125-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + properties: + compatible: + const: qcom,sm6125-dsi-phy-14nm + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + display-subsystem@5e00000 { + compatible = "qcom,sm6125-mdss"; + reg = <0x05e00000 0x1000>; + reg-names = "mdss"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "ahb", + "core"; + + power-domains = <&dispcc MDSS_GDSC>; + + iommus = <&apps_smmu 0x400 0x0>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@5e01000 { + compatible = "qcom,sm6125-dpu"; + reg = <0x05e01000 0x83208>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&gcc GCC_DISP_THROTTLE_CORE_CLK>; + clock-names = "bus", + "iface", + "rot", + "lut", + "core", + "vsync", + "throttle"; + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6125_VDDCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + }; + + dsi@5e94000 { + compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x05e94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SM6125_VDDCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + phy@5e94400 { + compatible = "qcom,sm6125-dsi-phy-14nm"; + reg = <0x05e94400 0x100>, + <0x05e94500 0x300>, + <0x05e94800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + + required-opps = <&rpmpd_opp_nom>; + power-domains = <&rpmpd SM6125_VDDMX>; + }; + }; +... From 9b6f4fedaac2db4b1389c457000cfdb5c3d1c0c5 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 23 Jul 2023 18:08:48 +0200 Subject: [PATCH 049/118] drm/msm/dpu: Add SM6125 support Add definitions for the display hardware used on the Qualcomm SM6125 platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/548978/ Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-10-a3f287dd6c07@somainline.org Signed-off-by: Dmitry Baryshkov --- .../msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 236 ++++++++++++++++++ .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 7 + .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 245 insertions(+) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h new file mode 100644 index 000000000000..5fddfcce6288 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -0,0 +1,236 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Marijn Suijten . All rights reserved. + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_5_4_SM6125_H +#define _DPU_5_4_SM6125_H + +static const struct dpu_caps sm6125_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0x6, + .has_dim_layer = true, + .has_idle_pc = true, + .max_linewidth = 2160, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp = MAX_HORZ_DECIMATION, + .max_vdeci_exp = MAX_VERT_DECIMATION, +}; + +static const struct dpu_ubwc_cfg sm6125_ubwc_cfg = { + .ubwc_version = DPU_HW_UBWC_VER_10, + .highest_bank_bit = 0x1, + .ubwc_swizzle = 0x1, +}; + +static const struct dpu_mdp_cfg sm6125_mdp = { + .name = "top_0", + .base = 0x0, .len = 0x45c, + .features = 0, + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + }, +}; + +static const struct dpu_ctl_cfg sm6125_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a00, .len = 0x1e0, + .features = BIT(DPU_CTL_ACTIVE_CFG), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sm6125_sspp[] = { + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1f0, + .features = VIG_SM6125_MASK, + .sblk = &sm6125_vig_sblk_0, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1f0, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_0, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1f0, + .features = DMA_SDM845_MASK, + .sblk = &sdm845_dma_sblk_1, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, +}; + +static const struct dpu_lm_cfg sm6125_lm[] = { + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_QCM2290_MASK, + .sblk = &sdm845_lm_sblk, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + .lm_pair = LM_1, + }, { + .name = "lm_1", .id = LM_1, + .base = 0x45000, .len = 0x320, + .features = MIXER_QCM2290_MASK, + .sblk = &sdm845_lm_sblk, + .pingpong = PINGPONG_1, + .dspp = 0, + .lm_pair = LM_0, + }, +}; + +static const struct dpu_dspp_cfg sm6125_dspp[] = { + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg sm6125_pp[] = { + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x70000, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .merge_3d = 0, + .sblk = &sdm845_pp_sblk, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = -1, + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x70800, .len = 0xd4, + .features = PINGPONG_SM8150_MASK, + .merge_3d = 0, + .sblk = &sdm845_pp_sblk, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr = -1, + }, +}; + +static const struct dpu_intf_cfg sm6125_intf[] = { + { + .name = "intf_0", .id = INTF_0, + .base = 0x6a000, .len = 0x280, + .features = INTF_SC7180_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x6a800, .len = 0x2c0, + .features = INTF_SC7180_MASK, + .type = INTF_DSI, + .controller_id = 0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, +}; + +static const struct dpu_perf_cfg sm6125_perf_data = { + .max_bw_low = 4100000, + .max_bw_high = 4100000, + .min_core_ib = 2400000, + .min_llcc_ib = 0, /* No LLCC on this SoC */ + .min_dram_ib = 800000, + .min_prefill_lines = 24, + .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sm8150_qos_linear), + .entries = sm8150_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +static const struct dpu_mdss_version sm6125_mdss_ver = { + .core_major_ver = 5, + .core_minor_ver = 4, +}; + +const struct dpu_mdss_cfg dpu_sm6125_cfg = { + .mdss_ver = &sm6125_mdss_ver, + .caps = &sm6125_dpu_caps, + .ubwc = &sm6125_ubwc_cfg, + .mdp = &sm6125_mdp, + .ctl_count = ARRAY_SIZE(sm6125_ctl), + .ctl = sm6125_ctl, + .sspp_count = ARRAY_SIZE(sm6125_sspp), + .sspp = sm6125_sspp, + .mixer_count = ARRAY_SIZE(sm6125_lm), + .mixer = sm6125_lm, + .dspp_count = ARRAY_SIZE(sm6125_dspp), + .dspp = sm6125_dspp, + .pingpong_count = ARRAY_SIZE(sm6125_pp), + .pingpong = sm6125_pp, + .intf_count = ARRAY_SIZE(sm6125_intf), + .intf = sm6125_intf, + .vbif_count = ARRAY_SIZE(sdm845_vbif), + .vbif = sdm845_vbif, + .perf = &sm6125_perf_data, + .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ + BIT(MDP_SSPP_TOP0_INTR2) | \ + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ + BIT(MDP_INTF0_INTR) | \ + BIT(MDP_INTF1_INTR) | \ + BIT(MDP_INTF1_TEAR_INTR), +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 00ccbce87ac7..3ff07d7cbf4b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -33,6 +33,9 @@ #define VIG_SC7180_MASK \ (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) +#define VIG_SM6125_MASK \ + (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) + #define VIG_SC7180_MASK_SDMA \ (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) @@ -333,6 +336,9 @@ static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = _VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4); +static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 = + _VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE); + static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = @@ -632,6 +638,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { #include "catalog/dpu_5_0_sm8150.h" #include "catalog/dpu_5_1_sc8180x.h" +#include "catalog/dpu_5_4_sm6125.h" #include "catalog/dpu_6_0_sm8250.h" #include "catalog/dpu_6_2_sc7180.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index d6f0c4fe4e9a..acfe43f4918c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -871,6 +871,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; extern const struct dpu_mdss_cfg dpu_sm8250_cfg; extern const struct dpu_mdss_cfg dpu_sc7180_cfg; extern const struct dpu_mdss_cfg dpu_sm6115_cfg; +extern const struct dpu_mdss_cfg dpu_sm6125_cfg; extern const struct dpu_mdss_cfg dpu_sm6350_cfg; extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; extern const struct dpu_mdss_cfg dpu_sm6375_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index a5c65eec6f88..c1d06e19b237 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1346,6 +1346,7 @@ static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, }, { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, }, { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, }, + { .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, }, { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, }, { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, }, { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, }, From 87aa3c9b44709f2c0c26d3a4fc4d08b3c1e46521 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 23 Jul 2023 18:08:49 +0200 Subject: [PATCH 050/118] drm/msm/mdss: Add SM6125 support SM6125 has an UBWC 3.0 decoder but only an UBWC 1.0 encoder. Reviewed-by: Dmitry Baryshkov Signed-off-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/548974/ Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-11-a3f287dd6c07@somainline.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_mdss.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 05648c910c68..bf68bae23264 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -559,6 +559,13 @@ static const struct msm_mdss_data sm6115_data = { .ubwc_static = 0x11f, }; +static const struct msm_mdss_data sm6125_data = { + .ubwc_version = UBWC_1_0, + .ubwc_dec_version = UBWC_3_0, + .ubwc_swizzle = 1, + .highest_bank_bit = 1, +}; + static const struct msm_mdss_data sm8250_data = { .ubwc_version = UBWC_4_0, .ubwc_dec_version = UBWC_4_0, @@ -579,6 +586,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data }, { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data }, { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data }, + { .compatible = "qcom,sm6125-mdss", .data = &sm6125_data }, { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data }, { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data }, { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data }, From 75df8c57b85b056fe6de2701c7b44a79e2ea1d43 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 23 Jul 2023 18:08:50 +0200 Subject: [PATCH 051/118] dt-bindings: msm: dsi-phy-14nm: Document SM6125 variant Document availability of the 14nm DSI PHY on SM6125. Note that this compatible uses the SoC-suffix variant, intead of postfixing an arbitrary number without the sm/sdm portion. The PHY is not powered by a vcca regulator like on most SoCs, but by the MX power domain that is provided via the power-domains property and a single corresponding required-opps. Acked-by: Krzysztof Kozlowski Signed-off-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/548979/ Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-12-a3f287dd6c07@somainline.org Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml index a43e11d3b00d..2361da5f6736 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml @@ -19,6 +19,7 @@ properties: - qcom,dsi-phy-14nm-2290 - qcom,dsi-phy-14nm-660 - qcom,dsi-phy-14nm-8953 + - qcom,sm6125-dsi-phy-14nm reg: items: @@ -35,6 +36,16 @@ properties: vcca-supply: description: Phandle to vcca regulator device node. + power-domains: + description: + A phandle and PM domain specifier for an optional power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing the power domain's performance point. + maxItems: 1 + required: - compatible - reg From be4dacf4eee1c4e2e91586e75e95b2852274dc58 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 23 Jul 2023 18:08:51 +0200 Subject: [PATCH 052/118] drm/msm/dsi: Reuse QCM2290 14nm DSI PHY configuration for SM6125 SM6125 features only a single PHY (despite a secondary PHY PLL source being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream sources for this "trinket" SoC do not define the typical "vcca" regulator to be available nor used. This, including the register offset is identical to QCM2290, whose config struct can trivially be reused. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/548980/ Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-13-a3f287dd6c07@somainline.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 9d5795c58a98..05621e5e7d63 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -561,6 +561,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_14nm_660_cfgs }, { .compatible = "qcom,dsi-phy-14nm-8953", .data = &dsi_phy_14nm_8953_cfgs }, + { .compatible = "qcom,sm6125-dsi-phy-14nm", + .data = &dsi_phy_14nm_2290_cfgs }, #endif #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY { .compatible = "qcom,dsi-phy-10nm", From b4b4050406895e75825a77475de57ffc90dd2653 Mon Sep 17 00:00:00 2001 From: Amit Pundir Date: Wed, 26 Jul 2023 18:57:18 +0530 Subject: [PATCH 053/118] dt-bindings: display/msm: mdss-common: add memory-region property Add and document the reserved memory region property in the mdss-common schema. For now (sdm845-db845c), it points to a framebuffer memory region reserved by the bootloader for splash screen. Acked-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Amit Pundir Patchwork: https://patchwork.freedesktop.org/patch/549376/ Link: https://lore.kernel.org/r/20230726132719.2117369-1-amit.pundir@linaro.org Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/mdss-common.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml index ccd7d6417523..a8086ca09d9f 100644 --- a/Documentation/devicetree/bindings/display/msm/mdss-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdss-common.yaml @@ -77,6 +77,12 @@ properties: items: - description: MDSS_CORE reset + memory-region: + maxItems: 1 + description: + Phandle to a node describing a reserved framebuffer memory region. + For example, the splash memory region set up by the bootloader. + required: - reg - reg-names From f09f5459bd85a575df15ae294363169ca8988a9f Mon Sep 17 00:00:00 2001 From: Ruan Jinjie Date: Thu, 27 Jul 2023 11:24:07 +0000 Subject: [PATCH 054/118] drm/msm: Remove redundant DRM_DEV_ERROR() There is no need to call the DRM_DEV_ERROR() function directly to print a custom message when handling an error from platform_get_irq() function as it is going to display an appropriate error message in case of a failure. Signed-off-by: Ruan Jinjie Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549499/ Link: https://lore.kernel.org/r/20230727112407.2916029-1-ruanjinjie@huawei.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 1 - drivers/gpu/drm/msm/msm_gpu.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c index b6201ae5b42e..700df4040e9a 100644 --- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c @@ -417,7 +417,6 @@ static int mdp4_kms_init(struct drm_device *dev) irq = platform_get_irq(pdev, 0); if (irq < 0) { ret = irq; - DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret); goto fail; } diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 52db90e34ead..8a9bacc920eb 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -897,7 +897,6 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, gpu->irq = platform_get_irq(pdev, 0); if (gpu->irq < 0) { ret = gpu->irq; - DRM_DEV_ERROR(drm->dev, "failed to get irq: %d\n", ret); goto fail; } From c54b4c35194e578747c083421fb3eca458b2aaa8 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 27 Jul 2023 17:45:39 +0300 Subject: [PATCH 055/118] drm/msm/dpu: inline __intr_offset Inline __intr_offset(), there is no point in having a separate oneline function for setting base block address. Reviewed-by: Neil Armstrong Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549655/ Link: https://lore.kernel.org/r/20230727144543.1483630-2-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 5e2d68ebb113..0776b0f6df4f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -435,12 +435,6 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx) return intr_status; } -static void __intr_offset(const struct dpu_mdss_cfg *m, - void __iomem *addr, struct dpu_hw_blk_reg_map *hw) -{ - hw->blk_addr = addr + m->mdp[0].base; -} - struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, const struct dpu_mdss_cfg *m) { @@ -454,7 +448,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, if (!intr) return ERR_PTR(-ENOMEM); - __intr_offset(m, addr, &intr->hw); + intr->hw.blk_addr = addr + m->mdp[0].base; intr->total_irqs = nirq; From 370891f0d983e6166db81c7fa2cc083c4f072052 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 27 Jul 2023 17:45:40 +0300 Subject: [PATCH 056/118] drm/msm/dpu: split interrupt address arrays There is no point in having a single enum (and a single array) for both DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single enum and two IRQ address arrays. Reviewed-by: Neil Armstrong Reviewed-by: Marijn Suijten Fixes: c7314613226a0 ("drm/msm: Add missing struct identifier") Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549653/ Link: https://lore.kernel.org/r/20230727144543.1483630-3-dmitry.baryshkov@linaro.org --- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +++++++++++++------ .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ++++--- 2 files changed, 72 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 0776b0f6df4f..0cecdc847b49 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -51,11 +51,9 @@ struct dpu_intr_reg { }; /* - * struct dpu_intr_reg - List of DPU interrupt registers - * - * When making changes be sure to sync with dpu_hw_intr_reg + * dpu_intr_set_legacy - List of DPU interrupt registers for DPU <= 6.x */ -static const struct dpu_intr_reg dpu_intr_set[] = { +static const struct dpu_intr_reg dpu_intr_set_legacy[] = { [MDP_SSPP_TOP0_INTR] = { INTR_CLEAR, INTR_EN, @@ -121,57 +119,78 @@ static const struct dpu_intr_reg dpu_intr_set[] = { MDP_AD4_INTR_EN_OFF(1), MDP_AD4_INTR_STATUS_OFF(1), }, - [MDP_INTF0_7xxx_INTR] = { +}; + +/* + * dpu_intr_set_7xxx - List of DPU interrupt registers for DPU >= 7.0 + */ +static const struct dpu_intr_reg dpu_intr_set_7xxx[] = { + [MDP_SSPP_TOP0_INTR] = { + INTR_CLEAR, + INTR_EN, + INTR_STATUS + }, + [MDP_SSPP_TOP0_INTR2] = { + INTR2_CLEAR, + INTR2_EN, + INTR2_STATUS + }, + [MDP_SSPP_TOP0_HIST_INTR] = { + HIST_INTR_CLEAR, + HIST_INTR_EN, + HIST_INTR_STATUS + }, + [MDP_INTF0_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(0), MDP_INTF_REV_7xxx_INTR_EN(0), MDP_INTF_REV_7xxx_INTR_STATUS(0) }, - [MDP_INTF1_7xxx_INTR] = { + [MDP_INTF1_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(1), MDP_INTF_REV_7xxx_INTR_EN(1), MDP_INTF_REV_7xxx_INTR_STATUS(1) }, - [MDP_INTF1_7xxx_TEAR_INTR] = { + [MDP_INTF1_TEAR_INTR] = { MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1), MDP_INTF_REV_7xxx_INTR_TEAR_EN(1), MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1) }, - [MDP_INTF2_7xxx_INTR] = { + [MDP_INTF2_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(2), MDP_INTF_REV_7xxx_INTR_EN(2), MDP_INTF_REV_7xxx_INTR_STATUS(2) }, - [MDP_INTF2_7xxx_TEAR_INTR] = { + [MDP_INTF2_TEAR_INTR] = { MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2), MDP_INTF_REV_7xxx_INTR_TEAR_EN(2), MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2) }, - [MDP_INTF3_7xxx_INTR] = { + [MDP_INTF3_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(3), MDP_INTF_REV_7xxx_INTR_EN(3), MDP_INTF_REV_7xxx_INTR_STATUS(3) }, - [MDP_INTF4_7xxx_INTR] = { + [MDP_INTF4_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(4), MDP_INTF_REV_7xxx_INTR_EN(4), MDP_INTF_REV_7xxx_INTR_STATUS(4) }, - [MDP_INTF5_7xxx_INTR] = { + [MDP_INTF5_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(5), MDP_INTF_REV_7xxx_INTR_EN(5), MDP_INTF_REV_7xxx_INTR_STATUS(5) }, - [MDP_INTF6_7xxx_INTR] = { + [MDP_INTF6_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(6), MDP_INTF_REV_7xxx_INTR_EN(6), MDP_INTF_REV_7xxx_INTR_STATUS(6) }, - [MDP_INTF7_7xxx_INTR] = { + [MDP_INTF7_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(7), MDP_INTF_REV_7xxx_INTR_EN(7), MDP_INTF_REV_7xxx_INTR_STATUS(7) }, - [MDP_INTF8_7xxx_INTR] = { + [MDP_INTF8_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(8), MDP_INTF_REV_7xxx_INTR_EN(8), MDP_INTF_REV_7xxx_INTR_STATUS(8) @@ -216,19 +235,19 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms) return IRQ_NONE; spin_lock_irqsave(&intr->irq_lock, irq_flags); - for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) { + for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) { if (!test_bit(reg_idx, &intr->irq_mask)) continue; /* Read interrupt status */ - irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off); + irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off); /* Read enable mask */ - enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off); + enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off); /* and clear the interrupt */ if (irq_status) - DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, + DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off, irq_status); /* Finally update IRQ status based on enable mask */ @@ -285,7 +304,11 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx) assert_spin_locked(&intr->irq_lock); reg_idx = DPU_IRQ_REG(irq_idx); - reg = &dpu_intr_set[reg_idx]; + reg = &intr->intr_set[reg_idx]; + + /* Is this interrupt register supported on the platform */ + if (WARN_ON(!reg->en_off)) + return -EINVAL; cache_irq_mask = intr->cache_irq_mask[reg_idx]; if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) { @@ -334,7 +357,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx) assert_spin_locked(&intr->irq_lock); reg_idx = DPU_IRQ_REG(irq_idx); - reg = &dpu_intr_set[reg_idx]; + reg = &intr->intr_set[reg_idx]; cache_irq_mask = intr->cache_irq_mask[reg_idx]; if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) { @@ -368,10 +391,10 @@ static void dpu_clear_irqs(struct dpu_kms *dpu_kms) if (!intr) return; - for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) { + for (i = 0; i < MDP_INTR_MAX; i++) { if (test_bit(i, &intr->irq_mask)) DPU_REG_WRITE(&intr->hw, - dpu_intr_set[i].clr_off, 0xffffffff); + intr->intr_set[i].clr_off, 0xffffffff); } /* ensure register writes go through */ @@ -386,10 +409,10 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms) if (!intr) return; - for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) { + for (i = 0; i < MDP_INTR_MAX; i++) { if (test_bit(i, &intr->irq_mask)) DPU_REG_WRITE(&intr->hw, - dpu_intr_set[i].en_off, 0x00000000); + intr->intr_set[i].en_off, 0x00000000); } /* ensure register writes go through */ @@ -421,10 +444,10 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx) reg_idx = DPU_IRQ_REG(irq_idx); intr_status = DPU_REG_READ(&intr->hw, - dpu_intr_set[reg_idx].status_off) & + intr->intr_set[reg_idx].status_off) & DPU_IRQ_MASK(irq_idx); if (intr_status) - DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, + DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off, intr_status); /* ensure register writes go through */ @@ -448,6 +471,11 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, if (!intr) return ERR_PTR(-ENOMEM); + if (m->mdss_ver->core_major_ver >= 7) + intr->intr_set = dpu_intr_set_7xxx; + else + intr->intr_set = dpu_intr_set_legacy; + intr->hw.blk_addr = addr + m->mdp[0].base; intr->total_irqs = nirq; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index 1f2dabc54c22..f329d6d7f646 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -23,24 +23,29 @@ enum dpu_hw_intr_reg { MDP_INTF3_INTR, MDP_INTF4_INTR, MDP_INTF5_INTR, + MDP_INTF6_INTR, + MDP_INTF7_INTR, + MDP_INTF8_INTR, MDP_INTF1_TEAR_INTR, MDP_INTF2_TEAR_INTR, MDP_AD4_0_INTR, MDP_AD4_1_INTR, - MDP_INTF0_7xxx_INTR, - MDP_INTF1_7xxx_INTR, - MDP_INTF1_7xxx_TEAR_INTR, - MDP_INTF2_7xxx_INTR, - MDP_INTF2_7xxx_TEAR_INTR, - MDP_INTF3_7xxx_INTR, - MDP_INTF4_7xxx_INTR, - MDP_INTF5_7xxx_INTR, - MDP_INTF6_7xxx_INTR, - MDP_INTF7_7xxx_INTR, - MDP_INTF8_7xxx_INTR, MDP_INTR_MAX, }; +/* compatibility */ +#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR +#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR +#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR +#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR +#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR +#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR +#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR +#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR +#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR +#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR +#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR + #define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset) /** @@ -60,6 +65,7 @@ struct dpu_hw_intr { u32 total_irqs; spinlock_t irq_lock; unsigned long irq_mask; + const struct dpu_intr_reg *intr_set; struct { void (*cb)(void *arg, int irq_idx); From bf8198cc3b904fb6c3fba90cefc8e8c539d263b0 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 27 Jul 2023 17:45:41 +0300 Subject: [PATCH 057/118] drm/msm/dpu: autodetect supported interrupts Declaring the mask of supported interrupts proved to be error-prone. It is very easy to add a bit with no corresponding backing block or to miss the INTF TE bit. Replace this with looping over the enabled INTF blocks to setup the irq mask. Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549654/ Link: https://lore.kernel.org/r/20230727144543.1483630-4-dmitry.baryshkov@linaro.org --- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 16 +++++++++++++++- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 3 +++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 0cecdc847b49..e3c50439f80a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -463,6 +463,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, { struct dpu_hw_intr *intr; int nirq = MDP_INTR_MAX * 32; + unsigned int i; if (!addr || !m) return ERR_PTR(-EINVAL); @@ -480,7 +481,20 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, intr->total_irqs = nirq; - intr->irq_mask = m->mdss_irqs; + intr->irq_mask = BIT(MDP_SSPP_TOP0_INTR) | + BIT(MDP_SSPP_TOP0_INTR2) | + BIT(MDP_SSPP_TOP0_HIST_INTR); + for (i = 0; i < m->intf_count; i++) { + const struct dpu_intf_cfg *intf = &m->intf[i]; + + if (intf->type == INTF_NONE) + continue; + + intr->irq_mask |= BIT(MDP_INTFn_INTR(intf->id)); + + if (intf->intr_tear_rd_ptr != -1) + intr->irq_mask |= BIT(DPU_IRQ_REG(intf->intr_tear_rd_ptr)); + } spin_lock_init(&intr->irq_lock); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index f329d6d7f646..6e0d0188edc6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -17,6 +17,7 @@ enum dpu_hw_intr_reg { MDP_SSPP_TOP0_INTR, MDP_SSPP_TOP0_INTR2, MDP_SSPP_TOP0_HIST_INTR, + /* All MDP_INTFn_INTR should come sequentially */ MDP_INTF0_INTR, MDP_INTF1_INTR, MDP_INTF2_INTR, @@ -33,6 +34,8 @@ enum dpu_hw_intr_reg { MDP_INTR_MAX, }; +#define MDP_INTFn_INTR(intf) (MDP_INTF0_INTR + (intf - INTF_0)) + /* compatibility */ #define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR #define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR From 40f9cedf54f1261017931f2851c5fbbf646e66e0 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 27 Jul 2023 17:45:42 +0300 Subject: [PATCH 058/118] drm/msm/dpu: drop now-unused mdss_irqs field from hw catalog Now as the list of the interrupts is constructed from the catalog data, drop the mdss_irqs field from catalog. Reviewed-by: Neil Armstrong Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549659/ Link: https://lore.kernel.org/r/20230727144543.1483630-5-dmitry.baryshkov@linaro.org --- .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 8 -------- .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 9 --------- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 11 ----------- .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 13 ------------- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 6 ------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 10 ---------- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 6 ------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 5 ----- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 6 ------ .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 5 ----- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 5 ----- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 9 --------- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 ------- .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 14 -------------- .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 9 --------- .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 9 --------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 --- 17 files changed, 135 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index b5fbac55f127..92530aec3bdc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -342,14 +342,6 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = { .vbif_count = ARRAY_SIZE(msm8998_vbif), .vbif = msm8998_vbif, .perf = &msm8998_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF2_INTR) | \ - BIT(MDP_INTF3_INTR) | \ - BIT(MDP_INTF4_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 8000b870d3a7..3034c1b6ed90 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -359,15 +359,6 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sdm845_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF2_INTR) | \ - BIT(MDP_INTF3_INTR) | \ - BIT(MDP_AD4_0_INTR) | \ - BIT(MDP_AD4_1_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 7ce2d69d28f6..3745c150540e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -404,17 +404,6 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sm8150_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF1_TEAR_INTR) | \ - BIT(MDP_INTF2_INTR) | \ - BIT(MDP_INTF2_TEAR_INTR) | \ - BIT(MDP_INTF3_INTR) | \ - BIT(MDP_AD4_0_INTR) | \ - BIT(MDP_AD4_1_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index cea005382456..6291568bef03 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -431,19 +431,6 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sc8180x_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF1_TEAR_INTR) | \ - BIT(MDP_INTF2_INTR) | \ - BIT(MDP_INTF2_TEAR_INTR) | \ - BIT(MDP_INTF3_INTR) | \ - BIT(MDP_INTF4_INTR) | \ - BIT(MDP_INTF5_INTR) | \ - BIT(MDP_AD4_0_INTR) | \ - BIT(MDP_AD4_1_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index 5fddfcce6288..e922668aea1a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -225,12 +225,6 @@ const struct dpu_mdss_cfg dpu_sm6125_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sm6125_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF1_TEAR_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 893d1271fb71..9751b39ae371 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -421,16 +421,6 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = { .wb_count = ARRAY_SIZE(sm8250_wb), .wb = sm8250_wb, .perf = &sm8250_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF1_TEAR_INTR) | \ - BIT(MDP_INTF2_INTR) | \ - BIT(MDP_INTF2_TEAR_INTR) | \ - BIT(MDP_INTF3_INTR) | \ - BIT(MDP_INTF4_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index 61118f648cbc..a9464b856f42 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -231,12 +231,6 @@ const struct dpu_mdss_cfg dpu_sc7180_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sc7180_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF1_TEAR_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index c0d7bb930e8a..ae7cd965c0b9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -161,11 +161,6 @@ const struct dpu_mdss_cfg dpu_sm6115_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sm6115_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF1_TEAR_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index 11c50aa5034b..a13305cad7cd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -234,12 +234,6 @@ const struct dpu_mdss_cfg dpu_sm6350_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sm6350_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF1_TEAR_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index 2182939bc026..bb297c3ef81a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -151,11 +151,6 @@ const struct dpu_mdss_cfg dpu_qcm2290_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &qcm2290_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF1_TEAR_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index f0c0aa90f82e..014a56e585b7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -173,11 +173,6 @@ const struct dpu_mdss_cfg dpu_sm6375_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sm6375_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF1_INTR) | \ - BIT(MDP_INTF1_TEAR_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 2460ced03610..90efde5e9da5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -412,15 +412,6 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sm8350_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_TEAR_INTR) | \ - BIT(MDP_INTF2_7xxx_INTR) | \ - BIT(MDP_INTF2_7xxx_TEAR_INTR) | \ - BIT(MDP_INTF3_7xxx_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index a8dea8f27c41..0a5dcec343fc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -281,13 +281,6 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sc7280_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_TEAR_INTR) | \ - BIT(MDP_INTF5_7xxx_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 397fe01125dd..7b1395f9e710 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -474,20 +474,6 @@ const struct dpu_mdss_cfg dpu_sc8280xp_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sc8280xp_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_TEAR_INTR) | \ - BIT(MDP_INTF2_7xxx_INTR) | \ - BIT(MDP_INTF2_7xxx_TEAR_INTR) | \ - BIT(MDP_INTF3_7xxx_INTR) | \ - BIT(MDP_INTF4_7xxx_INTR) | \ - BIT(MDP_INTF5_7xxx_INTR) | \ - BIT(MDP_INTF6_7xxx_INTR) | \ - BIT(MDP_INTF7_7xxx_INTR) | \ - BIT(MDP_INTF8_7xxx_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 90a8461911c8..4999f3d8f2e2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -435,15 +435,6 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sm8450_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_TEAR_INTR) | \ - BIT(MDP_INTF2_7xxx_INTR) | \ - BIT(MDP_INTF2_7xxx_TEAR_INTR) | \ - BIT(MDP_INTF3_7xxx_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index c9252528136d..401c6c2da367 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -449,15 +449,6 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = { .vbif_count = ARRAY_SIZE(sdm845_vbif), .vbif = sdm845_vbif, .perf = &sm8550_perf_data, - .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ - BIT(MDP_SSPP_TOP0_INTR2) | \ - BIT(MDP_SSPP_TOP0_HIST_INTR) | \ - BIT(MDP_INTF0_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_INTR) | \ - BIT(MDP_INTF1_7xxx_TEAR_INTR) | \ - BIT(MDP_INTF2_7xxx_INTR) | \ - BIT(MDP_INTF2_7xxx_TEAR_INTR) | \ - BIT(MDP_INTF3_7xxx_INTR), }; #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index acfe43f4918c..c72ed0e35dce 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -811,7 +811,6 @@ struct dpu_perf_cfg { * @dma_formats Supported formats for dma pipe * @cursor_formats Supported formats for cursor pipe * @vig_formats Supported formats for vig pipe - * @mdss_irqs: Bitmap with the irqs supported by the target */ struct dpu_mdss_cfg { const struct dpu_mdss_version *mdss_ver; @@ -860,8 +859,6 @@ struct dpu_mdss_cfg { const struct dpu_format_extended *dma_formats; const struct dpu_format_extended *cursor_formats; const struct dpu_format_extended *vig_formats; - - unsigned long mdss_irqs; }; extern const struct dpu_mdss_cfg dpu_msm8998_cfg; From edb34ac1f65eb3b17bebc08bc0c05ccf8d18226e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 27 Jul 2023 17:45:43 +0300 Subject: [PATCH 059/118] drm/msm/dpu: drop compatibility INTR defines While reworking interrupts masks, it was easier to keep old MDP_INTFn_7xxx_INTR and MDP_INTFn_7xxx_TEAR_INTR symbols. Now it is time to drop them and use unified symbol names. Reviewed-by: Neil Armstrong Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549656/ Link: https://lore.kernel.org/r/20230727144543.1483630-6-dmitry.baryshkov@linaro.org --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ++-- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ++-- .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ++-- .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 13 ------------- 6 files changed, 9 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 90efde5e9da5..941b585bd56f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -329,7 +329,7 @@ static const struct dpu_intf_cfg sm8350_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_2", .id = INTF_2, .base = 0x36000, .len = 0x2c4, @@ -339,7 +339,7 @@ static const struct dpu_intf_cfg sm8350_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 0a5dcec343fc..b18bb7ce2f94 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -210,7 +210,7 @@ static const struct dpu_intf_cfg sc7280_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_5", .id = INTF_5, .base = 0x39000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 7b1395f9e710..b08096f0d50b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -344,7 +344,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_2", .id = INTF_2, .base = 0x36000, .len = 0x300, @@ -354,7 +354,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 4999f3d8f2e2..9e0ad71c12a8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -352,7 +352,7 @@ static const struct dpu_intf_cfg sm8450_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_2", .id = INTF_2, .base = 0x36000, .len = 0x300, @@ -362,7 +362,7 @@ static const struct dpu_intf_cfg sm8450_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 401c6c2da367..2a19e4c0af1a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -366,7 +366,7 @@ static const struct dpu_intf_cfg sm8550_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_2", .id = INTF_2, .base = 0x36000, .len = 0x300, @@ -376,7 +376,7 @@ static const struct dpu_intf_cfg sm8550_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index 6e0d0188edc6..dab761e54863 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -36,19 +36,6 @@ enum dpu_hw_intr_reg { #define MDP_INTFn_INTR(intf) (MDP_INTF0_INTR + (intf - INTF_0)) -/* compatibility */ -#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR -#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR -#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR -#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR -#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR -#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR -#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR -#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR -#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR -#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR -#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR - #define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset) /** From 0fbe7c7d36e89631d3ad90479ba008319362c233 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 29 Jul 2023 00:33:14 +0300 Subject: [PATCH 060/118] drm/msm/mdss: correct UBWC programming for SM8550 The SM8550 platform employs newer UBWC decoder, which requires slightly different programming. Fixes: a2f33995c19d ("drm/msm: mdss: add support for SM8550") Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550049/ Link: https://lore.kernel.org/r/20230728213320.97309-2-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/msm_mdss.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index bf68bae23264..e38929205134 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -189,6 +189,7 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) #define UBWC_2_0 0x20000000 #define UBWC_3_0 0x30000000 #define UBWC_4_0 0x40000000 +#define UBWC_4_3 0x40030000 static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) { @@ -227,7 +228,10 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2); writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE); } else { - writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); + if (data->ubwc_dec_version == UBWC_4_3) + writel_relaxed(3, msm_mdss->mmio + UBWC_CTRL_2); + else + writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE); } } @@ -271,6 +275,7 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) msm_mdss_setup_ubwc_dec_30(msm_mdss); break; case UBWC_4_0: + case UBWC_4_3: msm_mdss_setup_ubwc_dec_40(msm_mdss); break; default: @@ -576,6 +581,16 @@ static const struct msm_mdss_data sm8250_data = { .macrotile_mode = 1, }; +static const struct msm_mdss_data sm8550_data = { + .ubwc_version = UBWC_4_0, + .ubwc_dec_version = UBWC_4_3, + .ubwc_swizzle = 6, + .ubwc_static = 1, + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + .highest_bank_bit = 3, + .macrotile_mode = 1, +}; + static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,mdss" }, { .compatible = "qcom,msm8998-mdss" }, @@ -593,7 +608,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data }, { .compatible = "qcom,sm8350-mdss", .data = &sm8250_data }, { .compatible = "qcom,sm8450-mdss", .data = &sm8250_data }, - { .compatible = "qcom,sm8550-mdss", .data = &sm8250_data }, + { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data }, {} }; MODULE_DEVICE_TABLE(of, mdss_dt_match); From cab5b40633b017f7f6fadd11f58c81a9e748aa39 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 29 Jul 2023 00:33:15 +0300 Subject: [PATCH 061/118] drm/msm/mdss: rename ubwc_version to ubwc_enc_version Rename the ubwc_version field to ubwc_enc_version, it denotes the version of the UBWC encoder, not the "UBWC version". Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550051/ Link: https://lore.kernel.org/r/20230728213320.97309-3-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/msm_mdss.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index e38929205134..67436a5a8cf1 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -27,7 +27,7 @@ #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ struct msm_mdss_data { - u32 ubwc_version; + u32 ubwc_enc_version; /* can be read from register 0x58 */ u32 ubwc_dec_version; u32 ubwc_swizzle; @@ -205,10 +205,10 @@ static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) (data->highest_bank_bit & 0x3) << 4 | (data->macrotile_mode & 0x1) << 12; - if (data->ubwc_version == UBWC_3_0) + if (data->ubwc_enc_version == UBWC_3_0) value |= BIT(10); - if (data->ubwc_version == UBWC_1_0) + if (data->ubwc_enc_version == UBWC_1_0) value |= BIT(8); writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); @@ -224,7 +224,7 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); - if (data->ubwc_version == UBWC_3_0) { + if (data->ubwc_enc_version == UBWC_3_0) { writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2); writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE); } else { @@ -507,13 +507,13 @@ static int mdss_remove(struct platform_device *pdev) } static const struct msm_mdss_data sc7180_data = { - .ubwc_version = UBWC_2_0, + .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, .ubwc_static = 0x1e, }; static const struct msm_mdss_data sc7280_data = { - .ubwc_version = UBWC_3_0, + .ubwc_enc_version = UBWC_3_0, .ubwc_dec_version = UBWC_4_0, .ubwc_swizzle = 6, .ubwc_static = 1, @@ -522,14 +522,14 @@ static const struct msm_mdss_data sc7280_data = { }; static const struct msm_mdss_data sc8180x_data = { - .ubwc_version = UBWC_3_0, + .ubwc_enc_version = UBWC_3_0, .ubwc_dec_version = UBWC_3_0, .highest_bank_bit = 3, .macrotile_mode = 1, }; static const struct msm_mdss_data sc8280xp_data = { - .ubwc_version = UBWC_4_0, + .ubwc_enc_version = UBWC_4_0, .ubwc_dec_version = UBWC_4_0, .ubwc_swizzle = 6, .ubwc_static = 1, @@ -538,13 +538,13 @@ static const struct msm_mdss_data sc8280xp_data = { }; static const struct msm_mdss_data sdm845_data = { - .ubwc_version = UBWC_2_0, + .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, .highest_bank_bit = 2, }; static const struct msm_mdss_data sm6350_data = { - .ubwc_version = UBWC_2_0, + .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, .ubwc_swizzle = 6, .ubwc_static = 0x1e, @@ -552,27 +552,27 @@ static const struct msm_mdss_data sm6350_data = { }; static const struct msm_mdss_data sm8150_data = { - .ubwc_version = UBWC_3_0, + .ubwc_enc_version = UBWC_3_0, .ubwc_dec_version = UBWC_3_0, .highest_bank_bit = 2, }; static const struct msm_mdss_data sm6115_data = { - .ubwc_version = UBWC_1_0, + .ubwc_enc_version = UBWC_1_0, .ubwc_dec_version = UBWC_2_0, .ubwc_swizzle = 7, .ubwc_static = 0x11f, }; static const struct msm_mdss_data sm6125_data = { - .ubwc_version = UBWC_1_0, + .ubwc_enc_version = UBWC_1_0, .ubwc_dec_version = UBWC_3_0, .ubwc_swizzle = 1, .highest_bank_bit = 1, }; static const struct msm_mdss_data sm8250_data = { - .ubwc_version = UBWC_4_0, + .ubwc_enc_version = UBWC_4_0, .ubwc_dec_version = UBWC_4_0, .ubwc_swizzle = 6, .ubwc_static = 1, @@ -582,7 +582,7 @@ static const struct msm_mdss_data sm8250_data = { }; static const struct msm_mdss_data sm8550_data = { - .ubwc_version = UBWC_4_0, + .ubwc_enc_version = UBWC_4_0, .ubwc_dec_version = UBWC_4_3, .ubwc_swizzle = 6, .ubwc_static = 1, From 71e00fc0afde15cb7bc8db1143d0050af6ac8d24 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 29 Jul 2023 00:33:16 +0300 Subject: [PATCH 062/118] drm/msm/mdss: export UBWC data DPU programming requires knowledge of some of UBWC parameters. This results in duplication of UBWC data between MDSS and DPU drivers. Export the required data from MDSS driver. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550052/ Link: https://lore.kernel.org/r/20230728213320.97309-4-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/msm_mdss.c | 30 +++++++++++++----------------- drivers/gpu/drm/msm/msm_mdss.h | 27 +++++++++++++++++++++++++++ 2 files changed, 40 insertions(+), 17 deletions(-) create mode 100644 drivers/gpu/drm/msm/msm_mdss.h diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 67436a5a8cf1..0189811bce4d 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -13,7 +13,7 @@ #include #include -#include "msm_drv.h" +#include "msm_mdss.h" #include "msm_kms.h" #define HW_REV 0x0 @@ -26,16 +26,6 @@ #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ -struct msm_mdss_data { - u32 ubwc_enc_version; - /* can be read from register 0x58 */ - u32 ubwc_dec_version; - u32 ubwc_swizzle; - u32 ubwc_static; - u32 highest_bank_bit; - u32 macrotile_mode; -}; - struct msm_mdss { struct device *dev; @@ -185,12 +175,6 @@ static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) return 0; } -#define UBWC_1_0 0x10000000 -#define UBWC_2_0 0x20000000 -#define UBWC_3_0 0x30000000 -#define UBWC_4_0 0x40000000 -#define UBWC_4_3 0x40030000 - static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) { const struct msm_mdss_data *data = msm_mdss->mdss_data; @@ -236,6 +220,18 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) } } +const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev) +{ + struct msm_mdss *mdss; + + if (!dev) + return ERR_PTR(-EINVAL); + + mdss = dev_get_drvdata(dev); + + return mdss->mdss_data; +} + static int msm_mdss_enable(struct msm_mdss *msm_mdss) { int ret; diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h new file mode 100644 index 000000000000..02bbab42adbc --- /dev/null +++ b/drivers/gpu/drm/msm/msm_mdss.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018, The Linux Foundation + */ + +#ifndef __MSM_MDSS_H__ +#define __MSM_MDSS_H__ + +struct msm_mdss_data { + u32 ubwc_enc_version; + /* can be read from register 0x58 */ + u32 ubwc_dec_version; + u32 ubwc_swizzle; + u32 ubwc_static; + u32 highest_bank_bit; + u32 macrotile_mode; +}; + +#define UBWC_1_0 0x10000000 +#define UBWC_2_0 0x20000000 +#define UBWC_3_0 0x30000000 +#define UBWC_4_0 0x40000000 +#define UBWC_4_3 0x40030000 + +const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev); + +#endif /* __MSM_MDSS_H__ */ From 6f410b24620914733a9d7f8d73a00d357e830080 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 29 Jul 2023 00:33:17 +0300 Subject: [PATCH 063/118] drm/msm/mdss: populate missing data As we are going to use MDSS data for DPU programming, populate missing MDSS data. The UBWC 1.0 and no UBWC cases do not require MDSS programming, so skip them. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/550055/ Link: https://lore.kernel.org/r/20230728213320.97309-5-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/msm_mdss.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 0189811bce4d..c2b4cf9ad2eb 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -264,6 +264,10 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) * UBWC_n and the rest of params comes from hw data. */ switch (msm_mdss->mdss_data->ubwc_dec_version) { + case 0: /* no UBWC */ + case UBWC_1_0: + /* do nothing */ + break; case UBWC_2_0: msm_mdss_setup_ubwc_dec_20(msm_mdss); break; @@ -502,10 +506,22 @@ static int mdss_remove(struct platform_device *pdev) return 0; } +static const struct msm_mdss_data msm8998_data = { + .ubwc_enc_version = UBWC_1_0, + .ubwc_dec_version = UBWC_1_0, + .highest_bank_bit = 1, +}; + +static const struct msm_mdss_data qcm2290_data = { + /* no UBWC */ + .highest_bank_bit = 0x2, +}; + static const struct msm_mdss_data sc7180_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, .ubwc_static = 0x1e, + .highest_bank_bit = 0x3, }; static const struct msm_mdss_data sc7280_data = { @@ -558,6 +574,7 @@ static const struct msm_mdss_data sm6115_data = { .ubwc_dec_version = UBWC_2_0, .ubwc_swizzle = 7, .ubwc_static = 0x11f, + .highest_bank_bit = 0x1, }; static const struct msm_mdss_data sm6125_data = { @@ -589,8 +606,8 @@ static const struct msm_mdss_data sm8550_data = { static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,mdss" }, - { .compatible = "qcom,msm8998-mdss" }, - { .compatible = "qcom,qcm2290-mdss" }, + { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data }, + { .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data }, { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data }, { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data }, { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data }, From a2e87e9ef891a0eec8de8ea8b060beaf4afd3ee2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 29 Jul 2023 00:33:18 +0300 Subject: [PATCH 064/118] drm/msm/dpu: use MDSS data for programming SSPP Switch to using data from MDSS driver to program the SSPP fetch and UBWC configuration. As a side-effect, this also swithes the DPU driver from DPU_HW_UBWC_VER_xx values to the UBWC_x_y enum, which reflects the hardware register values. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/550054/ Link: https://lore.kernel.org/r/20230728213320.97309-6-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 18 ++++++++++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 16 +++++++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 2 ++ 6 files changed, 33 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index b364cf75bb3f..f2192de93713 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -8,6 +8,8 @@ #include "dpu_hw_sspp.h" #include "dpu_kms.h" +#include "msm_mdss.h" + #include #define DPU_FETCH_CONFIG_RESET_VALUE 0x00000087 @@ -270,26 +272,26 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe *pipe, DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, DPU_FETCH_CONFIG_RESET_VALUE | ctx->ubwc->highest_bank_bit << 18); - switch (ctx->ubwc->ubwc_version) { - case DPU_HW_UBWC_VER_10: + switch (ctx->ubwc->ubwc_enc_version) { + case UBWC_1_0: fast_clear = fmt->alpha_enable ? BIT(31) : 0; DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1) | BIT(8) | (ctx->ubwc->highest_bank_bit << 4)); break; - case DPU_HW_UBWC_VER_20: + case UBWC_2_0: fast_clear = fmt->alpha_enable ? BIT(31) : 0; DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, fast_clear | (ctx->ubwc->ubwc_swizzle) | (ctx->ubwc->highest_bank_bit << 4)); break; - case DPU_HW_UBWC_VER_30: + case UBWC_3_0: DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, BIT(30) | (ctx->ubwc->ubwc_swizzle) | (ctx->ubwc->highest_bank_bit << 4)); break; - case DPU_HW_UBWC_VER_40: + case UBWC_4_0: DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL, DPU_FORMAT_IS_YUV(fmt) ? 0 : BIT(30)); break; @@ -670,11 +672,11 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, #endif struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg, - void __iomem *addr, const struct dpu_ubwc_cfg *ubwc) + void __iomem *addr, const struct msm_mdss_data *mdss_data) { struct dpu_hw_sspp *hw_pipe; - if (!addr || !ubwc) + if (!addr) return ERR_PTR(-EINVAL); hw_pipe = kzalloc(sizeof(*hw_pipe), GFP_KERNEL); @@ -685,7 +687,7 @@ struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg, hw_pipe->hw.log_mask = DPU_DBG_MASK_SSPP; /* Assign ops */ - hw_pipe->ubwc = ubwc; + hw_pipe->ubwc = mdss_data; hw_pipe->idx = cfg->id; hw_pipe->cap = cfg; _setup_layer_ops(hw_pipe, hw_pipe->cap->features); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 085f34bc6b88..cbf4f95ff0fd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -317,7 +317,7 @@ struct dpu_hw_sspp_ops { struct dpu_hw_sspp { struct dpu_hw_blk base; struct dpu_hw_blk_reg_map hw; - const struct dpu_ubwc_cfg *ubwc; + const struct msm_mdss_data *ubwc; /* Pipe */ enum dpu_sspp idx; @@ -333,10 +333,10 @@ struct dpu_kms; * Should be called once before accessing every pipe. * @cfg: Pipe catalog entry for which driver object is required * @addr: Mapped register io address of MDP - * @ubwc: UBWC configuration data + * @mdss_data: UBWC / MDSS configuration data */ struct dpu_hw_sspp *dpu_hw_sspp_init(const struct dpu_sspp_cfg *cfg, - void __iomem *addr, const struct dpu_ubwc_cfg *ubwc); + void __iomem *addr, const struct msm_mdss_data *mdss_data); /** * dpu_hw_sspp_destroy(): Destroys SSPP driver context diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index c1d06e19b237..2da9eef687af 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -22,6 +22,7 @@ #include "msm_drv.h" #include "msm_mmu.h" +#include "msm_mdss.h" #include "msm_gem.h" #include "disp/msm_disp_snapshot.h" @@ -1124,7 +1125,20 @@ static int dpu_kms_hw_init(struct msm_kms *kms) goto power_error; } - rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio); + dpu_kms->mdss = msm_mdss_get_mdss_data(dpu_kms->pdev->dev.parent); + if (IS_ERR(dpu_kms->mdss)) { + rc = PTR_ERR(dpu_kms->mdss); + DPU_ERROR("failed to get MDSS data: %d\n", rc); + goto power_error; + } + + if (!dpu_kms->mdss) { + rc = -EINVAL; + DPU_ERROR("NULL MDSS data\n"); + goto power_error; + } + + rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mdss, dpu_kms->mmio); if (rc) { DPU_ERROR("rm init failed: %d\n", rc); goto power_error; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index f3bdd4f11108..b6f53ca6e962 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -67,6 +67,7 @@ struct dpu_kms { struct msm_kms base; struct drm_device *dev; const struct dpu_mdss_cfg *catalog; + const struct msm_mdss_data *mdss; /* io/register spaces: */ void __iomem *mmio, *vbif[VBIF_MAX]; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 4a53e2c931d6..f9215643c71a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -101,6 +101,7 @@ int dpu_rm_destroy(struct dpu_rm *rm) int dpu_rm_init(struct dpu_rm *rm, const struct dpu_mdss_cfg *cat, + const struct msm_mdss_data *mdss_data, void __iomem *mmio) { int rc, i; @@ -230,7 +231,7 @@ int dpu_rm_init(struct dpu_rm *rm, struct dpu_hw_sspp *hw; const struct dpu_sspp_cfg *sspp = &cat->sspp[i]; - hw = dpu_hw_sspp_init(sspp, mmio, cat->ubwc); + hw = dpu_hw_sspp_init(sspp, mmio, mdss_data); if (IS_ERR(hw)) { rc = PTR_ERR(hw); DPU_ERROR("failed sspp object creation: err %d\n", rc); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h index d62c2edb2460..2b551566cbf4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h @@ -40,11 +40,13 @@ struct dpu_rm { * for all HW blocks. * @rm: DPU Resource Manager handle * @cat: Pointer to hardware catalog + * @mdss_data: Pointer to MDSS / UBWC configuration * @mmio: mapped register io address of MDP * @Return: 0 on Success otherwise -ERROR */ int dpu_rm_init(struct dpu_rm *rm, const struct dpu_mdss_cfg *cat, + const struct msm_mdss_data *mdss_data, void __iomem *mmio); /** From 1613c5fddd424a5d18b97d21bb2ede608133e205 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 29 Jul 2023 00:33:19 +0300 Subject: [PATCH 065/118] drm/msm/dpu: drop UBWC configuration As the DPU driver has switched to fetching data from MDSS driver, we can now drop the UBWC and highest_bank_bit parts of the DPU hw catalog. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550058/ Link: https://lore.kernel.org/r/20230728213320.97309-7-dmitry.baryshkov@linaro.org --- .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 6 ----- .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 6 ----- .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 6 ----- .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 6 ----- .../msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 7 ------ .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 7 ------ .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 6 ----- .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 7 ------ .../msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 7 ------ .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 5 ---- .../msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 7 ------ .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 6 ----- .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 ------ .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 7 ------ .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 7 ------ .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 6 ----- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 25 ------------------- 17 files changed, 128 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 92530aec3bdc..43c47a19cd94 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -21,11 +21,6 @@ static const struct dpu_caps msm8998_dpu_caps = { .max_vdeci_exp = MAX_VERT_DECIMATION, }; -static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_10, - .highest_bank_bit = 0x2, -}; - static const struct dpu_mdp_cfg msm8998_mdp = { .name = "top_0", .base = 0x0, .len = 0x458, @@ -323,7 +318,6 @@ static const struct dpu_mdss_version msm8998_mdss_ver = { const struct dpu_mdss_cfg dpu_msm8998_cfg = { .mdss_ver = &msm8998_mdss_ver, .caps = &msm8998_dpu_caps, - .ubwc = &msm8998_ubwc_cfg, .mdp = &msm8998_mdp, .ctl_count = ARRAY_SIZE(msm8998_ctl), .ctl = msm8998_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 3034c1b6ed90..88a5177dfdb7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -21,11 +21,6 @@ static const struct dpu_caps sdm845_dpu_caps = { .max_vdeci_exp = MAX_VERT_DECIMATION, }; -static const struct dpu_ubwc_cfg sdm845_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_20, - .highest_bank_bit = 0x2, -}; - static const struct dpu_mdp_cfg sdm845_mdp = { .name = "top_0", .base = 0x0, .len = 0x45c, @@ -340,7 +335,6 @@ static const struct dpu_mdss_version sdm845_mdss_ver = { const struct dpu_mdss_cfg dpu_sdm845_cfg = { .mdss_ver = &sdm845_mdss_ver, .caps = &sdm845_dpu_caps, - .ubwc = &sdm845_ubwc_cfg, .mdp = &sdm845_mdp, .ctl_count = ARRAY_SIZE(sdm845_ctl), .ctl = sdm845_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h index 3745c150540e..99acaf917e43 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h @@ -21,11 +21,6 @@ static const struct dpu_caps sm8150_dpu_caps = { .max_vdeci_exp = MAX_VERT_DECIMATION, }; -static const struct dpu_ubwc_cfg sm8150_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_30, - .highest_bank_bit = 0x2, -}; - static const struct dpu_mdp_cfg sm8150_mdp = { .name = "top_0", .base = 0x0, .len = 0x45c, @@ -383,7 +378,6 @@ static const struct dpu_mdss_version sm8150_mdss_ver = { const struct dpu_mdss_cfg dpu_sm8150_cfg = { .mdss_ver = &sm8150_mdss_ver, .caps = &sm8150_dpu_caps, - .ubwc = &sm8150_ubwc_cfg, .mdp = &sm8150_mdp, .ctl_count = ARRAY_SIZE(sm8150_ctl), .ctl = sm8150_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h index 6291568bef03..f3de21025ca7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h @@ -21,11 +21,6 @@ static const struct dpu_caps sc8180x_dpu_caps = { .max_vdeci_exp = MAX_VERT_DECIMATION, }; -static const struct dpu_ubwc_cfg sc8180x_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_30, - .highest_bank_bit = 0x3, -}; - static const struct dpu_mdp_cfg sc8180x_mdp = { .name = "top_0", .base = 0x0, .len = 0x45c, @@ -410,7 +405,6 @@ static const struct dpu_mdss_version sc8180x_mdss_ver = { const struct dpu_mdss_cfg dpu_sc8180x_cfg = { .mdss_ver = &sc8180x_mdss_ver, .caps = &sc8180x_dpu_caps, - .ubwc = &sc8180x_ubwc_cfg, .mdp = &sc8180x_mdp, .ctl_count = ARRAY_SIZE(sc8180x_ctl), .ctl = sc8180x_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h index e922668aea1a..2491eed10039 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h @@ -19,12 +19,6 @@ static const struct dpu_caps sm6125_dpu_caps = { .max_vdeci_exp = MAX_VERT_DECIMATION, }; -static const struct dpu_ubwc_cfg sm6125_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_10, - .highest_bank_bit = 0x1, - .ubwc_swizzle = 0x1, -}; - static const struct dpu_mdp_cfg sm6125_mdp = { .name = "top_0", .base = 0x0, .len = 0x45c, @@ -208,7 +202,6 @@ static const struct dpu_mdss_version sm6125_mdss_ver = { const struct dpu_mdss_cfg dpu_sm6125_cfg = { .mdss_ver = &sm6125_mdss_ver, .caps = &sm6125_dpu_caps, - .ubwc = &sm6125_ubwc_cfg, .mdp = &sm6125_mdp, .ctl_count = ARRAY_SIZE(sm6125_ctl), .ctl = sm6125_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h index 9751b39ae371..5f9b437b82a6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h @@ -19,12 +19,6 @@ static const struct dpu_caps sm8250_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_40, - .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ - .ubwc_swizzle = 0x6, -}; - static const struct dpu_mdp_cfg sm8250_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -398,7 +392,6 @@ static const struct dpu_mdss_version sm8250_mdss_ver = { const struct dpu_mdss_cfg dpu_sm8250_cfg = { .mdss_ver = &sm8250_mdss_ver, .caps = &sm8250_dpu_caps, - .ubwc = &sm8250_ubwc_cfg, .mdp = &sm8250_mdp, .ctl_count = ARRAY_SIZE(sm8250_ctl), .ctl = sm8250_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h index a9464b856f42..d030c08636b4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h @@ -17,11 +17,6 @@ static const struct dpu_caps sc7180_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_20, - .highest_bank_bit = 0x3, -}; - static const struct dpu_mdp_cfg sc7180_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -212,7 +207,6 @@ static const struct dpu_mdss_version sc7180_mdss_ver = { const struct dpu_mdss_cfg dpu_sc7180_cfg = { .mdss_ver = &sc7180_mdss_ver, .caps = &sc7180_dpu_caps, - .ubwc = &sc7180_ubwc_cfg, .mdp = &sc7180_mdp, .ctl_count = ARRAY_SIZE(sc7180_ctl), .ctl = sc7180_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h index ae7cd965c0b9..7e6000167ef0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h @@ -17,12 +17,6 @@ static const struct dpu_caps sm6115_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_10, - .highest_bank_bit = 0x1, - .ubwc_swizzle = 0x7, -}; - static const struct dpu_mdp_cfg sm6115_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -144,7 +138,6 @@ static const struct dpu_mdss_version sm6115_mdss_ver = { const struct dpu_mdss_cfg dpu_sm6115_cfg = { .mdss_ver = &sm6115_mdss_ver, .caps = &sm6115_dpu_caps, - .ubwc = &sm6115_ubwc_cfg, .mdp = &sm6115_mdp, .ctl_count = ARRAY_SIZE(sm6115_ctl), .ctl = sm6115_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h index a13305cad7cd..cf5db6f296bd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h @@ -19,12 +19,6 @@ static const struct dpu_caps sm6350_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_20, - .ubwc_swizzle = 6, - .highest_bank_bit = 1, -}; - static const struct dpu_mdp_cfg sm6350_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -215,7 +209,6 @@ static const struct dpu_mdss_version sm6350_mdss_ver = { const struct dpu_mdss_cfg dpu_sm6350_cfg = { .mdss_ver = &sm6350_mdss_ver, .caps = &sm6350_dpu_caps, - .ubwc = &sm6350_ubwc_cfg, .mdp = &sm6350_mdp, .ctl_count = ARRAY_SIZE(sm6350_ctl), .ctl = sm6350_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h index bb297c3ef81a..87a03aa16554 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h @@ -16,10 +16,6 @@ static const struct dpu_caps qcm2290_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = { - .highest_bank_bit = 0x2, -}; - static const struct dpu_mdp_cfg qcm2290_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -134,7 +130,6 @@ static const struct dpu_mdss_version qcm2290_mdss_ver = { const struct dpu_mdss_cfg dpu_qcm2290_cfg = { .mdss_ver = &qcm2290_mdss_ver, .caps = &qcm2290_dpu_caps, - .ubwc = &qcm2290_ubwc_cfg, .mdp = &qcm2290_mdp, .ctl_count = ARRAY_SIZE(qcm2290_ctl), .ctl = qcm2290_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h index 014a56e585b7..a327e21c90fb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h @@ -18,12 +18,6 @@ static const struct dpu_caps sm6375_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_20, - .ubwc_swizzle = 6, - .highest_bank_bit = 1, -}; - static const struct dpu_mdp_cfg sm6375_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -154,7 +148,6 @@ static const struct dpu_mdss_version sm6375_mdss_ver = { const struct dpu_mdss_cfg dpu_sm6375_cfg = { .mdss_ver = &sm6375_mdss_ver, .caps = &sm6375_dpu_caps, - .ubwc = &sm6375_ubwc_cfg, .mdp = &sm6375_mdp, .ctl_count = ARRAY_SIZE(sm6375_ctl), .ctl = sm6375_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 941b585bd56f..c906b6864b5e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -19,11 +19,6 @@ static const struct dpu_caps sm8350_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_40, - .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ -}; - static const struct dpu_mdp_cfg sm8350_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -391,7 +386,6 @@ static const struct dpu_mdss_version sm8350_mdss_ver = { const struct dpu_mdss_cfg dpu_sm8350_cfg = { .mdss_ver = &sm8350_mdss_ver, .caps = &sm8350_dpu_caps, - .ubwc = &sm8350_ubwc_cfg, .mdp = &sm8350_mdp, .ctl_count = ARRAY_SIZE(sm8350_ctl), .ctl = sm8350_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index b18bb7ce2f94..2bf9f34e54c6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -17,12 +17,6 @@ static const struct dpu_caps sc7280_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_30, - .highest_bank_bit = 0x1, - .ubwc_swizzle = 0x6, -}; - static const struct dpu_mdp_cfg sc7280_mdp = { .name = "top_0", .base = 0x0, .len = 0x2014, @@ -260,7 +254,6 @@ static const struct dpu_mdss_version sc7280_mdss_ver = { const struct dpu_mdss_cfg dpu_sc7280_cfg = { .mdss_ver = &sc7280_mdss_ver, .caps = &sc7280_dpu_caps, - .ubwc = &sc7280_ubwc_cfg, .mdp = &sc7280_mdp, .ctl_count = ARRAY_SIZE(sc7280_ctl), .ctl = sc7280_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index b08096f0d50b..ccd0477f4877 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -19,12 +19,6 @@ static const struct dpu_caps sc8280xp_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_40, - .highest_bank_bit = 2, - .ubwc_swizzle = 6, -}; - static const struct dpu_mdp_cfg sc8280xp_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -453,7 +447,6 @@ static const struct dpu_mdss_version sc8280xp_mdss_ver = { const struct dpu_mdss_cfg dpu_sc8280xp_cfg = { .mdss_ver = &sc8280xp_mdss_ver, .caps = &sc8280xp_dpu_caps, - .ubwc = &sc8280xp_ubwc_cfg, .mdp = &sc8280xp_mdp, .ctl_count = ARRAY_SIZE(sc8280xp_ctl), .ctl = sc8280xp_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 9e0ad71c12a8..2b2e9d4800f8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -19,12 +19,6 @@ static const struct dpu_caps sm8450_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sm8450_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_40, - .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ - .ubwc_swizzle = 0x6, -}; - static const struct dpu_mdp_cfg sm8450_mdp = { .name = "top_0", .base = 0x0, .len = 0x494, @@ -414,7 +408,6 @@ static const struct dpu_mdss_version sm8450_mdss_ver = { const struct dpu_mdss_cfg dpu_sm8450_cfg = { .mdss_ver = &sm8450_mdss_ver, .caps = &sm8450_dpu_caps, - .ubwc = &sm8450_ubwc_cfg, .mdp = &sm8450_mdp, .ctl_count = ARRAY_SIZE(sm8450_ctl), .ctl = sm8450_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 2a19e4c0af1a..833be1167499 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -19,11 +19,6 @@ static const struct dpu_caps sm8550_dpu_caps = { .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, }; -static const struct dpu_ubwc_cfg sm8550_ubwc_cfg = { - .ubwc_version = DPU_HW_UBWC_VER_40, - .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ -}; - static const struct dpu_mdp_cfg sm8550_mdp = { .name = "top_0", .base = 0, .len = 0x494, @@ -428,7 +423,6 @@ static const struct dpu_mdss_version sm8550_mdss_ver = { const struct dpu_mdss_cfg dpu_sm8550_cfg = { .mdss_ver = &sm8550_mdss_ver, .caps = &sm8550_dpu_caps, - .ubwc = &sm8550_ubwc_cfg, .mdp = &sm8550_mdp, .ctl_count = ARRAY_SIZE(sm8550_ctl), .ctl = sm8550_ctl, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index c72ed0e35dce..0989aaa9803d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -28,16 +28,6 @@ #define MAX_XIN_COUNT 16 -/** - * Supported UBWC feature versions - */ -enum { - DPU_HW_UBWC_VER_10 = 0x100, - DPU_HW_UBWC_VER_20 = 0x200, - DPU_HW_UBWC_VER_30 = 0x300, - DPU_HW_UBWC_VER_40 = 0x400, -}; - /** * MDP TOP BLOCK features * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe @@ -503,19 +493,6 @@ struct dpu_mdp_cfg { struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; }; -/** - * struct dpu_ubwc_cfg - UBWC and memory configuration - * - * @ubwc_version UBWC feature version (0x0 for not supported) - * @highest_bank_bit: UBWC parameter - * @ubwc_swizzle: ubwc default swizzle setting - */ -struct dpu_ubwc_cfg { - u32 ubwc_version; - u32 highest_bank_bit; - u32 ubwc_swizzle; -}; - /* struct dpu_ctl_cfg : MDP CTL instance info * @id: index identifying this block * @base: register base offset to mdss @@ -817,8 +794,6 @@ struct dpu_mdss_cfg { const struct dpu_caps *caps; - const struct dpu_ubwc_cfg *ubwc; - const struct dpu_mdp_cfg *mdp; u32 ctl_count; From 7b4a727e84f094aa3132ddbb4a4e8e435cb03e4b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 29 Jul 2023 00:33:20 +0300 Subject: [PATCH 066/118] drm/msm/dpu: drop BWC features from DPU_MDP_foo namespace The feature bits DPU_MDP_BWC, DPU_MDP_UBWC_1_0, and DPU_MDP_UBWC_1_5 are not used by the driver, drop them completely. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/550056/ Link: https://lore.kernel.org/r/20230728213320.97309-8-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 0989aaa9803d..6c9634209e9f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -32,10 +32,6 @@ * MDP TOP BLOCK features * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats - * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. - * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth - * compression initial revision - * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results * in a failure * @DPU_MDP_VSYNC_SEL Enables vsync source selection via MDP_VSYNC_SEL register @@ -46,9 +42,6 @@ enum { DPU_MDP_PANIC_PER_PIPE = 0x1, DPU_MDP_10BIT_SUPPORT, - DPU_MDP_BWC, - DPU_MDP_UBWC_1_0, - DPU_MDP_UBWC_1_5, DPU_MDP_AUDIO_SELECT, DPU_MDP_PERIPH_0_REMOVED, DPU_MDP_VSYNC_SEL, From f15de4f6245b73f28887a457110fa9c1b83cd890 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 30 Jul 2023 04:00:53 +0300 Subject: [PATCH 067/118] drm/msm/dpu: drop enum dpu_core_perf_data_bus_id Drop the leftover of bus-client -> interconnect conversion, the enum dpu_core_perf_data_bus_id. Fixes: cb88482e2570 ("drm/msm/dpu: clean up references of DPU custom bus scaling") Reviewed-by: Konrad Dybcio Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550194/ Link: https://lore.kernel.org/r/20230730010102.350713-2-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h index e3795995e145..29bb8ee2bc26 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h @@ -14,19 +14,6 @@ #define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000 -/** - * enum dpu_core_perf_data_bus_id - data bus identifier - * @DPU_CORE_PERF_DATA_BUS_ID_MNOC: DPU/MNOC data bus - * @DPU_CORE_PERF_DATA_BUS_ID_LLCC: MNOC/LLCC data bus - * @DPU_CORE_PERF_DATA_BUS_ID_EBI: LLCC/EBI data bus - */ -enum dpu_core_perf_data_bus_id { - DPU_CORE_PERF_DATA_BUS_ID_MNOC, - DPU_CORE_PERF_DATA_BUS_ID_LLCC, - DPU_CORE_PERF_DATA_BUS_ID_EBI, - DPU_CORE_PERF_DATA_BUS_ID_MAX, -}; - /** * struct dpu_core_perf_params - definition of performance parameters * @max_per_pipe_ib: maximum instantaneous bandwidth request From 808c92df654a55251da7d85734f8a8842b1e465d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 30 Jul 2023 04:00:54 +0300 Subject: [PATCH 068/118] drm/msm/dpu: bail from _dpu_core_perf_crtc_update_bus if there are no ICC paths Skip bandwidth aggregation and return early if there are no interconnect paths defined for the DPU device. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/550195/ Link: https://lore.kernel.org/r/20230730010102.350713-3-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 1d9d83d7b99e..3dbd73035a11 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -217,6 +217,9 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, int i, ret = 0; u64 avg_bw; + if (!kms->num_paths) + return 0; + drm_for_each_crtc(tmp_crtc, crtc->dev) { if (tmp_crtc->enabled && curr_client_type == @@ -234,9 +237,6 @@ static int _dpu_core_perf_crtc_update_bus(struct dpu_kms *kms, } } - if (!kms->num_paths) - return 0; - avg_bw = perf.bw_ctl; do_div(avg_bw, (kms->num_paths * 1000)); /*Bps_to_icc*/ From 6a4bc73915af677af2961266631b6446852b061d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 30 Jul 2023 04:00:55 +0300 Subject: [PATCH 069/118] drm/msm/dpu: drop separate dpu_core_perf_tune overrides The values in struct dpu_core_perf_tune are fixed per the core perf mode. Drop the 'tune' values and substitute them with known values when performing perf management. Note: min_bus_vote was not used at all, so it is just silently dropped. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550208/ Link: https://lore.kernel.org/r/20230730010102.350713-4-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 27 ++++++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 4 --- 2 files changed, 11 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 3dbd73035a11..34f3d30ab7d6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -286,10 +286,16 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc) static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms) { - u64 clk_rate = kms->perf.perf_tune.min_core_clk; + u64 clk_rate; struct drm_crtc *crtc; struct dpu_crtc_state *dpu_cstate; + if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) + return kms->perf.fix_core_clk_rate; + + if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) + return kms->perf.max_core_clk_rate; + drm_for_each_crtc(crtc, kms->dev) { if (crtc->enabled) { dpu_cstate = to_dpu_crtc_state(crtc->state); @@ -300,11 +306,6 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms) } } - if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) - clk_rate = kms->perf.fix_core_clk_rate; - - DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate); - return clk_rate; } @@ -392,6 +393,8 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, if (update_clk) { clk_rate = _dpu_core_perf_get_core_clk_rate(kms); + DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate); + trace_dpu_core_perf_update_clk(kms->dev, stop_req, clk_rate); clk_rate = min(clk_rate, kms->perf.max_core_clk_rate); @@ -413,7 +416,6 @@ static ssize_t _dpu_core_perf_mode_write(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos) { struct dpu_core_perf *perf = file->private_data; - const struct dpu_perf_cfg *cfg = perf->catalog->perf; u32 perf_mode = 0; int ret; @@ -428,14 +430,9 @@ static ssize_t _dpu_core_perf_mode_write(struct file *file, DRM_INFO("fix performance mode\n"); } else if (perf_mode == DPU_PERF_MODE_MINIMUM) { /* run the driver with max clk and BW vote */ - perf->perf_tune.min_core_clk = perf->max_core_clk_rate; - perf->perf_tune.min_bus_vote = - (u64) cfg->max_bw_high * 1000; DRM_INFO("minimum performance mode\n"); } else if (perf_mode == DPU_PERF_MODE_NORMAL) { /* reset the perf tune params to 0 */ - perf->perf_tune.min_core_clk = 0; - perf->perf_tune.min_bus_vote = 0; DRM_INFO("normal performance mode\n"); } perf->perf_tune.mode = perf_mode; @@ -451,10 +448,8 @@ static ssize_t _dpu_core_perf_mode_read(struct file *file, char buf[128]; len = scnprintf(buf, sizeof(buf), - "mode %d min_mdp_clk %llu min_bus_vote %llu\n", - perf->perf_tune.mode, - perf->perf_tune.min_core_clk, - perf->perf_tune.min_bus_vote); + "mode %d\n", + perf->perf_tune.mode); return simple_read_from_buffer(buff, count, ppos, buf, len); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h index 29bb8ee2bc26..c965dfbc3007 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h @@ -29,13 +29,9 @@ struct dpu_core_perf_params { /** * struct dpu_core_perf_tune - definition of performance tuning control * @mode: performance mode - * @min_core_clk: minimum core clock - * @min_bus_vote: minimum bus vote */ struct dpu_core_perf_tune { u32 mode; - u64 min_core_clk; - u64 min_bus_vote; }; /** From a6239e65c801a1c0556fe5df02fda4720a371ded Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 30 Jul 2023 04:00:56 +0300 Subject: [PATCH 070/118] drm/msm/dpu: rework indentation in dpu_core_perf dpu_core_perf.c contains several multi-line conditions which are hard to comprehent because of the indentation. Rework the identation of these conditions to make it easier to understand them. Reviewed-by: Abhinav Kumar Acked-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550197/ Link: https://lore.kernel.org/r/20230730010102.350713-5-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 34f3d30ab7d6..6ddbedb83e66 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -173,8 +173,8 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, drm_for_each_crtc(tmp_crtc, crtc->dev) { if (tmp_crtc->enabled && - (dpu_crtc_get_client_type(tmp_crtc) == - curr_client_type) && (tmp_crtc != crtc)) { + dpu_crtc_get_client_type(tmp_crtc) == curr_client_type && + tmp_crtc != crtc) { struct dpu_crtc_state *tmp_cstate = to_dpu_crtc_state(tmp_crtc->state); @@ -360,10 +360,8 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, update_bus = true; } - if ((params_changed && - (new->core_clk_rate > old->core_clk_rate)) || - (!params_changed && - (new->core_clk_rate < old->core_clk_rate))) { + if ((params_changed && new->core_clk_rate > old->core_clk_rate) || + (!params_changed && new->core_clk_rate < old->core_clk_rate)) { old->core_clk_rate = new->core_clk_rate; update_clk = true; } From 716f0d4cac0f4f420524ee330cacbe7f42fafecc Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 30 Jul 2023 04:00:57 +0300 Subject: [PATCH 071/118] drm/msm/dpu: drop the dpu_core_perf_crtc_update()'s stop_req param The stop_req is true only in the dpu_crtc_disable() case, when crtc->enable has already been set to false. This renders the stop_req argument useless. Remove it completely. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550206/ Link: https://lore.kernel.org/r/20230730010102.350713-6-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 3 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 6 +++--- 3 files changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 6ddbedb83e66..209e4fcca663 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -310,7 +310,7 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms) } int dpu_core_perf_crtc_update(struct drm_crtc *crtc, - int params_changed, bool stop_req) + int params_changed) { struct dpu_core_perf_params *new, *old; bool update_bus = false, update_clk = false; @@ -334,13 +334,13 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, dpu_crtc = to_dpu_crtc(crtc); dpu_cstate = to_dpu_crtc_state(crtc->state); - DRM_DEBUG_ATOMIC("crtc:%d stop_req:%d core_clk:%llu\n", - crtc->base.id, stop_req, kms->perf.core_clk_rate); + DRM_DEBUG_ATOMIC("crtc:%d enabled:%d core_clk:%llu\n", + crtc->base.id, crtc->enabled, kms->perf.core_clk_rate); old = &dpu_crtc->cur_perf; new = &dpu_cstate->new_perf; - if (crtc->enabled && !stop_req) { + if (crtc->enabled) { /* * cases for bus bandwidth update. * 1. new bandwidth vote - "ab or ib vote" is higher @@ -373,7 +373,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, } trace_dpu_perf_crtc_update(crtc->base.id, new->bw_ctl, - new->core_clk_rate, stop_req, update_bus, update_clk); + new->core_clk_rate, !crtc->enabled, update_bus, update_clk); if (update_bus) { ret = _dpu_core_perf_crtc_update_bus(kms, crtc); @@ -393,7 +393,7 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, DRM_DEBUG_ATOMIC("clk:%llu\n", clk_rate); - trace_dpu_core_perf_update_clk(kms->dev, stop_req, clk_rate); + trace_dpu_core_perf_update_clk(kms->dev, !crtc->enabled, clk_rate); clk_rate = min(clk_rate, kms->perf.max_core_clk_rate); ret = dev_pm_opp_set_rate(&kms->pdev->dev, clk_rate); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h index c965dfbc3007..c0097b67f9dd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h @@ -75,11 +75,10 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, * dpu_core_perf_crtc_update - update performance of the given crtc * @crtc: Pointer to crtc * @params_changed: true if crtc parameters are modified - * @stop_req: true if this is a stop request * return: zero if success, or error code otherwise */ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, - int params_changed, bool stop_req); + int params_changed); /** * dpu_core_perf_crtc_release_bw - release bandwidth of the given crtc diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 1edf2b6b0a26..8ce7586e2ddf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -718,7 +718,7 @@ static void dpu_crtc_frame_event_cb(void *data, u32 event) void dpu_crtc_complete_commit(struct drm_crtc *crtc) { trace_dpu_crtc_complete_commit(DRMID(crtc)); - dpu_core_perf_crtc_update(crtc, 0, false); + dpu_core_perf_crtc_update(crtc, 0); _dpu_crtc_complete_flip(crtc); } @@ -884,7 +884,7 @@ static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, return; /* update performance setting before crtc kickoff */ - dpu_core_perf_crtc_update(crtc, 1, false); + dpu_core_perf_crtc_update(crtc, 1); /* * Final plane updates: Give each plane a chance to complete all @@ -1100,7 +1100,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc, atomic_set(&dpu_crtc->frame_pending, 0); } - dpu_core_perf_crtc_update(crtc, 0, true); + dpu_core_perf_crtc_update(crtc, 0); drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) dpu_encoder_register_frame_event_callback(encoder, NULL, NULL); From 779f336ed4b8335e11441a400c5e5ffc4d7b57d0 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 30 Jul 2023 04:00:58 +0300 Subject: [PATCH 072/118] drm/msm/dpu: use dpu_perf_cfg in DPU core_perf code Simplify dpu_core_perf code by using only dpu_perf_cfg instead of using full-featured catalog data. Acked-by: Konrad Dybcio Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550198/ Link: https://lore.kernel.org/r/20230730010102.350713-7-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 73 ++++++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 8 +- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- 3 files changed, 35 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 209e4fcca663..f9585d717902 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -33,11 +33,11 @@ enum dpu_perf_mode { /** * _dpu_core_perf_calc_bw() - to calculate BW per crtc - * @kms: pointer to the dpu_kms + * @perf_cfg: performance configuration * @crtc: pointer to a crtc * Return: returns aggregated BW for all planes in crtc. */ -static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms, +static u64 _dpu_core_perf_calc_bw(const struct dpu_perf_cfg *perf_cfg, struct drm_crtc *crtc) { struct drm_plane *plane; @@ -53,7 +53,7 @@ static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms, crtc_plane_bw += pstate->plane_fetch_bw; } - bw_factor = kms->catalog->perf->bw_inefficiency_factor; + bw_factor = perf_cfg->bw_inefficiency_factor; if (bw_factor) { crtc_plane_bw *= bw_factor; do_div(crtc_plane_bw, 100); @@ -64,12 +64,12 @@ static u64 _dpu_core_perf_calc_bw(struct dpu_kms *kms, /** * _dpu_core_perf_calc_clk() - to calculate clock per crtc - * @kms: pointer to the dpu_kms + * @perf_cfg: performance configuration * @crtc: pointer to a crtc * @state: pointer to a crtc state * Return: returns max clk for all planes in crtc. */ -static u64 _dpu_core_perf_calc_clk(struct dpu_kms *kms, +static u64 _dpu_core_perf_calc_clk(const struct dpu_perf_cfg *perf_cfg, struct drm_crtc *crtc, struct drm_crtc_state *state) { struct drm_plane *plane; @@ -90,7 +90,7 @@ static u64 _dpu_core_perf_calc_clk(struct dpu_kms *kms, crtc_clk = max(pstate->plane_clk, crtc_clk); } - clk_factor = kms->catalog->perf->clk_inefficiency_factor; + clk_factor = perf_cfg->clk_inefficiency_factor; if (clk_factor) { crtc_clk *= clk_factor; do_div(crtc_clk, 100); @@ -106,30 +106,32 @@ static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc) return to_dpu_kms(priv->kms); } -static void _dpu_core_perf_calc_crtc(struct dpu_kms *kms, - struct drm_crtc *crtc, - struct drm_crtc_state *state, - struct dpu_core_perf_params *perf) +static void _dpu_core_perf_calc_crtc(const struct dpu_core_perf *core_perf, + struct drm_crtc *crtc, + struct drm_crtc_state *state, + struct dpu_core_perf_params *perf) { - if (!kms || !kms->catalog || !crtc || !state || !perf) { + const struct dpu_perf_cfg *perf_cfg = core_perf->perf_cfg; + + if (!perf_cfg || !crtc || !state || !perf) { DPU_ERROR("invalid parameters\n"); return; } memset(perf, 0, sizeof(struct dpu_core_perf_params)); - if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) { + if (core_perf->perf_tune.mode == DPU_PERF_MODE_MINIMUM) { perf->bw_ctl = 0; perf->max_per_pipe_ib = 0; perf->core_clk_rate = 0; - } else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) { - perf->bw_ctl = kms->perf.fix_core_ab_vote; - perf->max_per_pipe_ib = kms->perf.fix_core_ib_vote; - perf->core_clk_rate = kms->perf.fix_core_clk_rate; + } else if (core_perf->perf_tune.mode == DPU_PERF_MODE_FIXED) { + perf->bw_ctl = core_perf->fix_core_ab_vote; + perf->max_per_pipe_ib = core_perf->fix_core_ib_vote; + perf->core_clk_rate = core_perf->fix_core_clk_rate; } else { - perf->bw_ctl = _dpu_core_perf_calc_bw(kms, crtc); - perf->max_per_pipe_ib = kms->catalog->perf->min_dram_ib; - perf->core_clk_rate = _dpu_core_perf_calc_clk(kms, crtc, state); + perf->bw_ctl = _dpu_core_perf_calc_bw(perf_cfg, crtc); + perf->max_per_pipe_ib = perf_cfg->min_dram_ib; + perf->core_clk_rate = _dpu_core_perf_calc_clk(perf_cfg, crtc, state); } DRM_DEBUG_ATOMIC( @@ -154,10 +156,6 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, } kms = _dpu_crtc_get_kms(crtc); - if (!kms->catalog) { - DPU_ERROR("invalid parameters\n"); - return 0; - } /* we only need bandwidth check on real-time clients (interfaces) */ if (dpu_crtc_get_client_type(crtc) == NRT_CLIENT) @@ -166,7 +164,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, dpu_cstate = to_dpu_crtc_state(state); /* obtain new values */ - _dpu_core_perf_calc_crtc(kms, crtc, state, &dpu_cstate->new_perf); + _dpu_core_perf_calc_crtc(&kms->perf, crtc, state, &dpu_cstate->new_perf); bw_sum_of_intfs = dpu_cstate->new_perf.bw_ctl; curr_client_type = dpu_crtc_get_client_type(crtc); @@ -189,7 +187,7 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, bw = DIV_ROUND_UP_ULL(bw_sum_of_intfs, 1000); DRM_DEBUG_ATOMIC("calculated bandwidth=%uk\n", bw); - threshold = kms->catalog->perf->max_bw_high; + threshold = kms->perf.perf_cfg->max_bw_high; DRM_DEBUG_ATOMIC("final threshold bw limit = %d\n", threshold); @@ -265,11 +263,6 @@ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc) } kms = _dpu_crtc_get_kms(crtc); - if (!kms->catalog) { - DPU_ERROR("invalid kms\n"); - return; - } - dpu_crtc = to_dpu_crtc(crtc); if (atomic_dec_return(&kms->bandwidth_ref) > 0) @@ -326,10 +319,6 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, } kms = _dpu_crtc_get_kms(crtc); - if (!kms->catalog) { - DPU_ERROR("invalid kms\n"); - return -EINVAL; - } dpu_crtc = to_dpu_crtc(crtc); dpu_cstate = to_dpu_crtc_state(crtc->state); @@ -461,7 +450,6 @@ static const struct file_operations dpu_core_perf_mode_fops = { int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent) { struct dpu_core_perf *perf = &dpu_kms->perf; - const struct dpu_mdss_cfg *catalog = perf->catalog; struct dentry *entry; entry = debugfs_create_dir("core_perf", parent); @@ -473,15 +461,15 @@ int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent) debugfs_create_u32("enable_bw_release", 0600, entry, (u32 *)&perf->enable_bw_release); debugfs_create_u32("threshold_low", 0600, entry, - (u32 *)&catalog->perf->max_bw_low); + (u32 *)&perf->perf_cfg->max_bw_low); debugfs_create_u32("threshold_high", 0600, entry, - (u32 *)&catalog->perf->max_bw_high); + (u32 *)&perf->perf_cfg->max_bw_high); debugfs_create_u32("min_core_ib", 0600, entry, - (u32 *)&catalog->perf->min_core_ib); + (u32 *)&perf->perf_cfg->min_core_ib); debugfs_create_u32("min_llcc_ib", 0600, entry, - (u32 *)&catalog->perf->min_llcc_ib); + (u32 *)&perf->perf_cfg->min_llcc_ib); debugfs_create_u32("min_dram_ib", 0600, entry, - (u32 *)&catalog->perf->min_dram_ib); + (u32 *)&perf->perf_cfg->min_dram_ib); debugfs_create_file("perf_mode", 0600, entry, (u32 *)perf, &dpu_core_perf_mode_fops); debugfs_create_u64("fix_core_clk_rate", 0600, entry, @@ -504,17 +492,16 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf) perf->max_core_clk_rate = 0; perf->core_clk = NULL; - perf->catalog = NULL; perf->dev = NULL; } int dpu_core_perf_init(struct dpu_core_perf *perf, struct drm_device *dev, - const struct dpu_mdss_cfg *catalog, + const struct dpu_perf_cfg *perf_cfg, struct clk *core_clk) { perf->dev = dev; - perf->catalog = catalog; + perf->perf_cfg = perf_cfg; perf->core_clk = core_clk; perf->max_core_clk_rate = clk_get_rate(core_clk); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h index c0097b67f9dd..f4b84e67138c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h @@ -38,7 +38,7 @@ struct dpu_core_perf_tune { * struct dpu_core_perf - definition of core performance context * @dev: Pointer to drm device * @debugfs_root: top level debug folder - * @catalog: Pointer to catalog configuration + * @perf_cfg: Platform-specific performance configuration * @core_clk: Pointer to the core clock * @core_clk_rate: current core clock rate * @max_core_clk_rate: maximum allowable core clock rate @@ -51,7 +51,7 @@ struct dpu_core_perf_tune { struct dpu_core_perf { struct drm_device *dev; struct dentry *debugfs_root; - const struct dpu_mdss_cfg *catalog; + const struct dpu_perf_cfg *perf_cfg; struct clk *core_clk; u64 core_clk_rate; u64 max_core_clk_rate; @@ -96,12 +96,12 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf); * dpu_core_perf_init - initialize the given core performance context * @perf: Pointer to core performance context * @dev: Pointer to drm device - * @catalog: Pointer to catalog + * @perf_cfg: Pointer to platform performance configuration * @core_clk: pointer to core clock */ int dpu_core_perf_init(struct dpu_core_perf *perf, struct drm_device *dev, - const struct dpu_mdss_cfg *catalog, + const struct dpu_perf_cfg *perf_cfg, struct clk *core_clk); struct dpu_kms; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 2da9eef687af..03a2ef7842d0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1170,7 +1170,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms) dpu_kms->hw_vbif[vbif->id] = hw; } - rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog, + rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog->perf, msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, "core")); if (rc) { DPU_ERROR("failed to init perf %d\n", rc); From 7a735940293dc3adae2d412025ae7e52c765dd26 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 30 Jul 2023 04:00:59 +0300 Subject: [PATCH 073/118] drm/msm/dpu: remove unused fields from struct dpu_core_perf Remove dpu_core_perf::dev and dpu_core_perf::debugfs_root fields, they are not used by the code. Reviewed-by: Konrad Dybcio Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550200/ Link: https://lore.kernel.org/r/20230730010102.350713-8-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 3 --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +- 3 files changed, 1 insertion(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index f9585d717902..3dddec868bf5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -492,15 +492,12 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf) perf->max_core_clk_rate = 0; perf->core_clk = NULL; - perf->dev = NULL; } int dpu_core_perf_init(struct dpu_core_perf *perf, - struct drm_device *dev, const struct dpu_perf_cfg *perf_cfg, struct clk *core_clk) { - perf->dev = dev; perf->perf_cfg = perf_cfg; perf->core_clk = core_clk; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h index f4b84e67138c..e718d523ff30 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h @@ -36,8 +36,6 @@ struct dpu_core_perf_tune { /** * struct dpu_core_perf - definition of core performance context - * @dev: Pointer to drm device - * @debugfs_root: top level debug folder * @perf_cfg: Platform-specific performance configuration * @core_clk: Pointer to the core clock * @core_clk_rate: current core clock rate @@ -49,8 +47,6 @@ struct dpu_core_perf_tune { * @fix_core_ab_vote: fixed core ab vote in bps used in mode 2 */ struct dpu_core_perf { - struct drm_device *dev; - struct dentry *debugfs_root; const struct dpu_perf_cfg *perf_cfg; struct clk *core_clk; u64 core_clk_rate; @@ -95,12 +91,10 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf); /** * dpu_core_perf_init - initialize the given core performance context * @perf: Pointer to core performance context - * @dev: Pointer to drm device * @perf_cfg: Pointer to platform performance configuration * @core_clk: pointer to core clock */ int dpu_core_perf_init(struct dpu_core_perf *perf, - struct drm_device *dev, const struct dpu_perf_cfg *perf_cfg, struct clk *core_clk); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 03a2ef7842d0..1d440c68ccbb 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1170,7 +1170,7 @@ static int dpu_kms_hw_init(struct msm_kms *kms) dpu_kms->hw_vbif[vbif->id] = hw; } - rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog->perf, + rc = dpu_core_perf_init(&dpu_kms->perf, dpu_kms->catalog->perf, msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, "core")); if (rc) { DPU_ERROR("failed to init perf %d\n", rc); From d64d83806aa46be7b400663509fb47c80877cab6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 30 Jul 2023 04:01:00 +0300 Subject: [PATCH 074/118] drm/msm/dpu: remove extra clk_round_rate() call The dev_pm_opp_set_rate() already contains a call for clk_round_rate for the passed value. Stop calling it manually from _dpu_core_perf_get_core_clk_rate(). It is slightly incorrect to call it this way, as we should round the final calculated clock rate rather than rounding all the intermediate values. Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550212/ Link: https://lore.kernel.org/r/20230730010102.350713-9-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 3dddec868bf5..6a0f0ede4781 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -294,8 +294,6 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms) dpu_cstate = to_dpu_crtc_state(crtc->state); clk_rate = max(dpu_cstate->new_perf.core_clk_rate, clk_rate); - clk_rate = clk_round_rate(kms->perf.core_clk, - clk_rate); } } From 4161ec7e93d1ee15da54251e9f2319b88f66d976 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 30 Jul 2023 04:01:01 +0300 Subject: [PATCH 075/118] drm/msm/dpu: move max clock decision to dpu_kms. dpu_core_perf should not make decisions on the maximum possible core clock rate. Pass the value from dpu_kms_hw_init() and drop handling of core_clk from dpu_core_perf.c Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550201/ Link: https://lore.kernel.org/r/20230730010102.350713-10-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 11 ++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 8 ++------ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 13 +++++++++++-- 3 files changed, 15 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 6a0f0ede4781..665b7b21a817 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -489,21 +489,14 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf) } perf->max_core_clk_rate = 0; - perf->core_clk = NULL; } int dpu_core_perf_init(struct dpu_core_perf *perf, const struct dpu_perf_cfg *perf_cfg, - struct clk *core_clk) + unsigned long max_core_clk_rate) { perf->perf_cfg = perf_cfg; - perf->core_clk = core_clk; - - perf->max_core_clk_rate = clk_get_rate(core_clk); - if (!perf->max_core_clk_rate) { - DPU_DEBUG("optional max core clk rate, use default\n"); - perf->max_core_clk_rate = DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE; - } + perf->max_core_clk_rate = max_core_clk_rate; return 0; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h index e718d523ff30..8cc55752db5e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h @@ -12,8 +12,6 @@ #include "dpu_hw_catalog.h" -#define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000 - /** * struct dpu_core_perf_params - definition of performance parameters * @max_per_pipe_ib: maximum instantaneous bandwidth request @@ -37,7 +35,6 @@ struct dpu_core_perf_tune { /** * struct dpu_core_perf - definition of core performance context * @perf_cfg: Platform-specific performance configuration - * @core_clk: Pointer to the core clock * @core_clk_rate: current core clock rate * @max_core_clk_rate: maximum allowable core clock rate * @perf_tune: debug control for performance tuning @@ -48,7 +45,6 @@ struct dpu_core_perf_tune { */ struct dpu_core_perf { const struct dpu_perf_cfg *perf_cfg; - struct clk *core_clk; u64 core_clk_rate; u64 max_core_clk_rate; struct dpu_core_perf_tune perf_tune; @@ -92,11 +88,11 @@ void dpu_core_perf_destroy(struct dpu_core_perf *perf); * dpu_core_perf_init - initialize the given core performance context * @perf: Pointer to core performance context * @perf_cfg: Pointer to platform performance configuration - * @core_clk: pointer to core clock + * @max_core_clk_rate: Maximum core clock rate */ int dpu_core_perf_init(struct dpu_core_perf *perf, const struct dpu_perf_cfg *perf_cfg, - struct clk *core_clk); + unsigned long max_core_clk_rate); struct dpu_kms; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 1d440c68ccbb..46950e60acb9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1052,11 +1052,14 @@ unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name) return clk_get_rate(clk); } +#define DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE 412500000 + static int dpu_kms_hw_init(struct msm_kms *kms) { struct dpu_kms *dpu_kms; struct drm_device *dev; int i, rc = -EINVAL; + unsigned long max_core_clk_rate; u32 core_rev; if (!kms) { @@ -1170,8 +1173,14 @@ static int dpu_kms_hw_init(struct msm_kms *kms) dpu_kms->hw_vbif[vbif->id] = hw; } - rc = dpu_core_perf_init(&dpu_kms->perf, dpu_kms->catalog->perf, - msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, "core")); + /* TODO: use the same max_freq as in dpu_kms_hw_init */ + max_core_clk_rate = dpu_kms_get_clk_rate(dpu_kms, "core"); + if (!max_core_clk_rate) { + DPU_DEBUG("max core clk rate not determined, using default\n"); + max_core_clk_rate = DPU_PERF_DEFAULT_MAX_CORE_CLK_RATE; + } + + rc = dpu_core_perf_init(&dpu_kms->perf, dpu_kms->catalog->perf, max_core_clk_rate); if (rc) { DPU_ERROR("failed to init perf %d\n", rc); goto perf_err; From 3d5199a173d06fdd08e87a32174ef9bea339e6be Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 30 Jul 2023 04:01:02 +0300 Subject: [PATCH 076/118] drm/msm/dpu: drop dpu_core_perf_destroy() This function does nothing, just clears one struct field. Drop it now. Acked-by: Konrad Dybcio Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550210/ Link: https://lore.kernel.org/r/20230730010102.350713-11-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 10 ---------- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 - 3 files changed, 17 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 665b7b21a817..0b54a659a940 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -481,16 +481,6 @@ int dpu_core_perf_debugfs_init(struct dpu_kms *dpu_kms, struct dentry *parent) } #endif -void dpu_core_perf_destroy(struct dpu_core_perf *perf) -{ - if (!perf) { - DPU_ERROR("invalid parameters\n"); - return; - } - - perf->max_core_clk_rate = 0; -} - int dpu_core_perf_init(struct dpu_core_perf *perf, const struct dpu_perf_cfg *perf_cfg, unsigned long max_core_clk_rate) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h index 8cc55752db5e..4186977390bd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h @@ -78,12 +78,6 @@ int dpu_core_perf_crtc_update(struct drm_crtc *crtc, */ void dpu_core_perf_crtc_release_bw(struct drm_crtc *crtc); -/** - * dpu_core_perf_destroy - destroy the given core performance context - * @perf: Pointer to core performance context - */ -void dpu_core_perf_destroy(struct dpu_core_perf *perf); - /** * dpu_core_perf_init - initialize the given core performance context * @perf: Pointer to core performance context diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 46950e60acb9..aa6ba2cf4b84 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1226,7 +1226,6 @@ static int dpu_kms_hw_init(struct msm_kms *kms) return 0; drm_obj_init_err: - dpu_core_perf_destroy(&dpu_kms->perf); hw_intr_init_err: perf_err: power_error: From 42d0d253ed03b961c325ff756eec0480cb4adc6b Mon Sep 17 00:00:00 2001 From: Jonathan Marek Date: Wed, 2 Aug 2023 09:48:53 -0400 Subject: [PATCH 077/118] drm/msm/dpu: increase memtype count to 16 for sm8550 sm8550 has 16 vbif clients. This fixes the extra 2 clients (DMA4/DMA5) not having their memtype initialized. This fixes DMA4/DMA5 planes not displaying correctly. Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550") Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov Tested-by: Neil Armstrong # on SM8550-QRD Patchwork: https://patchwork.freedesktop.org/patch/550968/ Link: https://lore.kernel.org/r/20230802134900.30435-1-jonathan@marek.ca [DB: fixed the Fixes tag] Signed-off-by: Dmitry Baryshkov --- .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ++-- .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++++++++++ 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 833be1167499..c43bda0bc708 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -440,8 +440,8 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = { .merge_3d = sm8550_merge_3d, .intf_count = ARRAY_SIZE(sm8550_intf), .intf = sm8550_intf, - .vbif_count = ARRAY_SIZE(sdm845_vbif), - .vbif = sdm845_vbif, + .vbif_count = ARRAY_SIZE(sm8550_vbif), + .vbif = sm8550_vbif, .perf = &sm8550_perf_data, }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 3ff07d7cbf4b..ce369eeffa7d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -539,6 +539,26 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = { }, }; +static const struct dpu_vbif_cfg sm8550_vbif[] = { + { + .name = "vbif_rt", .id = VBIF_RT, + .base = 0, .len = 0x1040, + .features = BIT(DPU_VBIF_QOS_REMAP), + .xin_halt_timeout = 0x4000, + .qos_rp_remap_size = 0x40, + .qos_rt_tbl = { + .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), + .priority_lvl = sdm845_rt_pri_lvl, + }, + .qos_nrt_tbl = { + .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), + .priority_lvl = sdm845_nrt_pri_lvl, + }, + .memtype_count = 16, + .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, + }, +}; + /************************************************************* * PERF data config *************************************************************/ From e550ad0e5c3d1a521413e6efb22729698a70110b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 2 Aug 2023 21:36:54 +0300 Subject: [PATCH 078/118] drm/msm/dpu: fix DSC 1.2 block lengths All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length. This includes the common block itself, enc subblocks and some empty space around. Change that to pass 0x4 instead, the length of common register block itself. Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets") Reported-by: Ryan McCann Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/550998/ Link: https://lore.kernel.org/r/20230802183655.4188640-1-dmitry.baryshkov@linaro.org --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 8 ++++---- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 12 ++++++------ .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 8 ++++---- .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 8 ++++---- 5 files changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index c906b6864b5e..f8d16f9bf528 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -283,22 +283,22 @@ static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = { static const struct dpu_dsc_cfg sm8350_dsc[] = { { .name = "dce_0_0", .id = DSC_0, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_0, }, { .name = "dce_0_1", .id = DSC_1, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_1, }, { .name = "dce_1_0", .id = DSC_2, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_0, }, { .name = "dce_1_1", .id = DSC_3, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_1, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 2bf9f34e54c6..3b5061c4402a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -163,7 +163,7 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { static const struct dpu_dsc_cfg sc7280_dsc[] = { { .name = "dce_0_0", .id = DSC_0, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_0, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index ccd0477f4877..58f5e25679b1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -286,32 +286,32 @@ static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = { static const struct dpu_dsc_cfg sc8280xp_dsc[] = { { .name = "dce_0_0", .id = DSC_0, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_0, }, { .name = "dce_0_1", .id = DSC_1, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_1, }, { .name = "dce_1_0", .id = DSC_2, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_0, }, { .name = "dce_1_1", .id = DSC_3, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_1, }, { .name = "dce_2_0", .id = DSC_4, - .base = 0x82000, .len = 0x29c, + .base = 0x82000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_0, }, { .name = "dce_2_1", .id = DSC_5, - .base = 0x82000, .len = 0x29c, + .base = 0x82000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_1, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 2b2e9d4800f8..1b12178dfbca 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -305,22 +305,22 @@ static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { static const struct dpu_dsc_cfg sm8450_dsc[] = { { .name = "dce_0_0", .id = DSC_0, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_0, }, { .name = "dce_0_1", .id = DSC_1, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_1, }, { .name = "dce_1_0", .id = DSC_2, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_0, }, { .name = "dce_1_1", .id = DSC_3, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_1, }, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index c43bda0bc708..7bed819dfc39 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -320,22 +320,22 @@ static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { static const struct dpu_dsc_cfg sm8550_dsc[] = { { .name = "dce_0_0", .id = DSC_0, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_0, }, { .name = "dce_0_1", .id = DSC_1, - .base = 0x80000, .len = 0x29c, + .base = 0x80000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2), .sblk = &dsc_sblk_1, }, { .name = "dce_1_0", .id = DSC_2, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_0, }, { .name = "dce_1_1", .id = DSC_3, - .base = 0x81000, .len = 0x29c, + .base = 0x81000, .len = 0x4, .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), .sblk = &dsc_sblk_1, }, From 57a1ca6cf73b164ff93c2a541a6fc2337fd07b20 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 2 Aug 2023 21:36:55 +0300 Subject: [PATCH 079/118] drm/msm/dpu: fix DSC 1.2 enc subblock length Both struct dpu_dsc_sub_blks instances declare enc subblock length to be 0x100, while the actual length is 0x9c (last register having offset 0x98). Reduce subblock length to remove the empty register space from being dumped. Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets") Reviewed-by: Abhinav Kumar Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550999/ Link: https://lore.kernel.org/r/20230802183655.4188640-2-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index ce369eeffa7d..713dfc079718 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -456,12 +456,12 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { * DSC sub blocks config *************************************************************/ static const struct dpu_dsc_sub_blks dsc_sblk_0 = { - .enc = {.name = "enc", .base = 0x100, .len = 0x100}, + .enc = {.name = "enc", .base = 0x100, .len = 0x9c}, .ctl = {.name = "ctl", .base = 0xF00, .len = 0x10}, }; static const struct dpu_dsc_sub_blks dsc_sblk_1 = { - .enc = {.name = "enc", .base = 0x200, .len = 0x100}, + .enc = {.name = "enc", .base = 0x200, .len = 0x9c}, .ctl = {.name = "ctl", .base = 0xF80, .len = 0x10}, }; From fdcb8fe0c9f0dfa8377f6b6a7e5b16aa0bec72f2 Mon Sep 17 00:00:00 2001 From: Jessica Zhang Date: Wed, 2 Aug 2023 10:01:13 -0700 Subject: [PATCH 080/118] drm/msm/dpu: Drop encoder vsync_event Drop vsync_event and vsync_event_work handlers as they are unnecessary. In addition drop the dpu_enc_ktime_template event class as it will be unused after the vsync_event handlers are dropped. Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550983/ Link: https://lore.kernel.org/r/20230802-encoder-cleanup-v2-1-5bfdec0ce765@quicinc.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 65 +-------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 23 -------- 2 files changed, 1 insertion(+), 87 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index f0a2a1dca741..d34e684a4178 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -152,7 +152,6 @@ enum dpu_enc_rc_states { * @crtc_frame_event_cb_data: callback handler private data * @frame_done_timeout_ms: frame done timeout in ms * @frame_done_timer: watchdog timer for frame done event - * @vsync_event_timer: vsync timer * @disp_info: local copy of msm_display_info struct * @idle_pc_supported: indicate if idle power collaps is supported * @rc_lock: resource control mutex lock to protect @@ -160,7 +159,6 @@ enum dpu_enc_rc_states { * @rc_state: resource controller state * @delayed_off_work: delayed worker to schedule disabling of * clks and resources after IDLE_TIMEOUT time. - * @vsync_event_work: worker to handle vsync event for autorefresh * @topology: topology of the display * @idle_timeout: idle timeout duration in milliseconds * @wide_bus_en: wide bus is enabled on this interface @@ -194,7 +192,6 @@ struct dpu_encoder_virt { atomic_t frame_done_timeout_ms; struct timer_list frame_done_timer; - struct timer_list vsync_event_timer; struct msm_display_info disp_info; @@ -202,7 +199,6 @@ struct dpu_encoder_virt { struct mutex rc_lock; enum dpu_enc_rc_states rc_state; struct delayed_work delayed_off_work; - struct kthread_work vsync_event_work; struct msm_display_topology topology; u32 idle_timeout; @@ -1770,49 +1766,6 @@ int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time) return 0; } -static void dpu_encoder_vsync_event_handler(struct timer_list *t) -{ - struct dpu_encoder_virt *dpu_enc = from_timer(dpu_enc, t, - vsync_event_timer); - struct drm_encoder *drm_enc = &dpu_enc->base; - struct msm_drm_private *priv; - struct msm_drm_thread *event_thread; - - if (!drm_enc->dev || !drm_enc->crtc) { - DPU_ERROR("invalid parameters\n"); - return; - } - - priv = drm_enc->dev->dev_private; - - if (drm_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) { - DPU_ERROR("invalid crtc index\n"); - return; - } - event_thread = &priv->event_thread[drm_enc->crtc->index]; - if (!event_thread) { - DPU_ERROR("event_thread not found for crtc:%d\n", - drm_enc->crtc->index); - return; - } - - del_timer(&dpu_enc->vsync_event_timer); -} - -static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) -{ - struct dpu_encoder_virt *dpu_enc = container_of(work, - struct dpu_encoder_virt, vsync_event_work); - ktime_t wakeup_time; - - if (dpu_encoder_vsync_time(&dpu_enc->base, &wakeup_time)) - return; - - trace_dpu_enc_vsync_event_work(DRMID(&dpu_enc->base), wakeup_time); - mod_timer(&dpu_enc->vsync_event_timer, - nsecs_to_jiffies(ktime_to_ns(wakeup_time))); -} - static u32 dpu_encoder_dsc_initial_line_calc(struct drm_dsc_config *dsc, u32 enc_ip_width) @@ -1972,7 +1925,6 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc) { struct dpu_encoder_virt *dpu_enc; struct dpu_encoder_phys *phys; - ktime_t wakeup_time; unsigned long timeout_ms; unsigned int i; @@ -1998,14 +1950,6 @@ void dpu_encoder_kickoff(struct drm_encoder *drm_enc) phys->ops.handle_post_kickoff(phys); } - if (dpu_enc->disp_info.intf_type == INTF_DSI && - !dpu_encoder_vsync_time(drm_enc, &wakeup_time)) { - trace_dpu_enc_early_kickoff(DRMID(drm_enc), - ktime_to_ms(wakeup_time)); - mod_timer(&dpu_enc->vsync_event_timer, - nsecs_to_jiffies(ktime_to_ns(wakeup_time))); - } - DPU_ATRACE_END("encoder_kickoff"); } @@ -2439,11 +2383,7 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev, timer_setup(&dpu_enc->frame_done_timer, dpu_encoder_frame_done_timeout, 0); - if (disp_info->intf_type == INTF_DSI) - timer_setup(&dpu_enc->vsync_event_timer, - dpu_encoder_vsync_event_handler, - 0); - else if (disp_info->intf_type == INTF_DP) + if (disp_info->intf_type == INTF_DP) dpu_enc->wide_bus_en = msm_dp_wide_bus_available( priv->dp[disp_info->h_tile_instance[0]]); @@ -2451,9 +2391,6 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev, dpu_encoder_off_work); dpu_enc->idle_timeout = IDLE_TIMEOUT; - kthread_init_work(&dpu_enc->vsync_event_work, - dpu_encoder_vsync_event_work_handler); - memcpy(&dpu_enc->disp_info, disp_info, sizeof(*disp_info)); DPU_DEBUG_ENC(dpu_enc, "created\n"); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index 1a92d21094f4..c74b9be25e68 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -453,29 +453,6 @@ TRACE_EVENT(dpu_enc_trigger_flush, __entry->extra_flush_bits, __entry->pending_flush_ret) ); -DECLARE_EVENT_CLASS(dpu_enc_ktime_template, - TP_PROTO(uint32_t drm_id, ktime_t time), - TP_ARGS(drm_id, time), - TP_STRUCT__entry( - __field( uint32_t, drm_id ) - __field( ktime_t, time ) - ), - TP_fast_assign( - __entry->drm_id = drm_id; - __entry->time = time; - ), - TP_printk("id=%u, time=%lld", __entry->drm_id, - ktime_to_ms(__entry->time)) -); -DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_vsync_event_work, - TP_PROTO(uint32_t drm_id, ktime_t time), - TP_ARGS(drm_id, time) -); -DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_early_kickoff, - TP_PROTO(uint32_t drm_id, ktime_t time), - TP_ARGS(drm_id, time) -); - DECLARE_EVENT_CLASS(dpu_id_event_template, TP_PROTO(uint32_t drm_id, u32 event), TP_ARGS(drm_id, event), From fd0ad3b2365c1c58aa5a761c18efc4817193beb6 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 3 Aug 2023 22:45:21 +0200 Subject: [PATCH 081/118] drm/msm/mdp5: Don't leak some plane state Apparently no one noticed that mdp5 plane states leak like a sieve ever since we introduced plane_state->commit refcount a few years ago in 21a01abbe32a ("drm/atomic: Fix freeing connector/plane state too early by tracking commits, v3.") Fix it by using the right helpers. Fixes: 21a01abbe32a ("drm/atomic: Fix freeing connector/plane state too early by tracking commits, v3.") Cc: Maarten Lankhorst Cc: Daniel Vetter Cc: Rob Clark Cc: Abhinav Kumar Cc: Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Reported-and-tested-by: dorum@noisolation.com Cc: dorum@noisolation.com Signed-off-by: Daniel Vetter Reviewed-by: Rob Clark Reviewed-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/551236/ Link: https://lore.kernel.org/r/20230803204521.928582-1-daniel.vetter@ffwll.ch Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c index bd2c4ac45601..0d5ff03cb091 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c @@ -130,8 +130,7 @@ static void mdp5_plane_destroy_state(struct drm_plane *plane, { struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); - if (state->fb) - drm_framebuffer_put(state->fb); + __drm_atomic_helper_plane_destroy_state(state); kfree(pstate); } From b0fe70105056ca7f167000e35d9e0ea3d490fded Mon Sep 17 00:00:00 2001 From: Jiapeng Chong Date: Fri, 4 Aug 2023 15:57:46 +0800 Subject: [PATCH 082/118] drm/msm/dpu: clean up some inconsistent indenting No functional modification involved. drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c:183 dpu_core_perf_crtc_check() warn: inconsistent indenting. Reported-by: Abaci Robot Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6096 Signed-off-by: Jiapeng Chong Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/551313/ Link: https://lore.kernel.org/r/20230804075746.77435-1-jiapeng.chong@linux.alibaba.com Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 0b54a659a940..1c0e7e5480e4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -177,10 +177,10 @@ int dpu_core_perf_crtc_check(struct drm_crtc *crtc, to_dpu_crtc_state(tmp_crtc->state); DRM_DEBUG_ATOMIC("crtc:%d bw:%llu ctrl:%d\n", - tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl, - tmp_cstate->bw_control); + tmp_crtc->base.id, tmp_cstate->new_perf.bw_ctl, + tmp_cstate->bw_control); - bw_sum_of_intfs += tmp_cstate->new_perf.bw_ctl; + bw_sum_of_intfs += tmp_cstate->new_perf.bw_ctl; } /* convert bandwidth to kb */ From 34202be9523718838c620fdadf2e985890286883 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Fri, 4 Aug 2023 12:48:04 +0300 Subject: [PATCH 083/118] drm/msm/dpu: initialise clk_rate to 0 in _dpu_core_perf_get_core_clk_rate When removing the core perf tune overrides, I also occasionaly removed the initialisation of the clk_rate variable. Initialise it to 0 to let max() correctly calculate the maximum of requested clock rates. Reported-by: Dan Carpenter Fixes: 6a4bc73915af ("drm/msm/dpu: drop separate dpu_core_perf_tune overrides") Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/551321/ Link: https://lore.kernel.org/r/20230804094804.36053-1-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c index 1c0e7e5480e4..ef871239adb2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c @@ -289,6 +289,7 @@ static u64 _dpu_core_perf_get_core_clk_rate(struct dpu_kms *kms) if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) return kms->perf.max_core_clk_rate; + clk_rate = 0; drm_for_each_crtc(crtc, kms->dev) { if (crtc->enabled) { dpu_cstate = to_dpu_crtc_state(crtc->state); From d93cf453f51da168f4410ba73656f1e862096973 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 2 Aug 2023 13:04:19 +0300 Subject: [PATCH 084/118] drm/msm/dpu: fix the irq index in dpu_encoder_phys_wb_wait_for_commit_done Since commit 1e7ac595fa46 ("drm/msm/dpu: pass irq to dpu_encoder_helper_wait_for_irq()") the dpu_encoder_phys_wb_wait_for_commit_done expects the IRQ index rather than the IRQ index in phys_enc->intr table, however writeback got the older invocation in place. This was unnoticed for several releases, but now it's time to fix it. Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback") Signed-off-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/550924/ Link: https://lore.kernel.org/r/20230802100426.4184892-2-dmitry.baryshkov@linaro.org --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index a466ff70a4d6..78037a697633 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -446,7 +446,8 @@ static int dpu_encoder_phys_wb_wait_for_commit_done( wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt; wait_info.timeout_ms = KICKOFF_TIMEOUT_MS; - ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_WB_DONE, + ret = dpu_encoder_helper_wait_for_irq(phys_enc, + phys_enc->irq[INTR_IDX_WB_DONE], dpu_encoder_phys_wb_done_irq, &wait_info); if (ret == -ETIMEDOUT) _dpu_encoder_phys_wb_handle_wbdone_timeout(phys_enc); From 832ee64debddc07cc8062462825f5dfb618504ae Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 27 Jul 2023 14:20:06 -0700 Subject: [PATCH 085/118] drm/msm/adreno: Remove GPU name No real need to have marketing names in the kernel. Signed-off-by: Rob Clark Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549757/ --- drivers/gpu/drm/msm/adreno/adreno_device.c | 25 ---------------------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++++------ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 - 3 files changed, 5 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index ce8d0b2475bf..326912284a95 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -24,7 +24,6 @@ static const struct adreno_info gpulist[] = { { .rev = ADRENO_REV(2, 0, 0, 0), .revn = 200, - .name = "A200", .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", [ADRENO_FW_PFP] = "yamato_pfp.fw", @@ -35,7 +34,6 @@ static const struct adreno_info gpulist[] = { }, { /* a200 on i.mx51 has only 128kib gmem */ .rev = ADRENO_REV(2, 0, 0, 1), .revn = 201, - .name = "A200", .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", [ADRENO_FW_PFP] = "yamato_pfp.fw", @@ -46,7 +44,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(2, 2, 0, ANY_ID), .revn = 220, - .name = "A220", .fw = { [ADRENO_FW_PM4] = "leia_pm4_470.fw", [ADRENO_FW_PFP] = "leia_pfp_470.fw", @@ -57,7 +54,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 0, 5, ANY_ID), .revn = 305, - .name = "A305", .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", [ADRENO_FW_PFP] = "a300_pfp.fw", @@ -68,7 +64,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 0, 6, 0), .revn = 307, /* because a305c is revn==306 */ - .name = "A306", .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", [ADRENO_FW_PFP] = "a300_pfp.fw", @@ -79,7 +74,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), .revn = 320, - .name = "A320", .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", [ADRENO_FW_PFP] = "a300_pfp.fw", @@ -90,7 +84,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 3, 0, ANY_ID), .revn = 330, - .name = "A330", .fw = { [ADRENO_FW_PM4] = "a330_pm4.fw", [ADRENO_FW_PFP] = "a330_pfp.fw", @@ -101,7 +94,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(4, 0, 5, ANY_ID), .revn = 405, - .name = "A405", .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", [ADRENO_FW_PFP] = "a420_pfp.fw", @@ -112,7 +104,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(4, 2, 0, ANY_ID), .revn = 420, - .name = "A420", .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", [ADRENO_FW_PFP] = "a420_pfp.fw", @@ -123,7 +114,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(4, 3, 0, ANY_ID), .revn = 430, - .name = "A430", .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", [ADRENO_FW_PFP] = "a420_pfp.fw", @@ -134,7 +124,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 0, 6, ANY_ID), .revn = 506, - .name = "A506", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -152,7 +141,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 0, 8, ANY_ID), .revn = 508, - .name = "A508", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -169,7 +157,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 0, 9, ANY_ID), .revn = 509, - .name = "A509", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -187,7 +174,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 1, 0, ANY_ID), .revn = 510, - .name = "A510", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -202,7 +188,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 1, 2, ANY_ID), .revn = 512, - .name = "A512", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -219,7 +204,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 3, 0, 2), .revn = 530, - .name = "A530", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -238,7 +222,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 4, 0, ANY_ID), .revn = 540, - .name = "A540", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -256,7 +239,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 1, 0, ANY_ID), .revn = 610, - .name = "A610", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", }, @@ -268,7 +250,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), .revn = 618, - .name = "A618", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a630_gmu.bin", @@ -279,7 +260,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), .revn = 619, - .name = "A619", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a619_gmu.bin", @@ -292,7 +272,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 3, 0, ANY_ID), .revn = 630, - .name = "A630", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a630_gmu.bin", @@ -305,7 +284,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 4, 0, ANY_ID), .revn = 640, - .name = "A640", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a640_gmu.bin", @@ -318,7 +296,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 5, 0, ANY_ID), .revn = 650, - .name = "A650", .fw = { [ADRENO_FW_SQE] = "a650_sqe.fw", [ADRENO_FW_GMU] = "a650_gmu.bin", @@ -332,7 +309,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 6, 0, ANY_ID), .revn = 660, - .name = "A660", .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a660_gmu.bin", @@ -357,7 +333,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 8, 0, ANY_ID), .revn = 680, - .name = "A680", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a640_gmu.bin", diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 5c5901d65950..e3cd9ff6ff1d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1105,14 +1105,11 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, speedbin = 0xffff; adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); - gpu_name = adreno_gpu->info->name; - if (!gpu_name) { - gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d", - rev->core, rev->major, rev->minor, - rev->patchid); - if (!gpu_name) - return -ENOMEM; - } + gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d", + rev->core, rev->major, rev->minor, + rev->patchid); + if (!gpu_name) + return -ENOMEM; adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 845019891ad1..ac2350ebe035 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -61,7 +61,6 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; struct adreno_info { struct adreno_rev rev; uint32_t revn; - const char *name; const char *fw[ADRENO_FW_MAX]; uint32_t gmem; u64 quirks; From 6391030df06276ab9bdd1ee306787796974b64b3 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 27 Jul 2023 14:20:07 -0700 Subject: [PATCH 086/118] drm/msm/adreno: Remove redundant gmem size param Even in the ocmem case, the allocated ocmem buffer size should match the requested size. v2: Move stray hunk to previous patch, make OCMEM size mismatch an error condition. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549759/ --- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 9 +++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 - 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c index c67089a7ebc1..50ee03bc94b4 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -205,7 +205,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu) A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT); for (i = 3; i <= 5; i++) - if ((SZ_16K << i) == adreno_gpu->gmem) + if ((SZ_16K << i) == adreno_gpu->info->gmem) break; gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i); diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index bbb1bf33f98e..2cb519a4f173 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -749,7 +749,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO, - 0x00100000 + adreno_gpu->gmem - 1); + 0x00100000 + adreno_gpu->info->gmem - 1); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000); if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) || diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index b3ada1e7b598..edbade75020f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1270,7 +1270,7 @@ static int hw_init(struct msm_gpu *gpu) gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, 0x00100000); gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX, - 0x00100000 + adreno_gpu->gmem - 1); + 0x00100000 + adreno_gpu->info->gmem - 1); } gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index e3cd9ff6ff1d..ef98d51d237f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -320,7 +320,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, *value = adreno_gpu->info->revn; return 0; case MSM_PARAM_GMEM_SIZE: - *value = adreno_gpu->gmem; + *value = adreno_gpu->info->gmem; return 0; case MSM_PARAM_GMEM_BASE: *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0; @@ -1041,14 +1041,16 @@ int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, return PTR_ERR(ocmem); } - ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem); + ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->info->gmem); if (IS_ERR(ocmem_hdl)) return PTR_ERR(ocmem_hdl); adreno_ocmem->ocmem = ocmem; adreno_ocmem->base = ocmem_hdl->addr; adreno_ocmem->hdl = ocmem_hdl; - adreno_gpu->gmem = ocmem_hdl->len; + + if (WARN_ON(ocmem_hdl->len != adreno_gpu->info->gmem)) + return -ENOMEM; return 0; } @@ -1097,7 +1099,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); - adreno_gpu->gmem = adreno_gpu->info->gmem; adreno_gpu->revn = adreno_gpu->info->revn; adreno_gpu->rev = *rev; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index ac2350ebe035..4a22aa879445 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -77,7 +77,6 @@ struct adreno_gpu { struct msm_gpu base; struct adreno_rev rev; const struct adreno_info *info; - uint32_t gmem; /* actual gmem size */ uint32_t revn; /* numeric revision name */ uint16_t speedbin; const struct adreno_gpu_funcs *funcs; From f4f1c707817db92b7c9394ecd46a1fafe1943535 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 27 Jul 2023 14:20:08 -0700 Subject: [PATCH 087/118] drm/msm/adreno: Remove redundant revn param This just duplicates what is in adreno_info, and can cause confusion if used before it is set. Signed-off-by: Rob Clark Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549761/ --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 -- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 - drivers/gpu/drm/msm/adreno/adreno_gpu.h | 22 +++++++++------------- 3 files changed, 9 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index edbade75020f..5ba8b5aca502 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2484,8 +2484,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(-EINVAL); /* Assign these early so that we can use the is_aXYZ helpers */ - /* Numeric revision IDs (e.g. 630) */ - adreno_gpu->revn = info->revn; /* New-style ADRENO_REV()-only */ adreno_gpu->rev = info->rev; /* Quirk data */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index ef98d51d237f..f4d45534dd7f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1099,7 +1099,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); - adreno_gpu->revn = adreno_gpu->info->revn; adreno_gpu->rev = *rev; if (adreno_read_speedbin(dev, &speedbin) || !speedbin) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 4a22aa879445..922f3dec2211 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -77,7 +77,6 @@ struct adreno_gpu { struct msm_gpu base; struct adreno_rev rev; const struct adreno_info *info; - uint32_t revn; /* numeric revision name */ uint16_t speedbin; const struct adreno_gpu_funcs *funcs; @@ -147,10 +146,9 @@ bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn) { - /* revn can be zero, but if not is set at same time as info */ - WARN_ON_ONCE(!gpu->info); - - return gpu->revn == revn; + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->revn == revn; } static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu) @@ -160,18 +158,16 @@ static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu) static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu) { - /* revn can be zero, but if not is set at same time as info */ - WARN_ON_ONCE(!gpu->info); - - return (gpu->revn < 300); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return (gpu->info->revn < 300); } static inline bool adreno_is_a20x(const struct adreno_gpu *gpu) { - /* revn can be zero, but if not is set at same time as info */ - WARN_ON_ONCE(!gpu->info); - - return (gpu->revn < 210); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return (gpu->info->revn < 210); } static inline bool adreno_is_a225(const struct adreno_gpu *gpu) From 459f9e26e7d49f80f587d7592ccb78e00ab458e4 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 27 Jul 2023 14:20:09 -0700 Subject: [PATCH 088/118] drm/msm/adreno: Use quirk identify hw_apriv Rather than just open coding a list of gpu-id matches. Signed-off-by: Rob Clark Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549764/ --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +-- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 5ba8b5aca502..6f8c4381fa4a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2489,8 +2489,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) /* Quirk data */ adreno_gpu->info = info; - if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu)) - adreno_gpu->base.hw_apriv = true; + adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); a6xx_llc_slices_init(pdev, a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 326912284a95..f469f951a907 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -302,6 +302,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", .hwcg = a650_hwcg, @@ -315,6 +316,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", .hwcg = a660_hwcg, @@ -327,6 +329,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .hwcg = a660_hwcg, .address_space_size = SZ_16G, @@ -350,6 +353,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_4M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", .hwcg = a690_hwcg, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 922f3dec2211..14d7f75da77a 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -32,6 +32,7 @@ enum { #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) +#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) struct adreno_rev { uint8_t core; From 155668ef412fc82ff3172666831d95770141cdd6 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 27 Jul 2023 14:20:10 -0700 Subject: [PATCH 089/118] drm/msm/adreno: Use quirk to identify cached-coherent support It is better to explicitly list it. With the move to opaque chip-id's for future devices, we should avoid trying to infer things like generation from the numerical value. Signed-off-by: Rob Clark Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549765/ --- drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +++++++++++++++------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index f469f951a907..3c531da417b9 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -256,6 +256,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), @@ -266,6 +267,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .hwcg = a615_hwcg, @@ -278,6 +280,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a630_zap.mdt", .hwcg = a630_hwcg, @@ -290,6 +293,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg, @@ -302,7 +306,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", .hwcg = a650_hwcg, @@ -316,7 +321,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", .hwcg = a660_hwcg, @@ -329,7 +335,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .hwcg = a660_hwcg, .address_space_size = SZ_16G, @@ -342,6 +349,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_2M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg, @@ -353,7 +361,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_4M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", .hwcg = a690_hwcg, @@ -565,9 +574,9 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) if (ret) return ret; - if (config.rev.core >= 6) - if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu))) - priv->has_cached_coherent = true; + priv->has_cached_coherent = + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) && + !adreno_has_gmu_wrapper(to_adreno_gpu(gpu)); return 0; } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 14d7f75da77a..059e35d76e2e 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -33,6 +33,7 @@ enum { #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) +#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) struct adreno_rev { uint8_t core; From f30a648d87485174700cd91e54fada5df5691a77 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 27 Jul 2023 14:20:11 -0700 Subject: [PATCH 090/118] drm/msm/adreno: Allow SoC specific gpu device table entries There are cases where there are differences due to SoC integration. Such as cache-coherency support, and (in the next patch) e-fuse to speedbin mappings. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549767/ --- drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 3c531da417b9..e62bc895a31f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, + }, { + .machine = "qcom,sm4350", + .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + }, { + .machine = "qcom,sm6375", + .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), .revn = 619, @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev) /* identify gpu: */ for (i = 0; i < ARRAY_SIZE(gpulist); i++) { const struct adreno_info *info = &gpulist[i]; + if (info->machine && !of_machine_is_compatible(info->machine)) + continue; if (adreno_cmp_rev(info->rev, rev)) return info; } @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) config.rev.minor, config.rev.patchid); priv->is_a2xx = config.rev.core == 2; + priv->has_cached_coherent = + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); gpu = info->init(drm); if (IS_ERR(gpu)) { @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) if (ret) return ret; - priv->has_cached_coherent = - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) && - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu)); - return 0; } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 059e35d76e2e..2abc43b6b5a9 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; struct adreno_info { + const char *machine; struct adreno_rev rev; uint32_t revn; const char *fw[ADRENO_FW_MAX]; From c928a05e44155c860253eb97afe23770171989fe Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 27 Jul 2023 14:20:12 -0700 Subject: [PATCH 091/118] drm/msm/adreno: Move speedbin mapping to device table This simplifies the code. v2: Use a table of structs instead of flat uint32_t[] Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549769/ --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 173 ++------------------- drivers/gpu/drm/msm/adreno/adreno_device.c | 51 ++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 30 ++++ 3 files changed, 98 insertions(+), 156 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 6f8c4381fa4a..a81a6459c656 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2204,159 +2204,19 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return progress; } -static u32 a610_get_speed_bin(u32 fuse) +static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) { - /* - * There are (at least) three SoCs implementing A610: SM6125 (trinket), - * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning, - * as only a single SKU exists and we don't support khaje upstream yet. - * Hence, this matching table is only valid for bengal and can be easily - * expanded if need be. - */ - - if (fuse == 0) - return 0; - else if (fuse == 206) - return 1; - else if (fuse == 200) - return 2; - else if (fuse == 157) - return 3; - else if (fuse == 127) - return 4; - - return UINT_MAX; -} - -static u32 a618_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 169) - return 1; - else if (fuse == 174) - return 2; - - return UINT_MAX; -} - -static u32 a619_holi_get_speed_bin(u32 fuse) -{ - /* - * There are (at least) two SoCs implementing A619_holi: SM4350 (holi) - * and SM6375 (blair). Limit the fuse matching to the corresponding - * SoC to prevent bogus frequency setting (as improbable as it may be, - * given unexpected fuse values are.. unexpected! But still possible.) - */ - - if (fuse == 0) - return 0; - - if (of_machine_is_compatible("qcom,sm4350")) { - if (fuse == 138) - return 1; - else if (fuse == 92) - return 2; - } else if (of_machine_is_compatible("qcom,sm6375")) { - if (fuse == 190) - return 1; - else if (fuse == 177) - return 2; - } else - pr_warn("Unknown SoC implementing A619_holi!\n"); - - return UINT_MAX; -} - -static u32 a619_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 120) - return 4; - else if (fuse == 138) - return 3; - else if (fuse == 169) - return 2; - else if (fuse == 180) - return 1; - - return UINT_MAX; -} - -static u32 a640_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 1) - return 1; - - return UINT_MAX; -} - -static u32 a650_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 1) - return 1; - /* Yep, 2 and 3 are swapped! :/ */ - else if (fuse == 2) - return 3; - else if (fuse == 3) - return 2; - - return UINT_MAX; -} - -static u32 adreno_7c3_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 117) - return 0; - else if (fuse == 190) - return 1; - - return UINT_MAX; -} - -static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u32 fuse) -{ - u32 val = UINT_MAX; - - if (adreno_is_a610(adreno_gpu)) - val = a610_get_speed_bin(fuse); - - if (adreno_is_a618(adreno_gpu)) - val = a618_get_speed_bin(fuse); - - else if (adreno_is_a619_holi(adreno_gpu)) - val = a619_holi_get_speed_bin(fuse); - - else if (adreno_is_a619(adreno_gpu)) - val = a619_get_speed_bin(fuse); - - else if (adreno_is_7c3(adreno_gpu)) - val = adreno_7c3_get_speed_bin(fuse); - - else if (adreno_is_a640(adreno_gpu)) - val = a640_get_speed_bin(fuse); - - else if (adreno_is_a650(adreno_gpu)) - val = a650_get_speed_bin(fuse); - - if (val == UINT_MAX) { - DRM_DEV_ERROR(dev, - "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", - fuse); + if (!info->speedbins) return UINT_MAX; - } - return (1 << val); + for (int i = 0; info->speedbins[i].fuse != SHRT_MAX; i++) + if (info->speedbins[i].fuse == fuse) + return BIT(info->speedbins[i].speedbin); + + return UINT_MAX; } -static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_gpu) +static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) { u32 supp_hw; u32 speedbin; @@ -2375,7 +2235,14 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_g return ret; } - supp_hw = fuse_to_supp_hw(dev, adreno_gpu, speedbin); + supp_hw = fuse_to_supp_hw(info, speedbin); + + if (supp_hw == UINT_MAX) { + DRM_DEV_ERROR(dev, + "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", + speedbin); + return UINT_MAX; + } ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); if (ret) @@ -2483,17 +2350,11 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) if (!info) return ERR_PTR(-EINVAL); - /* Assign these early so that we can use the is_aXYZ helpers */ - /* New-style ADRENO_REV()-only */ - adreno_gpu->rev = info->rev; - /* Quirk data */ - adreno_gpu->info = info; - adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); a6xx_llc_slices_init(pdev, a6xx_gpu); - ret = a6xx_set_supported_hw(&pdev->dev, adreno_gpu); + ret = a6xx_set_supported_hw(&pdev->dev, info); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index e62bc895a31f..325b25dc8bfd 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -247,6 +247,20 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a610_zap.mdt", .hwcg = a612_hwcg, + /* + * There are (at least) three SoCs implementing A610: SM6125 + * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does + * not have speedbinning, as only a single SKU exists and we + * don't support khaje upstream yet. Hence, this matching + * table is only valid for bengal. + */ + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 206, 1 }, + { 200, 2 }, + { 157, 3 }, + { 127, 4 }, + ), }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), .revn = 618, @@ -258,6 +272,11 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 169, 1 }, + { 174, 2 }, + ), }, { .machine = "qcom,sm4350", .rev = ADRENO_REV(6, 1, 9, ANY_ID), @@ -271,6 +290,11 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 138, 1 }, + { 92, 2 }, + ), }, { .machine = "qcom,sm6375", .rev = ADRENO_REV(6, 1, 9, ANY_ID), @@ -284,6 +308,11 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 190, 1 }, + { 177, 2 }, + ), }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), .revn = 619, @@ -297,6 +326,13 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 120, 4 }, + { 138, 3 }, + { 169, 2 }, + { 180, 1 }, + ), }, { .rev = ADRENO_REV(6, 3, 0, ANY_ID), .revn = 630, @@ -323,6 +359,10 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + ), }, { .rev = ADRENO_REV(6, 5, 0, ANY_ID), .revn = 650, @@ -338,6 +378,12 @@ static const struct adreno_info gpulist[] = { .zapfw = "a650_zap.mdt", .hwcg = a650_hwcg, .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 1, 1 }, + { 2, 3 }, /* Yep, 2 and 3 are swapped! :/ */ + { 3, 2 }, + ), }, { .rev = ADRENO_REV(6, 6, 0, ANY_ID), .revn = 660, @@ -366,6 +412,11 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .hwcg = a660_hwcg, .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 117, 0 }, + { 190, 1 }, + ), }, { .rev = ADRENO_REV(6, 8, 0, ANY_ID), .revn = 680, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 2abc43b6b5a9..0460e61b7bce 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -60,6 +60,11 @@ struct adreno_reglist { extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[]; extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; +struct adreno_speedbin { + uint16_t fuse; + uint16_t speedbin; +}; + struct adreno_info { const char *machine; struct adreno_rev rev; @@ -72,8 +77,33 @@ struct adreno_info { u32 inactive_period; const struct adreno_reglist *hwcg; u64 address_space_size; + /** + * @speedbins: Optional table of fuse to speedbin mappings + * + * Consists of pairs of fuse, index mappings, terminated with + * {SHRT_MAX, 0} sentinal. + */ + struct adreno_speedbin *speedbins; }; +/* + * Helper to build a speedbin table, ie. the table: + * fuse | speedbin + * -----+--------- + * 0 | 0 + * 169 | 1 + * 174 | 2 + * + * would be declared as: + * + * .speedbins = ADRENO_SPEEDBINS( + * { 0, 0 }, + * { 169, 1 }, + * { 174, 2 }, + * ), + */ +#define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} } + const struct adreno_info *adreno_info(struct adreno_rev rev); struct adreno_gpu { From 75a5227c0d1d2a8c20cf4b2d0f2e030d43dc13eb Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 27 Jul 2023 14:20:13 -0700 Subject: [PATCH 092/118] drm/msm/adreno: Bring the a630 family together All of these are derivatives of a630. Signed-off-by: Rob Clark Reviewed-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/549770/ --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 5deb79924897..f1bb20574018 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1617,7 +1617,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) SZ_256K - SZ_16K, 0x44000, "dcache"); if (ret) goto err_memory; - } else if (adreno_is_a630(adreno_gpu) || adreno_is_a615_family(adreno_gpu)) { + } else if (adreno_is_a630_family(adreno_gpu)) { /* HFI v1, has sptprac */ gmu->legacy = true; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 0460e61b7bce..9584f552e1c5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -339,12 +339,13 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu) { /* The order of args is important here to handle ANY_ID correctly */ return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev); -}; +} -/* check for a615, a616, a618, a619 or any derivatives */ -static inline int adreno_is_a615_family(const struct adreno_gpu *gpu) +/* check for a615, a616, a618, a619 or any a630 derivatives */ +static inline int adreno_is_a630_family(const struct adreno_gpu *gpu) { - return adreno_is_revn(gpu, 615) || + return adreno_is_revn(gpu, 630) || + adreno_is_revn(gpu, 615) || adreno_is_revn(gpu, 616) || adreno_is_revn(gpu, 618) || adreno_is_revn(gpu, 619); From 67133dc086963a01b0446665b148aa6d39085db9 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 27 Jul 2023 14:20:14 -0700 Subject: [PATCH 093/118] drm/msm/adreno: Add adreno family Sometimes it is useful to know the sub-generation (or "family"). And in any case, this helps us get away from infering the generation from the numerical chip-id. v2: Fix is_a2xx() typo Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549773/ --- drivers/gpu/drm/msm/adreno/adreno_device.c | 31 ++++++++++++++- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 +++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 46 ++++++++++++++++------ 3 files changed, 70 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 325b25dc8bfd..e014d85a60cc 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -23,6 +23,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); static const struct adreno_info gpulist[] = { { .rev = ADRENO_REV(2, 0, 0, 0), + .family = ADRENO_2XX_GEN1, .revn = 200, .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", @@ -33,6 +34,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { /* a200 on i.mx51 has only 128kib gmem */ .rev = ADRENO_REV(2, 0, 0, 1), + .family = ADRENO_2XX_GEN1, .revn = 201, .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", @@ -43,6 +45,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { .rev = ADRENO_REV(2, 2, 0, ANY_ID), + .family = ADRENO_2XX_GEN2, .revn = 220, .fw = { [ADRENO_FW_PM4] = "leia_pm4_470.fw", @@ -53,6 +56,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { .rev = ADRENO_REV(3, 0, 5, ANY_ID), + .family = ADRENO_3XX, .revn = 305, .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", @@ -63,6 +67,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 0, 6, 0), + .family = ADRENO_3XX, .revn = 307, /* because a305c is revn==306 */ .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", @@ -73,6 +78,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), + .family = ADRENO_3XX, .revn = 320, .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", @@ -83,6 +89,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 3, 0, ANY_ID), + .family = ADRENO_3XX, .revn = 330, .fw = { [ADRENO_FW_PM4] = "a330_pm4.fw", @@ -93,6 +100,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(4, 0, 5, ANY_ID), + .family = ADRENO_4XX, .revn = 405, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", @@ -103,6 +111,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(4, 2, 0, ANY_ID), + .family = ADRENO_4XX, .revn = 420, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", @@ -113,6 +122,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(4, 3, 0, ANY_ID), + .family = ADRENO_4XX, .revn = 430, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", @@ -123,6 +133,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(5, 0, 6, ANY_ID), + .family = ADRENO_5XX, .revn = 506, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -140,6 +151,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a506_zap.mdt", }, { .rev = ADRENO_REV(5, 0, 8, ANY_ID), + .family = ADRENO_5XX, .revn = 508, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -156,6 +168,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a508_zap.mdt", }, { .rev = ADRENO_REV(5, 0, 9, ANY_ID), + .family = ADRENO_5XX, .revn = 509, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -173,6 +186,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a512_zap.mdt", }, { .rev = ADRENO_REV(5, 1, 0, ANY_ID), + .family = ADRENO_5XX, .revn = 510, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -187,6 +201,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, }, { .rev = ADRENO_REV(5, 1, 2, ANY_ID), + .family = ADRENO_5XX, .revn = 512, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -203,6 +218,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a512_zap.mdt", }, { .rev = ADRENO_REV(5, 3, 0, 2), + .family = ADRENO_5XX, .revn = 530, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -221,6 +237,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a530_zap.mdt", }, { .rev = ADRENO_REV(5, 4, 0, ANY_ID), + .family = ADRENO_5XX, .revn = 540, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -238,6 +255,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a540_zap.mdt", }, { .rev = ADRENO_REV(6, 1, 0, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 610, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -263,6 +281,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 618, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -280,6 +299,7 @@ static const struct adreno_info gpulist[] = { }, { .machine = "qcom,sm4350", .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -298,6 +318,7 @@ static const struct adreno_info gpulist[] = { }, { .machine = "qcom,sm6375", .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -315,6 +336,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -335,6 +357,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 3, 0, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 630, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -348,6 +371,7 @@ static const struct adreno_info gpulist[] = { .hwcg = a630_hwcg, }, { .rev = ADRENO_REV(6, 4, 0, ANY_ID), + .family = ADRENO_6XX_GEN2, .revn = 640, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -365,6 +389,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 5, 0, ANY_ID), + .family = ADRENO_6XX_GEN3, .revn = 650, .fw = { [ADRENO_FW_SQE] = "a650_sqe.fw", @@ -386,6 +411,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 6, 0, ANY_ID), + .family = ADRENO_6XX_GEN4, .revn = 660, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", @@ -401,6 +427,7 @@ static const struct adreno_info gpulist[] = { .address_space_size = SZ_16G, }, { .rev = ADRENO_REV(6, 3, 5, ANY_ID), + .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a660_gmu.bin", @@ -419,6 +446,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 8, 0, ANY_ID), + .family = ADRENO_6XX_GEN2, .revn = 680, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -432,6 +460,7 @@ static const struct adreno_info gpulist[] = { .hwcg = a640_hwcg, }, { .rev = ADRENO_REV(6, 9, 0, ANY_ID), + .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a690_gmu.bin", @@ -641,7 +670,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, config.rev.minor, config.rev.patchid); - priv->is_a2xx = config.rev.core == 2; + priv->is_a2xx = info->family < ADRENO_3XX; priv->has_cached_coherent = !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index f4d45534dd7f..1951036b2308 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1080,8 +1080,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, u32 speedbin; int ret; + adreno_gpu->funcs = funcs; + adreno_gpu->info = adreno_info(config->rev); + adreno_gpu->rev = *rev; + /* Only handle the core clock when GMU is not in use (or is absent). */ - if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) { + if (adreno_has_gmu_wrapper(adreno_gpu) || + adreno_gpu->info->family < ADRENO_6XX_GEN1) { /* * This can only be done before devm_pm_opp_of_add_table(), or * dev_pm_opp_set_config() will WARN_ON() @@ -1097,10 +1102,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - adreno_gpu->funcs = funcs; - adreno_gpu->info = adreno_info(config->rev); - adreno_gpu->rev = *rev; - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) speedbin = 0xffff; adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 9584f552e1c5..502fe860cc91 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -29,6 +29,25 @@ enum { ADRENO_FW_MAX, }; +/** + * @enum adreno_family: identify generation and possibly sub-generation + * + * In some cases there are distinct sub-generations within a major revision + * so it helps to be able to group the GPU devices by generation and if + * necessary sub-generation. + */ +enum adreno_family { + ADRENO_2XX_GEN1, /* a20x */ + ADRENO_2XX_GEN2, /* a22x */ + ADRENO_3XX, + ADRENO_4XX, + ADRENO_5XX, + ADRENO_6XX_GEN1, /* a630 family */ + ADRENO_6XX_GEN2, /* a640 family */ + ADRENO_6XX_GEN3, /* a650 family */ + ADRENO_6XX_GEN4, /* a660 family */ +}; + #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) @@ -68,6 +87,7 @@ struct adreno_speedbin { struct adreno_info { const char *machine; struct adreno_rev rev; + enum adreno_family family; uint32_t revn; const char *fw[ADRENO_FW_MAX]; uint32_t gmem; @@ -193,14 +213,14 @@ static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return (gpu->info->revn < 300); + return gpu->info->family <= ADRENO_2XX_GEN2; } static inline bool adreno_is_a20x(const struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return (gpu->info->revn < 210); + return gpu->info->family == ADRENO_2XX_GEN1; } static inline bool adreno_is_a225(const struct adreno_gpu *gpu) @@ -344,29 +364,31 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu) /* check for a615, a616, a618, a619 or any a630 derivatives */ static inline int adreno_is_a630_family(const struct adreno_gpu *gpu) { - return adreno_is_revn(gpu, 630) || - adreno_is_revn(gpu, 615) || - adreno_is_revn(gpu, 616) || - adreno_is_revn(gpu, 618) || - adreno_is_revn(gpu, 619); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family == ADRENO_6XX_GEN1; } static inline int adreno_is_a660_family(const struct adreno_gpu *gpu) { - return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family == ADRENO_6XX_GEN4; } /* check for a650, a660, or any derivatives */ static inline int adreno_is_a650_family(const struct adreno_gpu *gpu) { - return adreno_is_revn(gpu, 650) || - adreno_is_revn(gpu, 620) || - adreno_is_a660_family(gpu); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family >= ADRENO_6XX_GEN3; } static inline int adreno_is_a640_family(const struct adreno_gpu *gpu) { - return adreno_is_a640(gpu) || adreno_is_a680(gpu); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family == ADRENO_6XX_GEN2; } u64 adreno_private_address_space_size(struct msm_gpu *gpu); From 8825f59692674a46b9a1f4afdeb06fb015cd05e0 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 27 Jul 2023 14:20:15 -0700 Subject: [PATCH 094/118] drm/msm/adreno: Add helper for formating chip-id This is used in a few places, including one that is parsed by userspace tools. So let's standardize it a bit better. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549774/ --- drivers/gpu/drm/msm/adreno/adreno_device.c | 8 +++----- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 19 ++++++++----------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++++++ 3 files changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index e014d85a60cc..7448f299b77c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -661,14 +661,12 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) info = adreno_info(config.rev); if (!info) { - dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n", - config.rev.core, config.rev.major, - config.rev.minor, config.rev.patchid); + dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n", + ADRENO_CHIPID_ARGS(config.rev)); return -ENXIO; } - DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, - config.rev.minor, config.rev.patchid); + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev)); priv->is_a2xx = info->family < ADRENO_3XX; priv->has_cached_coherent = diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 1951036b2308..a775b4d82735 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -847,10 +847,9 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, if (IS_ERR_OR_NULL(state)) return; - drm_printf(p, "revision: %d (%d.%d.%d.%d)\n", - adreno_gpu->info->revn, adreno_gpu->rev.core, - adreno_gpu->rev.major, adreno_gpu->rev.minor, - adreno_gpu->rev.patchid); + drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n", + adreno_gpu->info->revn, + ADRENO_CHIPID_ARGS(adreno_gpu->rev)); /* * If this is state collected due to iova fault, so fault related info * @@ -921,10 +920,9 @@ void adreno_dump_info(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); int i; - printk("revision: %d (%d.%d.%d.%d)\n", - adreno_gpu->info->revn, adreno_gpu->rev.core, - adreno_gpu->rev.major, adreno_gpu->rev.minor, - adreno_gpu->rev.patchid); + printk("revision: %u (%"ADRENO_CHIPID_FMT")\n", + adreno_gpu->info->revn, + ADRENO_CHIPID_ARGS(adreno_gpu->rev)); for (i = 0; i < gpu->nr_rings; i++) { struct msm_ringbuffer *ring = gpu->rb[i]; @@ -1106,9 +1104,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, speedbin = 0xffff; adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); - gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d", - rev->core, rev->major, rev->minor, - rev->patchid); + gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, + ADRENO_CHIPID_ARGS(config->rev)); if (!gpu_name) return -ENOMEM; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 502fe860cc91..65162186ce9d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -66,6 +66,12 @@ struct adreno_rev { #define ADRENO_REV(core, major, minor, patchid) \ ((struct adreno_rev){ core, major, minor, patchid }) +/* Helper for formating the chip_id in the way that userspace tools like + * crashdec expect. + */ +#define ADRENO_CHIPID_FMT "u.%u.%u.%u" +#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid + struct adreno_gpu_funcs { struct msm_gpu_funcs base; int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value); From 47bd37f948a40bea515c6cb2f4c6fcc92162c822 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 27 Jul 2023 14:20:16 -0700 Subject: [PATCH 095/118] drm/msm/adreno: Move adreno info to config Let's just stash it in adreno_platform_config rather than looking it up in N different places. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549777/ --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 +++------------ drivers/gpu/drm/msm/adreno/adreno_device.c | 5 +++-- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +-- 4 files changed, 8 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index a81a6459c656..9be3260c8033 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2316,7 +2316,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) struct msm_drm_private *priv = dev->dev_private; struct platform_device *pdev = priv->gpu_pdev; struct adreno_platform_config *config = pdev->dev.platform_data; - const struct adreno_info *info; struct device_node *node; struct a6xx_gpu *a6xx_gpu; struct adreno_gpu *adreno_gpu; @@ -2341,20 +2340,12 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) adreno_gpu->gmu_is_wrapper = of_device_is_compatible(node, "qcom,adreno-gmu-wrapper"); - /* - * We need to know the platform type before calling into adreno_gpu_init - * so that the hw_apriv flag can be correctly set. Snoop into the info - * and grab the revision number - */ - info = adreno_info(config->rev); - if (!info) - return ERR_PTR(-EINVAL); - - adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); + adreno_gpu->base.hw_apriv = + !!(config->info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); a6xx_llc_slices_init(pdev, a6xx_gpu); - ret = a6xx_set_supported_hw(&pdev->dev, info); + ret = a6xx_set_supported_hw(&pdev->dev, config->info); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 7448f299b77c..332cb804a45d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -508,7 +508,7 @@ bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2) _rev_match(rev1.patchid, rev2.patchid); } -const struct adreno_info *adreno_info(struct adreno_rev rev) +static const struct adreno_info *adreno_info(struct adreno_rev rev) { int i; @@ -659,13 +659,14 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) priv->gpu_pdev = to_platform_device(dev); info = adreno_info(config.rev); - if (!info) { dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n", ADRENO_CHIPID_ARGS(config.rev)); return -ENXIO; } + config.info = info; + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev)); priv->is_a2xx = info->family < ADRENO_3XX; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index a775b4d82735..865ff4c1eaf6 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1079,7 +1079,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, int ret; adreno_gpu->funcs = funcs; - adreno_gpu->info = adreno_info(config->rev); + adreno_gpu->info = config->info; adreno_gpu->rev = *rev; /* Only handle the core clock when GMU is not in use (or is absent). */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 65162186ce9d..8776db16c243 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -130,8 +130,6 @@ struct adreno_info { */ #define ADRENO_SPEEDBINS(tbl...) (struct adreno_speedbin[]) { tbl {SHRT_MAX, 0} } -const struct adreno_info *adreno_info(struct adreno_rev rev); - struct adreno_gpu { struct msm_gpu base; struct adreno_rev rev; @@ -185,6 +183,7 @@ struct adreno_ocmem { /* platform config data (ie. from DT, or pdata) */ struct adreno_platform_config { struct adreno_rev rev; + const struct adreno_info *info; }; #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) From b42ab8545eb3529ff80534148e2ddb5c998d14c3 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 27 Jul 2023 14:20:17 -0700 Subject: [PATCH 096/118] dt-bindings: drm/msm/gpu: Extend bindings for chip-id Upcoming GPUs use an opaque chip-id for identifying the GPU. Signed-off-by: Rob Clark Patchwork: https://patchwork.freedesktop.org/patch/549778/ --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 58ca8912a8c3..56b9b247e8c2 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -13,6 +13,12 @@ maintainers: properties: compatible: oneOf: + - description: | + The driver is parsing the compat string for Adreno to + figure out the chip-id. + items: + - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$' + - const: qcom,adreno - description: | The driver is parsing the compat string for Adreno to figure out the gpu-id and patch level. From 90b593ce1c9e979e64f6dd3dccec11ed3654077f Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 27 Jul 2023 14:20:18 -0700 Subject: [PATCH 097/118] drm/msm/adreno: Switch to chip-id for identifying GPU Since the revision becomes an opaque identifier with future GPUs, move away from treating different ranges of bits as having a given meaning. This means that we need to explicitly list different patch revisions in the device table. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/549782/ --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 14 ++- drivers/gpu/drm/msm/adreno/adreno_device.c | 137 +++++++++++---------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 14 +-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 49 ++++---- 7 files changed, 115 insertions(+), 105 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 715436cb3996..8b4cdf95f445 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -145,7 +145,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu) gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000); /* Early A430's have a timing issue with SP/TP power collapse; disabling HW clock gating prevents it. */ - if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2) + if (adreno_is_a430(adreno_gpu) && adreno_patchid(adreno_gpu) < 2) gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0); else gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA); diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 2cb519a4f173..041d1cd8ed99 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1770,7 +1770,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) nr_rings = 4; - if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev)) + if (config->info->revn == 510) nr_rings = 1; ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings); diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c index 0e63a1429189..7705f8010484 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c @@ -179,7 +179,7 @@ static void a540_lm_setup(struct msm_gpu *gpu) /* The battery current limiter isn't enabled for A540 */ config = AGC_LM_CONFIG_BCL_DISABLED; - config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT; + config |= adreno_patchid(adreno_gpu) << AGC_LM_CONFIG_GPU_VERSION_SHIFT; /* For now disable GPMU side throttling */ config |= AGC_LM_CONFIG_THROTTLE_DISABLE; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index f1bb20574018..bf7f855f4a34 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -790,10 +790,16 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, (1 << 31) | (0xa << 18) | (0xa0)); - chipid = adreno_gpu->rev.core << 24; - chipid |= adreno_gpu->rev.major << 16; - chipid |= adreno_gpu->rev.minor << 12; - chipid |= adreno_gpu->rev.patchid << 8; + /* + * Note that the GMU has a slightly different layout for + * chip_id, for whatever reason, so a bit of massaging + * is needed. The upper 16b are the same, but minor and + * patchid are packed in four bits each with the lower + * 8b unused: + */ + chipid = adreno_gpu->chip_id & 0xffff0000; + chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */ + chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */ gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 332cb804a45d..9cda403ebc7b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -22,7 +22,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); static const struct adreno_info gpulist[] = { { - .rev = ADRENO_REV(2, 0, 0, 0), + .chip_ids = ADRENO_CHIP_IDS(0x02000000), .family = ADRENO_2XX_GEN1, .revn = 200, .fw = { @@ -33,7 +33,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a2xx_gpu_init, }, { /* a200 on i.mx51 has only 128kib gmem */ - .rev = ADRENO_REV(2, 0, 0, 1), + .chip_ids = ADRENO_CHIP_IDS(0x02000001), .family = ADRENO_2XX_GEN1, .revn = 201, .fw = { @@ -44,7 +44,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a2xx_gpu_init, }, { - .rev = ADRENO_REV(2, 2, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x02020000), .family = ADRENO_2XX_GEN2, .revn = 220, .fw = { @@ -55,7 +55,10 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a2xx_gpu_init, }, { - .rev = ADRENO_REV(3, 0, 5, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS( + 0x03000512, + 0x03000520 + ), .family = ADRENO_3XX, .revn = 305, .fw = { @@ -66,7 +69,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, }, { - .rev = ADRENO_REV(3, 0, 6, 0), + .chip_ids = ADRENO_CHIP_IDS(0x03000600), .family = ADRENO_3XX, .revn = 307, /* because a305c is revn==306 */ .fw = { @@ -77,7 +80,11 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, }, { - .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS( + 0x03020000, + 0x03020001, + 0x03020002 + ), .family = ADRENO_3XX, .revn = 320, .fw = { @@ -88,7 +95,11 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, }, { - .rev = ADRENO_REV(3, 3, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS( + 0x03030000, + 0x03030001, + 0x03030002 + ), .family = ADRENO_3XX, .revn = 330, .fw = { @@ -99,7 +110,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, }, { - .rev = ADRENO_REV(4, 0, 5, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x04000500), .family = ADRENO_4XX, .revn = 405, .fw = { @@ -110,7 +121,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a4xx_gpu_init, }, { - .rev = ADRENO_REV(4, 2, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x04020000), .family = ADRENO_4XX, .revn = 420, .fw = { @@ -121,7 +132,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a4xx_gpu_init, }, { - .rev = ADRENO_REV(4, 3, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x04030002), .family = ADRENO_4XX, .revn = 430, .fw = { @@ -132,7 +143,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a4xx_gpu_init, }, { - .rev = ADRENO_REV(5, 0, 6, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05000600), .family = ADRENO_5XX, .revn = 506, .fw = { @@ -150,7 +161,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a506_zap.mdt", }, { - .rev = ADRENO_REV(5, 0, 8, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05000800), .family = ADRENO_5XX, .revn = 508, .fw = { @@ -167,7 +178,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a508_zap.mdt", }, { - .rev = ADRENO_REV(5, 0, 9, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05000900), .family = ADRENO_5XX, .revn = 509, .fw = { @@ -185,7 +196,7 @@ static const struct adreno_info gpulist[] = { /* Adreno 509 uses the same ZAP as 512 */ .zapfw = "a512_zap.mdt", }, { - .rev = ADRENO_REV(5, 1, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05010000), .family = ADRENO_5XX, .revn = 510, .fw = { @@ -200,7 +211,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = 250, .init = a5xx_gpu_init, }, { - .rev = ADRENO_REV(5, 1, 2, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05010200), .family = ADRENO_5XX, .revn = 512, .fw = { @@ -217,7 +228,10 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a512_zap.mdt", }, { - .rev = ADRENO_REV(5, 3, 0, 2), + .chip_ids = ADRENO_CHIP_IDS( + 0x05030002, + 0x05030004 + ), .family = ADRENO_5XX, .revn = 530, .fw = { @@ -236,7 +250,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a530_zap.mdt", }, { - .rev = ADRENO_REV(5, 4, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05040001), .family = ADRENO_5XX, .revn = 540, .fw = { @@ -254,7 +268,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a540_zap.mdt", }, { - .rev = ADRENO_REV(6, 1, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010000), .family = ADRENO_6XX_GEN1, .revn = 610, .fw = { @@ -280,7 +294,7 @@ static const struct adreno_info gpulist[] = { { 127, 4 }, ), }, { - .rev = ADRENO_REV(6, 1, 8, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010800), .family = ADRENO_6XX_GEN1, .revn = 618, .fw = { @@ -298,7 +312,7 @@ static const struct adreno_info gpulist[] = { ), }, { .machine = "qcom,sm4350", - .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010900), .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { @@ -317,7 +331,7 @@ static const struct adreno_info gpulist[] = { ), }, { .machine = "qcom,sm6375", - .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010900), .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { @@ -335,7 +349,7 @@ static const struct adreno_info gpulist[] = { { 177, 2 }, ), }, { - .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010900), .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { @@ -356,7 +370,10 @@ static const struct adreno_info gpulist[] = { { 180, 1 }, ), }, { - .rev = ADRENO_REV(6, 3, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS( + 0x06030001, + 0x06030002 + ), .family = ADRENO_6XX_GEN1, .revn = 630, .fw = { @@ -370,7 +387,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a630_zap.mdt", .hwcg = a630_hwcg, }, { - .rev = ADRENO_REV(6, 4, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06040001), .family = ADRENO_6XX_GEN2, .revn = 640, .fw = { @@ -388,7 +405,7 @@ static const struct adreno_info gpulist[] = { { 1, 1 }, ), }, { - .rev = ADRENO_REV(6, 5, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06050002), .family = ADRENO_6XX_GEN3, .revn = 650, .fw = { @@ -410,7 +427,7 @@ static const struct adreno_info gpulist[] = { { 3, 2 }, ), }, { - .rev = ADRENO_REV(6, 6, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06060001), .family = ADRENO_6XX_GEN4, .revn = 660, .fw = { @@ -426,7 +443,7 @@ static const struct adreno_info gpulist[] = { .hwcg = a660_hwcg, .address_space_size = SZ_16G, }, { - .rev = ADRENO_REV(6, 3, 5, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06030500), .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", @@ -445,7 +462,7 @@ static const struct adreno_info gpulist[] = { { 190, 1 }, ), }, { - .rev = ADRENO_REV(6, 8, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06080000), .family = ADRENO_6XX_GEN2, .revn = 680, .fw = { @@ -459,7 +476,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg, }, { - .rev = ADRENO_REV(6, 9, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06090000), .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", @@ -494,31 +511,16 @@ MODULE_FIRMWARE("qcom/a630_sqe.fw"); MODULE_FIRMWARE("qcom/a630_gmu.bin"); MODULE_FIRMWARE("qcom/a630_zap.mbn"); -static inline bool _rev_match(uint8_t entry, uint8_t id) +static const struct adreno_info *adreno_info(uint32_t chip_id) { - return (entry == ANY_ID) || (entry == id); -} - -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2) -{ - - return _rev_match(rev1.core, rev2.core) && - _rev_match(rev1.major, rev2.major) && - _rev_match(rev1.minor, rev2.minor) && - _rev_match(rev1.patchid, rev2.patchid); -} - -static const struct adreno_info *adreno_info(struct adreno_rev rev) -{ - int i; - /* identify gpu: */ - for (i = 0; i < ARRAY_SIZE(gpulist); i++) { + for (int i = 0; i < ARRAY_SIZE(gpulist); i++) { const struct adreno_info *info = &gpulist[i]; if (info->machine && !of_machine_is_compatible(info->machine)) continue; - if (adreno_cmp_rev(info->rev, rev)) - return info; + for (int j = 0; info->chip_ids[j]; j++) + if (info->chip_ids[j] == chip_id) + return info; } return NULL; @@ -598,12 +600,11 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev) return NULL; } -static int find_chipid(struct device *dev, struct adreno_rev *rev) +static int find_chipid(struct device *dev, uint32_t *chipid) { struct device_node *node = dev->of_node; const char *compat; int ret; - u32 chipid; /* first search the compat strings for qcom,adreno-XYZ.W: */ ret = of_property_read_string_index(node, "compatible", 0, &compat); @@ -612,32 +613,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev) if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 || sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) { - rev->core = r / 100; + uint32_t core, major, minor; + + core = r / 100; r %= 100; - rev->major = r / 10; + major = r / 10; r %= 10; - rev->minor = r; - rev->patchid = patch; + minor = r; + + *chipid = (core << 24) | + (major << 16) | + (minor << 8) | + patch; return 0; } + + if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1) + return 0; } /* and if that fails, fall back to legacy "qcom,chipid" property: */ - ret = of_property_read_u32(node, "qcom,chipid", &chipid); + ret = of_property_read_u32(node, "qcom,chipid", chipid); if (ret) { DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret); return ret; } - rev->core = (chipid >> 24) & 0xff; - rev->major = (chipid >> 16) & 0xff; - rev->minor = (chipid >> 8) & 0xff; - rev->patchid = (chipid & 0xff); - dev_warn(dev, "Using legacy qcom,chipid binding!\n"); - dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n", - rev->core, rev->major, rev->minor, rev->patchid); return 0; } @@ -651,23 +654,23 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) struct msm_gpu *gpu; int ret; - ret = find_chipid(dev, &config.rev); + ret = find_chipid(dev, &config.chip_id); if (ret) return ret; dev->platform_data = &config; priv->gpu_pdev = to_platform_device(dev); - info = adreno_info(config.rev); + info = adreno_info(config.chip_id); if (!info) { dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n", - ADRENO_CHIPID_ARGS(config.rev)); + ADRENO_CHIPID_ARGS(config.chip_id)); return -ENXIO; } config.info = info; - DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev)); + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id)); priv->is_a2xx = info->family < ADRENO_3XX; priv->has_cached_coherent = diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 865ff4c1eaf6..ba35c2a87021 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -326,10 +326,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0; return 0; case MSM_PARAM_CHIP_ID: - *value = (uint64_t)adreno_gpu->rev.patchid | - ((uint64_t)adreno_gpu->rev.minor << 8) | - ((uint64_t)adreno_gpu->rev.major << 16) | - ((uint64_t)adreno_gpu->rev.core << 24); + *value = adreno_gpu->chip_id; if (!adreno_gpu->info->revn) *value |= ((uint64_t) adreno_gpu->speedbin) << 32; return 0; @@ -849,7 +846,7 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n", adreno_gpu->info->revn, - ADRENO_CHIPID_ARGS(adreno_gpu->rev)); + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id)); /* * If this is state collected due to iova fault, so fault related info * @@ -922,7 +919,7 @@ void adreno_dump_info(struct msm_gpu *gpu) printk("revision: %u (%"ADRENO_CHIPID_FMT")\n", adreno_gpu->info->revn, - ADRENO_CHIPID_ARGS(adreno_gpu->rev)); + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id)); for (i = 0; i < gpu->nr_rings; i++) { struct msm_ringbuffer *ring = gpu->rb[i]; @@ -1073,14 +1070,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_platform_config *config = dev->platform_data; struct msm_gpu_config adreno_gpu_config = { 0 }; struct msm_gpu *gpu = &adreno_gpu->base; - struct adreno_rev *rev = &config->rev; const char *gpu_name; u32 speedbin; int ret; adreno_gpu->funcs = funcs; adreno_gpu->info = config->info; - adreno_gpu->rev = *rev; + adreno_gpu->chip_id = config->chip_id; /* Only handle the core clock when GMU is not in use (or is absent). */ if (adreno_has_gmu_wrapper(adreno_gpu) || @@ -1105,7 +1101,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, - ADRENO_CHIPID_ARGS(config->rev)); + ADRENO_CHIPID_ARGS(config->chip_id)); if (!gpu_name) return -ENOMEM; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 8776db16c243..49f38edf9854 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -54,23 +54,15 @@ enum adreno_family { #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) -struct adreno_rev { - uint8_t core; - uint8_t major; - uint8_t minor; - uint8_t patchid; -}; - -#define ANY_ID 0xff - -#define ADRENO_REV(core, major, minor, patchid) \ - ((struct adreno_rev){ core, major, minor, patchid }) - /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. */ #define ADRENO_CHIPID_FMT "u.%u.%u.%u" -#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid +#define ADRENO_CHIPID_ARGS(_c) \ + (((_c) >> 24) & 0xff), \ + (((_c) >> 16) & 0xff), \ + (((_c) >> 8) & 0xff), \ + ((_c) & 0xff) struct adreno_gpu_funcs { struct msm_gpu_funcs base; @@ -92,7 +84,12 @@ struct adreno_speedbin { struct adreno_info { const char *machine; - struct adreno_rev rev; + /** + * @chipids: Table of matching chip-ids + * + * Terminated with 0 sentinal + */ + uint32_t *chip_ids; enum adreno_family family; uint32_t revn; const char *fw[ADRENO_FW_MAX]; @@ -112,6 +109,8 @@ struct adreno_info { struct adreno_speedbin *speedbins; }; +#define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 } + /* * Helper to build a speedbin table, ie. the table: * fuse | speedbin @@ -132,8 +131,8 @@ struct adreno_info { struct adreno_gpu { struct msm_gpu base; - struct adreno_rev rev; const struct adreno_info *info; + uint32_t chip_id; uint16_t speedbin; const struct adreno_gpu_funcs *funcs; @@ -182,7 +181,7 @@ struct adreno_ocmem { /* platform config data (ie. from DT, or pdata) */ struct adreno_platform_config { - struct adreno_rev rev; + uint32_t chip_id; const struct adreno_info *info; }; @@ -200,7 +199,15 @@ struct adreno_platform_config { __ret; \ }) -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); +static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu) +{ + /* It is probably ok to assume legacy "adreno_rev" format + * for all a6xx devices, but probably best to limit this + * to older things. + */ + WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1); + return gpu->chip_id & 0xff; +} static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn) { @@ -256,7 +263,7 @@ static inline bool adreno_is_a330(const struct adreno_gpu *gpu) static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu) { - return adreno_is_a330(gpu) && (gpu->rev.patchid > 0); + return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0); } static inline int adreno_is_a405(const struct adreno_gpu *gpu) @@ -346,8 +353,7 @@ static inline int adreno_is_a650(const struct adreno_gpu *gpu) static inline int adreno_is_7c3(const struct adreno_gpu *gpu) { - /* The order of args is important here to handle ANY_ID correctly */ - return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev); + return gpu->info->chip_ids[0] == 0x06030500; } static inline int adreno_is_a660(const struct adreno_gpu *gpu) @@ -362,8 +368,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu) static inline int adreno_is_a690(const struct adreno_gpu *gpu) { - /* The order of args is important here to handle ANY_ID correctly */ - return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev); + return gpu->info->chip_ids[0] == 0x06090000; } /* check for a615, a616, a618, a619 or any a630 derivatives */ From 3bf84665675625653ca4df099faa66ad80180f27 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Fri, 30 Jun 2023 09:20:43 -0700 Subject: [PATCH 098/118] drm/msm/a6xx: Fix misleading comment The range is actually len+1. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov Reviewed-by: Akhil P Oommen Patchwork: https://patchwork.freedesktop.org/patch/545099/ --- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index c788b06e72da..ab66d281828c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -39,8 +39,8 @@ struct a6xx_gpu { /* * Given a register and a count, return a value to program into - * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len - * registers starting at _reg. + * REG_CP_PROTECT_REG(n) - this will block both reads and writes for + * _len + 1 registers starting at _reg. */ #define A6XX_PROTECT_NORDWR(_reg, _len) \ ((1 << 31) | \ From b3ba797e45288e1be33418d3181b40fce816198b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:10:36 +0200 Subject: [PATCH 099/118] drm/msm/a6xx: Add some missing header definitions Add a definition of the GMU_AHB_FENCE_STATUS_CLR reg and CP_PROTECT_CNTL bitfields. This may be substituted with a mesa header sync. Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/543330/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx.xml.h | 3 +++ drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 4dc3be6ed45d..1c051535fd4a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -1166,6 +1166,9 @@ static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f +#define A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE 0x00000008 +#define A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN 0x00000002 +#define A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN 0x00000001 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h index 9ab15d91aced..fcd9eb53baf8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h @@ -425,6 +425,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) #define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313 +#define REG_A6XX_GMU_AHB_FENCE_STATUS_CLR 0x00009314 + #define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315 #define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316 From 02a726fc6b2892a5fe4704060594b1af9c2ff953 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:10:37 +0200 Subject: [PATCH 100/118] drm/msm/a6xx: Use descriptive bitfield names for CP_PROTECT_CNTL We have the necessary information, so explain which bit does what. Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/543332/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 9be3260c8033..e0c90393cda5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -930,7 +930,10 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) * protect violation and select the last span to protect from the start * address all the way to the end of the register address space */ - gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3)); + gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, + A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN | + A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN | + A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE); for (i = 0; i < count - 1; i++) gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]); From 29af7605453797b9b58c3369314bd5710f5ea2ba Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:10:38 +0200 Subject: [PATCH 101/118] drm/msm/a6xx: Skip empty protection ranges entries Some specific SKUs leave certain protection range registers empty. Allow for that behavior. Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/543334/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index e0c90393cda5..15006ba63b6a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -935,8 +935,11 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN | A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE); - for (i = 0; i < count - 1; i++) - gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]); + for (i = 0; i < count - 1; i++) { + /* Intentionally skip writing to some registers */ + if (regs[i]) + gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]); + } /* last CP_PROTECT to have "infinite" length on the last entry */ gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]); } From 5e46ad83db102ce36ec4d47a62e115b7ac812311 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:10:39 +0200 Subject: [PATCH 102/118] drm/msm/a6xx: Ensure clean GMU state in a6xx_gmu_fw_start While it's not very well understood, there is some sort of a fault handler implemented in the GMU firmware which triggers when a certain bit is set, resulting in the M3 core not booting up the way we expect it to. Write a magic value to a magic register to hopefully prevent that from happening. Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/543335/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index bf7f855f4a34..452beb90d53c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -790,6 +790,12 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, (1 << 31) | (0xa << 18) | (0xa0)); + /* + * Snapshots toggle the NMI bit which will result in a jump to the NMI + * handler instead of __main. Set the M3 config value to avoid that. + */ + gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052); + /* * Note that the GMU has a slightly different layout for * chip_id, for whatever reason, so a bit of massaging From 6ab410e0ffa3c8aa2fe10692346cf6df59d57a02 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:10:40 +0200 Subject: [PATCH 103/118] drm/msm/a6xx: Improve GMU force shutdown sequence The GMU force shutdown sequence involves some additional register cleanup which was not implemented previously. Do so. Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/543340/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 452beb90d53c..0bf12524cae4 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -899,6 +899,13 @@ static void a6xx_gmu_force_off(struct a6xx_gmu *gmu) /* Make sure there are no outstanding RPMh votes */ a6xx_gmu_rpmh_off(gmu); + /* Clear the WRITEDROPPED fields and put fence into allow mode */ + gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7); + gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); + + /* Make sure the above writes go through */ + wmb(); + /* Halt the gmu cm3 core */ gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); From 1bfa7951459de5ed32dd02ae9578aed5174d3dd1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 20 Jun 2023 13:10:41 +0200 Subject: [PATCH 104/118] drm/msm/a6xx: Fix up GMU region reservations Change the order of region allocations to make the addresses match downstream. This shouldn't matter very much, but helps eliminate one more difference when comparing register accesses. Also, make the log region 16K long. That's what it is, unconditionally on A6xx and A7xx. Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/543338/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 0bf12524cae4..8325d37d4914 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1646,13 +1646,13 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) goto err_memory; } - /* Allocate memory for for the HFI queues */ - ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi"); + /* Allocate memory for the GMU log region */ + ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_16K, 0, "log"); if (ret) goto err_memory; - /* Allocate memory for the GMU log region */ - ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0, "log"); + /* Allocate memory for for the HFI queues */ + ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi"); if (ret) goto err_memory; From db07ce5da8b26bfeaf437a676ae49bd3bb1eace6 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 20 Jun 2023 20:23:19 -0300 Subject: [PATCH 105/118] drm/msm/a2xx: Call adreno_gpu_init() earlier The adreno_is_a20x() and adreno_is_a225() functions rely on the GPU revision, but such information is retrieved inside adreno_gpu_init(), which is called afterwards. Fix this problem by caling adreno_gpu_init() earlier, so that the GPU information revision is available when adreno_is_a20x() and adreno_is_a225() run. Tested on a imx53-qsb board. Fixes: 21af872cd8c6 ("drm/msm/adreno: add a2xx") Signed-off-by: Fabio Estevam Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/543456/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c index 50ee03bc94b4..0d8133f3174b 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -540,6 +540,10 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev) gpu->perfcntrs = perfcntrs; gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs); + ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); + if (ret) + goto fail; + if (adreno_is_a20x(adreno_gpu)) adreno_gpu->registers = a200_registers; else if (adreno_is_a225(adreno_gpu)) @@ -547,10 +551,6 @@ struct msm_gpu *a2xx_gpu_init(struct drm_device *dev) else adreno_gpu->registers = a220_registers; - ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1); - if (ret) - goto fail; - if (!gpu->aspace) { dev_err(dev->dev, "No memory protection without MMU\n"); if (!allow_vram_carveout) { From 3136a0f83519076edfbc14be65f286785434189a Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 3 Aug 2023 10:34:28 -0700 Subject: [PATCH 106/118] drm/msm/a6xx: Fix GMU lockdep splat For normal GPU devfreq, we need to acquire the GMU lock while already holding devfreq locks. But in the teardown path, we were calling dev_pm_domain_detach() while already holding the GMU lock, resulting in this lockdep splat: ====================================================== WARNING: possible circular locking dependency detected 6.4.3-debug+ #3 Not tainted ------------------------------------------------------ ring0/391 is trying to acquire lock: ffffff80a025c078 (&devfreq->lock){+.+.}-{3:3}, at: qos_notifier_call+0x30/0x74 but task is already holding lock: ffffff809b8c1ce8 (&(c->notifiers)->rwsem){++++}-{3:3}, at: blocking_notifier_call_chain+0x34/0x78 which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #4 (&(c->notifiers)->rwsem){++++}-{3:3}: down_write+0x58/0x74 __blocking_notifier_chain_register+0x64/0x84 blocking_notifier_chain_register+0x1c/0x28 freq_qos_add_notifier+0x5c/0x7c dev_pm_qos_add_notifier+0xd4/0xf0 devfreq_add_device+0x42c/0x560 devm_devfreq_add_device+0x6c/0xb8 msm_devfreq_init+0xa8/0x16c [msm] msm_gpu_init+0x368/0x54c [msm] adreno_gpu_init+0x248/0x2b0 [msm] a6xx_gpu_init+0x2d0/0x384 [msm] adreno_bind+0x264/0x2bc [msm] component_bind_all+0x124/0x1f4 msm_drm_bind+0x2d0/0x5f4 [msm] try_to_bring_up_aggregate_device+0x88/0x1a4 __component_add+0xd4/0x128 component_add+0x1c/0x28 dp_display_probe+0x37c/0x3c0 [msm] platform_probe+0x70/0xc0 really_probe+0x148/0x280 __driver_probe_device+0xfc/0x114 driver_probe_device+0x44/0x100 __device_attach_driver+0x64/0xdc bus_for_each_drv+0xb0/0xd8 __device_attach+0xe4/0x140 device_initial_probe+0x1c/0x28 bus_probe_device+0x44/0xb0 deferred_probe_work_func+0xb0/0xc8 process_one_work+0x288/0x3d8 worker_thread+0x1f0/0x260 kthread+0xf0/0x100 ret_from_fork+0x10/0x20 -> #3 (dev_pm_qos_mtx){+.+.}-{3:3}: __mutex_lock+0xc8/0x388 mutex_lock_nested+0x2c/0x38 dev_pm_qos_remove_notifier+0x3c/0xc8 genpd_remove_device+0x40/0x11c genpd_dev_pm_detach+0x88/0x130 dev_pm_domain_detach+0x2c/0x3c a6xx_gmu_remove+0x44/0xdc [msm] a6xx_destroy+0x7c/0xa4 [msm] adreno_unbind+0x50/0x64 [msm] component_unbind+0x44/0x64 component_unbind_all+0xb4/0xbc msm_drm_uninit.isra.0+0x124/0x17c [msm] msm_drm_bind+0x340/0x5f4 [msm] try_to_bring_up_aggregate_device+0x88/0x1a4 __component_add+0xd4/0x128 component_add+0x1c/0x28 dp_display_probe+0x37c/0x3c0 [msm] platform_probe+0x70/0xc0 really_probe+0x148/0x280 __driver_probe_device+0xfc/0x114 driver_probe_device+0x44/0x100 __device_attach_driver+0x64/0xdc bus_for_each_drv+0xb0/0xd8 __device_attach+0xe4/0x140 device_initial_probe+0x1c/0x28 bus_probe_device+0x44/0xb0 deferred_probe_work_func+0xb0/0xc8 process_one_work+0x288/0x3d8 worker_thread+0x1f0/0x260 kthread+0xf0/0x100 ret_from_fork+0x10/0x20 -> #2 (&a6xx_gpu->gmu.lock){+.+.}-{3:3}: __mutex_lock+0xc8/0x388 mutex_lock_nested+0x2c/0x38 a6xx_gpu_set_freq+0x38/0x64 [msm] msm_devfreq_target+0x170/0x18c [msm] devfreq_set_target+0x90/0x1e4 devfreq_update_target+0xb4/0xf0 update_devfreq+0x1c/0x28 devfreq_monitor+0x3c/0x10c process_one_work+0x288/0x3d8 worker_thread+0x1f0/0x260 kthread+0xf0/0x100 ret_from_fork+0x10/0x20 -> #1 (&df->lock){+.+.}-{3:3}: __mutex_lock+0xc8/0x388 mutex_lock_nested+0x2c/0x38 msm_devfreq_get_dev_status+0x4c/0x104 [msm] devfreq_simple_ondemand_func+0x5c/0x128 devfreq_update_target+0x68/0xf0 update_devfreq+0x1c/0x28 devfreq_monitor+0x3c/0x10c process_one_work+0x288/0x3d8 worker_thread+0x1f0/0x260 kthread+0xf0/0x100 ret_from_fork+0x10/0x20 -> #0 (&devfreq->lock){+.+.}-{3:3}: __lock_acquire+0xdf8/0x109c lock_acquire+0x234/0x284 __mutex_lock+0xc8/0x388 mutex_lock_nested+0x2c/0x38 qos_notifier_call+0x30/0x74 qos_min_notifier_call+0x1c/0x28 notifier_call_chain+0xf4/0x114 blocking_notifier_call_chain+0x4c/0x78 pm_qos_update_target+0x184/0x190 freq_qos_apply+0x4c/0x64 apply_constraint+0xf8/0xfc __dev_pm_qos_update_request+0x138/0x164 dev_pm_qos_update_request+0x44/0x68 msm_devfreq_boost+0x40/0x70 [msm] msm_devfreq_active+0xc0/0xf0 [msm] msm_gpu_submit+0xc8/0x12c [msm] msm_job_run+0x88/0x128 [msm] drm_sched_main+0x240/0x324 [gpu_sched] kthread+0xf0/0x100 ret_from_fork+0x10/0x20 other info that might help us debug this: Chain exists of: &devfreq->lock --> dev_pm_qos_mtx --> &(c->notifiers)->rwsem Possible unsafe locking scenario: CPU0 CPU1 ---- ---- rlock(&(c->notifiers)->rwsem); lock(dev_pm_qos_mtx); lock(&(c->notifiers)->rwsem); lock(&devfreq->lock); *** DEADLOCK *** 4 locks held by ring0/391: #0: ffffff809c811170 (&gpu->lock){+.+.}-{3:3}, at: msm_job_run+0x7c/0x128 [msm] #1: ffffff809c811208 (&gpu->active_lock){+.+.}-{3:3}, at: msm_gpu_submit+0xa8/0x12c [msm] #2: ffffffecbbb46600 (dev_pm_qos_mtx){+.+.}-{3:3}, at: dev_pm_qos_update_request+0x38/0x68 #3: ffffff809b8c1ce8 (&(c->notifiers)->rwsem){++++}-{3:3}, at: blocking_notifier_call_chain+0x34/0x78 stack backtrace: CPU: 6 PID: 391 Comm: ring0 Not tainted 6.4.3debug+ #3 Hardware name: Google Villager (rev1+) with LTE (DT) Call trace: dump_backtrace+0xb4/0xf0 show_stack+0x20/0x30 dump_stack_lvl+0x60/0x84 dump_stack+0x18/0x24 print_circular_bug+0x1cc/0x234 check_noncircular+0x78/0xac __lock_acquire+0xdf8/0x109c lock_acquire+0x234/0x284 __mutex_lock+0xc8/0x388 mutex_lock_nested+0x2c/0x38 qos_notifier_call+0x30/0x74 qos_min_notifier_call+0x1c/0x28 notifier_call_chain+0xf4/0x114 blocking_notifier_call_chain+0x4c/0x78 pm_qos_update_target+0x184/0x190 freq_qos_apply+0x4c/0x64 apply_constraint+0xf8/0xfc __dev_pm_qos_update_request+0x138/0x164 dev_pm_qos_update_request+0x44/0x68 msm_devfreq_boost+0x40/0x70 [msm] msm_devfreq_active+0xc0/0xf0 [msm] msm_gpu_submit+0xc8/0x12c [msm] msm_job_run+0x88/0x128 [msm] drm_sched_main+0x240/0x324 [gpu_sched] kthread+0xf0/0x100 ret_from_fork+0x10/0x20 Fix this by only synchronizing access to gmu->initialized. Fixes: 4cd15a3e8b36 ("drm/msm/a6xx: Make GPU destroy a bit safer") Cc: Douglas Anderson Signed-off-by: Rob Clark Reviewed-by: Douglas Anderson Patchwork: https://patchwork.freedesktop.org/patch/551171/ --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 11 ++++++++--- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 -- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 8325d37d4914..03fa89bf3e4b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1454,8 +1454,15 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) struct a6xx_gmu *gmu = &a6xx_gpu->gmu; struct platform_device *pdev = to_platform_device(gmu->dev); - if (!gmu->initialized) + mutex_lock(&gmu->lock); + if (!gmu->initialized) { + mutex_unlock(&gmu->lock); return; + } + + gmu->initialized = false; + + mutex_unlock(&gmu->lock); pm_runtime_force_suspend(gmu->dev); @@ -1485,8 +1492,6 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu) /* Drop reference taken in of_find_device_by_node */ put_device(gmu->dev); - - gmu->initialized = false; } static int cxpd_notifier_cb(struct notifier_block *nb, diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 15006ba63b6a..1ed202c4e497 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2097,9 +2097,7 @@ static void a6xx_destroy(struct msm_gpu *gpu) a6xx_llc_slices_destroy(a6xx_gpu); - mutex_lock(&a6xx_gpu->gmu.lock); a6xx_gmu_remove(a6xx_gpu); - mutex_unlock(&a6xx_gpu->gmu.lock); adreno_gpu_cleanup(adreno_gpu); From 42854f8d2bff3f3a36f8f1c985c69618a13ed9ec Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 3 Aug 2023 11:32:45 -0700 Subject: [PATCH 107/118] drm/msm: Disallow relocs on a6xx+ Mesa stopped using these pretty early in a6xx bringup[1]. Take advantage of this to disallow some legacy UABI. [1] https://gitlab.freedesktop.org/mesa/mesa/-/commit/7ef722861b691ce99be3827ed05f8c0ddf2cd66e Signed-off-by: Rob Clark Acked-by: Daniel Vetter Patchwork: https://patchwork.freedesktop.org/patch/551175/ --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 ++ drivers/gpu/drm/msm/msm_gem_submit.c | 10 ++++++++++ drivers/gpu/drm/msm/msm_gpu.h | 9 +++++++++ 3 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index ba35c2a87021..695cce82d914 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1078,6 +1078,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->info = config->info; adreno_gpu->chip_id = config->chip_id; + gpu->allow_relocs = config->info->family < ADRENO_6XX_GEN1; + /* Only handle the core clock when GMU is not in use (or is absent). */ if (adreno_has_gmu_wrapper(adreno_gpu) || adreno_gpu->info->family < ADRENO_6XX_GEN1) { diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c index 63c96416e183..3b908f9f5493 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -882,6 +882,16 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data, if (submit->valid) continue; + if (!gpu->allow_relocs) { + if (submit->cmd[i].nr_relocs) { + DRM_ERROR("relocs not allowed\n"); + ret = -EINVAL; + goto out; + } + + continue; + } + ret = submit_reloc(submit, msm_obj, submit->cmd[i].offset * 4, submit->cmd[i].nr_relocs, submit->cmd[i].relocs); if (ret) diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index 7a4fa1b8655b..4252e3839fbc 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -285,6 +285,15 @@ struct msm_gpu { /* True if the hardware supports expanded apriv (a650 and newer) */ bool hw_apriv; + /** + * @allow_relocs: allow relocs in SUBMIT ioctl + * + * Mesa won't use relocs for driver version 1.4.0 and later. This + * switch-over happened early enough in mesa a6xx bringup that we + * can disallow relocs for a6xx and newer. + */ + bool allow_relocs; + struct thermal_cooling_device *cooling; }; From a895037e1e98cd71f31ef3e4f266fb19d577b621 Mon Sep 17 00:00:00 2001 From: Ruan Jinjie Date: Thu, 10 Aug 2023 20:04:24 +0800 Subject: [PATCH 108/118] drm/msm/adreno: adreno_gpu: Switch to memdup_user_nul() helper Use memdup_user_nul() helper instead of open-coding to simplify the code. Signed-off-by: Ruan Jinjie Reviewed-by: Bjorn Andersson Patchwork: https://patchwork.freedesktop.org/patch/552130/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 695cce82d914..8090dde03280 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -397,17 +397,9 @@ int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx, case MSM_PARAM_CMDLINE: { char *str, **paramp; - str = kmalloc(len + 1, GFP_KERNEL); - if (!str) - return -ENOMEM; - - if (copy_from_user(str, u64_to_user_ptr(value), len)) { - kfree(str); - return -EFAULT; - } - - /* Ensure string is null terminated: */ - str[len] = '\0'; + str = memdup_user_nul(u64_to_user_ptr(value), len); + if (IS_ERR(str)) + return PTR_ERR(str); mutex_lock(&gpu->lock); From 1a8b612ef09bcba3708443339adfad9802d3e9d8 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 2 Aug 2023 15:21:49 -0700 Subject: [PATCH 109/118] drm/msm: Take lru lock once per job_run Rather than acquiring it and dropping it for each individual obj. Signed-off-by: Rob Clark Patchwork: https://patchwork.freedesktop.org/patch/551019/ --- drivers/gpu/drm/msm/msm_gem.c | 3 --- drivers/gpu/drm/msm/msm_ringbuffer.c | 5 +++++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 20cfd86d2b32..6d1dbffc3905 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -509,14 +509,11 @@ void msm_gem_unpin_locked(struct drm_gem_object *obj) */ void msm_gem_unpin_active(struct drm_gem_object *obj) { - struct msm_drm_private *priv = obj->dev->dev_private; struct msm_gem_object *msm_obj = to_msm_bo(obj); - mutex_lock(&priv->lru.lock); msm_obj->pin_count--; GEM_WARN_ON(msm_obj->pin_count < 0); update_lru_active(obj); - mutex_unlock(&priv->lru.lock); } struct msm_gem_vma *msm_gem_get_vma_locked(struct drm_gem_object *obj, diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c index b60199184409..8b8353dcde9f 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.c +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c @@ -16,10 +16,13 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job) struct msm_gem_submit *submit = to_msm_submit(job); struct msm_fence_context *fctx = submit->ring->fctx; struct msm_gpu *gpu = submit->gpu; + struct msm_drm_private *priv = gpu->dev->dev_private; int i; msm_fence_init(submit->hw_fence, fctx); + mutex_lock(&priv->lru.lock); + for (i = 0; i < submit->nr_bos; i++) { struct drm_gem_object *obj = &submit->bos[i].obj->base; @@ -28,6 +31,8 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job) submit->bos[i].flags &= ~(BO_VMA_PINNED | BO_OBJ_PINNED); } + mutex_unlock(&priv->lru.lock); + /* TODO move submit path over to using a per-ring lock.. */ mutex_lock(&gpu->lock); From 6ba5daa5d5ad54b78aeac8912092f986e8d4c38f Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 2 Aug 2023 15:21:50 -0700 Subject: [PATCH 110/118] drm/msm: Use drm_gem_object in submit bos table Basically everywhere wants the base ptr type. So store that instead of msm_gem_object. Signed-off-by: Rob Clark Patchwork: https://patchwork.freedesktop.org/patch/551021/ --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 ++-- drivers/gpu/drm/msm/msm_gem.h | 2 +- drivers/gpu/drm/msm/msm_gem_submit.c | 42 +++++++++++++-------------- drivers/gpu/drm/msm/msm_gpu.c | 20 ++++++------- drivers/gpu/drm/msm/msm_rd.c | 8 ++--- drivers/gpu/drm/msm/msm_ringbuffer.c | 2 +- 6 files changed, 40 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 041d1cd8ed99..e5916c106796 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -66,7 +66,7 @@ void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit) { struct msm_ringbuffer *ring = submit->ring; - struct msm_gem_object *obj; + struct drm_gem_object *obj; uint32_t *ptr, dwords; unsigned int i; @@ -83,7 +83,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit obj = submit->bos[submit->cmd[i].idx].obj; dwords = submit->cmd[i].size; - ptr = msm_gem_get_vaddr(&obj->base); + ptr = msm_gem_get_vaddr(obj); /* _get_vaddr() shouldn't fail at this point, * since we've already mapped it once in @@ -103,7 +103,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit OUT_RING(ring, ptr[i]); } - msm_gem_put_vaddr(&obj->base); + msm_gem_put_vaddr(obj); break; } diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h index 2bd6846c83a9..31b370474fa8 100644 --- a/drivers/gpu/drm/msm/msm_gem.h +++ b/drivers/gpu/drm/msm/msm_gem.h @@ -301,7 +301,7 @@ struct msm_gem_submit { #define BO_VMA_PINNED 0x1000 /* vma (virtual address) is pinned */ uint32_t flags; union { - struct msm_gem_object *obj; + struct drm_gem_object *obj; uint32_t handle; }; uint64_t iova; diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c index 3b908f9f5493..a03bdded1a15 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -165,7 +165,7 @@ static int submit_lookup_objects(struct msm_gem_submit *submit, drm_gem_object_get(obj); - submit->bos[i].obj = to_msm_bo(obj); + submit->bos[i].obj = obj; } out_unlock: @@ -251,7 +251,7 @@ static int submit_lookup_cmds(struct msm_gem_submit *submit, static void submit_cleanup_bo(struct msm_gem_submit *submit, int i, unsigned cleanup_flags) { - struct drm_gem_object *obj = &submit->bos[i].obj->base; + struct drm_gem_object *obj = submit->bos[i].obj; unsigned flags = submit->bos[i].flags & cleanup_flags; /* @@ -287,7 +287,7 @@ static int submit_lock_objects(struct msm_gem_submit *submit) retry: for (i = 0; i < submit->nr_bos; i++) { - struct msm_gem_object *msm_obj = submit->bos[i].obj; + struct drm_gem_object *obj = submit->bos[i].obj; if (slow_locked == i) slow_locked = -1; @@ -295,7 +295,7 @@ static int submit_lock_objects(struct msm_gem_submit *submit) contended = i; if (!(submit->bos[i].flags & BO_LOCKED)) { - ret = dma_resv_lock_interruptible(msm_obj->base.resv, + ret = dma_resv_lock_interruptible(obj->resv, &submit->ticket); if (ret) goto fail; @@ -321,9 +321,9 @@ static int submit_lock_objects(struct msm_gem_submit *submit) submit_unlock_unpin_bo(submit, slow_locked); if (ret == -EDEADLK) { - struct msm_gem_object *msm_obj = submit->bos[contended].obj; + struct drm_gem_object *obj = submit->bos[contended].obj; /* we lost out in a seqno race, lock and retry.. */ - ret = dma_resv_lock_slow_interruptible(msm_obj->base.resv, + ret = dma_resv_lock_slow_interruptible(obj->resv, &submit->ticket); if (!ret) { submit->bos[contended].flags |= BO_LOCKED; @@ -346,7 +346,7 @@ static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit) int i, ret = 0; for (i = 0; i < submit->nr_bos; i++) { - struct drm_gem_object *obj = &submit->bos[i].obj->base; + struct drm_gem_object *obj = submit->bos[i].obj; bool write = submit->bos[i].flags & MSM_SUBMIT_BO_WRITE; /* NOTE: _reserve_shared() must happen before @@ -389,7 +389,7 @@ static int submit_pin_objects(struct msm_gem_submit *submit) submit->valid = true; for (i = 0; i < submit->nr_bos; i++) { - struct drm_gem_object *obj = &submit->bos[i].obj->base; + struct drm_gem_object *obj = submit->bos[i].obj; struct msm_gem_vma *vma; /* if locking succeeded, pin bo: */ @@ -424,7 +424,7 @@ static void submit_attach_object_fences(struct msm_gem_submit *submit) int i; for (i = 0; i < submit->nr_bos; i++) { - struct drm_gem_object *obj = &submit->bos[i].obj->base; + struct drm_gem_object *obj = submit->bos[i].obj; if (submit->bos[i].flags & MSM_SUBMIT_BO_WRITE) dma_resv_add_fence(obj->resv, submit->user_fence, @@ -436,7 +436,7 @@ static void submit_attach_object_fences(struct msm_gem_submit *submit) } static int submit_bo(struct msm_gem_submit *submit, uint32_t idx, - struct msm_gem_object **obj, uint64_t *iova, bool *valid) + struct drm_gem_object **obj, uint64_t *iova, bool *valid) { if (idx >= submit->nr_bos) { DRM_ERROR("invalid buffer index: %u (out of %u)\n", @@ -455,7 +455,7 @@ static int submit_bo(struct msm_gem_submit *submit, uint32_t idx, } /* process the reloc's and patch up the cmdstream as needed: */ -static int submit_reloc(struct msm_gem_submit *submit, struct msm_gem_object *obj, +static int submit_reloc(struct msm_gem_submit *submit, struct drm_gem_object *obj, uint32_t offset, uint32_t nr_relocs, struct drm_msm_gem_submit_reloc *relocs) { uint32_t i, last_offset = 0; @@ -473,7 +473,7 @@ static int submit_reloc(struct msm_gem_submit *submit, struct msm_gem_object *ob /* For now, just map the entire thing. Eventually we probably * to do it page-by-page, w/ kmap() if not vmap()d.. */ - ptr = msm_gem_get_vaddr_locked(&obj->base); + ptr = msm_gem_get_vaddr_locked(obj); if (IS_ERR(ptr)) { ret = PTR_ERR(ptr); @@ -497,7 +497,7 @@ static int submit_reloc(struct msm_gem_submit *submit, struct msm_gem_object *ob /* offset in dwords: */ off = submit_reloc.submit_offset / 4; - if ((off >= (obj->base.size / 4)) || + if ((off >= (obj->size / 4)) || (off < last_offset)) { DRM_ERROR("invalid offset %u at reloc %u\n", off, i); ret = -EINVAL; @@ -524,7 +524,7 @@ static int submit_reloc(struct msm_gem_submit *submit, struct msm_gem_object *ob } out: - msm_gem_put_vaddr_locked(&obj->base); + msm_gem_put_vaddr_locked(obj); return ret; } @@ -542,10 +542,10 @@ static void submit_cleanup(struct msm_gem_submit *submit, bool error) cleanup_flags |= BO_VMA_PINNED | BO_OBJ_PINNED; for (i = 0; i < submit->nr_bos; i++) { - struct msm_gem_object *msm_obj = submit->bos[i].obj; + struct drm_gem_object *obj = submit->bos[i].obj; submit_cleanup_bo(submit, i, cleanup_flags); if (error) - drm_gem_object_put(&msm_obj->base); + drm_gem_object_put(obj); } } @@ -554,7 +554,7 @@ void msm_submit_retire(struct msm_gem_submit *submit) int i; for (i = 0; i < submit->nr_bos; i++) { - struct drm_gem_object *obj = &submit->bos[i].obj->base; + struct drm_gem_object *obj = submit->bos[i].obj; drm_gem_object_put(obj); } @@ -861,17 +861,17 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data, goto out; for (i = 0; i < args->nr_cmds; i++) { - struct msm_gem_object *msm_obj; + struct drm_gem_object *obj; uint64_t iova; ret = submit_bo(submit, submit->cmd[i].idx, - &msm_obj, &iova, NULL); + &obj, &iova, NULL); if (ret) goto out; if (!submit->cmd[i].size || ((submit->cmd[i].size + submit->cmd[i].offset) > - msm_obj->base.size / 4)) { + obj->size / 4)) { DRM_ERROR("invalid cmdstream size: %u\n", submit->cmd[i].size * 4); ret = -EINVAL; goto out; @@ -892,7 +892,7 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data, continue; } - ret = submit_reloc(submit, msm_obj, submit->cmd[i].offset * 4, + ret = submit_reloc(submit, obj, submit->cmd[i].offset * 4, submit->cmd[i].nr_relocs, submit->cmd[i].relocs); if (ret) goto out; diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 8a9bacc920eb..5c10b559a595 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -219,36 +219,36 @@ static void msm_gpu_devcoredump_free(void *data) } static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state, - struct msm_gem_object *obj, u64 iova, bool full) + struct drm_gem_object *obj, u64 iova, bool full) { struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos]; /* Don't record write only objects */ - state_bo->size = obj->base.size; + state_bo->size = obj->size; state_bo->iova = iova; - BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(obj->name)); + BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(to_msm_bo(obj)->name)); - memcpy(state_bo->name, obj->name, sizeof(state_bo->name)); + memcpy(state_bo->name, to_msm_bo(obj)->name, sizeof(state_bo->name)); if (full) { void *ptr; - state_bo->data = kvmalloc(obj->base.size, GFP_KERNEL); + state_bo->data = kvmalloc(obj->size, GFP_KERNEL); if (!state_bo->data) goto out; - msm_gem_lock(&obj->base); - ptr = msm_gem_get_vaddr_active(&obj->base); - msm_gem_unlock(&obj->base); + msm_gem_lock(obj); + ptr = msm_gem_get_vaddr_active(obj); + msm_gem_unlock(obj); if (IS_ERR(ptr)) { kvfree(state_bo->data); state_bo->data = NULL; goto out; } - memcpy(state_bo->data, ptr, obj->base.size); - msm_gem_put_vaddr(&obj->base); + memcpy(state_bo->data, ptr, obj->size); + msm_gem_put_vaddr(obj); } out: state->nr_bos++; diff --git a/drivers/gpu/drm/msm/msm_rd.c b/drivers/gpu/drm/msm/msm_rd.c index 8d5687d5ed78..5adc51f7ab59 100644 --- a/drivers/gpu/drm/msm/msm_rd.c +++ b/drivers/gpu/drm/msm/msm_rd.c @@ -310,7 +310,7 @@ static void snapshot_buf(struct msm_rd_state *rd, struct msm_gem_submit *submit, int idx, uint64_t iova, uint32_t size, bool full) { - struct msm_gem_object *obj = submit->bos[idx].obj; + struct drm_gem_object *obj = submit->bos[idx].obj; unsigned offset = 0; const char *buf; @@ -318,7 +318,7 @@ static void snapshot_buf(struct msm_rd_state *rd, offset = iova - submit->bos[idx].iova; } else { iova = submit->bos[idx].iova; - size = obj->base.size; + size = obj->size; } /* @@ -335,7 +335,7 @@ static void snapshot_buf(struct msm_rd_state *rd, if (!(submit->bos[idx].flags & MSM_SUBMIT_BO_READ)) return; - buf = msm_gem_get_vaddr_active(&obj->base); + buf = msm_gem_get_vaddr_active(obj); if (IS_ERR(buf)) return; @@ -343,7 +343,7 @@ static void snapshot_buf(struct msm_rd_state *rd, rd_write_section(rd, RD_BUFFER_CONTENTS, buf, size); - msm_gem_put_vaddr_locked(&obj->base); + msm_gem_put_vaddr_locked(obj); } /* called under gpu->lock */ diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c index 8b8353dcde9f..6fa427d2992e 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.c +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c @@ -24,7 +24,7 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job) mutex_lock(&priv->lru.lock); for (i = 0; i < submit->nr_bos; i++) { - struct drm_gem_object *obj = &submit->bos[i].obj->base; + struct drm_gem_object *obj = submit->bos[i].obj; msm_gem_vma_unpin_fenced(submit->bos[i].vma, fctx); msm_gem_unpin_active(obj); From fc896cf3d6913fb0e79ec146fff6dcda5aaa4384 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 2 Aug 2023 15:21:51 -0700 Subject: [PATCH 111/118] drm/msm: Take lru lock once per submit_pin_objects() Split out pin_count incrementing and lru updating into a separate loop so we can take the lru lock only once for all objs. Since we are still holding the obj lock, it is safe to split this up. Signed-off-by: Rob Clark Patchwork: https://patchwork.freedesktop.org/patch/551025/ --- drivers/gpu/drm/msm/msm_gem.c | 45 ++++++++++++++++++---------- drivers/gpu/drm/msm/msm_gem.h | 1 + drivers/gpu/drm/msm/msm_gem_submit.c | 17 ++++++++++- 3 files changed, 46 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 6d1dbffc3905..1c81ff6115ac 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -222,9 +222,7 @@ static void put_pages(struct drm_gem_object *obj) static struct page **msm_gem_pin_pages_locked(struct drm_gem_object *obj, unsigned madv) { - struct msm_drm_private *priv = obj->dev->dev_private; struct msm_gem_object *msm_obj = to_msm_bo(obj); - struct page **p; msm_gem_assert_locked(obj); @@ -234,16 +232,29 @@ static struct page **msm_gem_pin_pages_locked(struct drm_gem_object *obj, return ERR_PTR(-EBUSY); } - p = get_pages(obj); - if (IS_ERR(p)) - return p; + return get_pages(obj); +} + +/* + * Update the pin count of the object, call under lru.lock + */ +void msm_gem_pin_obj_locked(struct drm_gem_object *obj) +{ + struct msm_drm_private *priv = obj->dev->dev_private; + + msm_gem_assert_locked(obj); + + to_msm_bo(obj)->pin_count++; + drm_gem_lru_move_tail_locked(&priv->lru.pinned, obj); +} + +static void pin_obj_locked(struct drm_gem_object *obj) +{ + struct msm_drm_private *priv = obj->dev->dev_private; mutex_lock(&priv->lru.lock); - msm_obj->pin_count++; - update_lru_locked(obj); + msm_gem_pin_obj_locked(obj); mutex_unlock(&priv->lru.lock); - - return p; } struct page **msm_gem_pin_pages(struct drm_gem_object *obj) @@ -252,6 +263,8 @@ struct page **msm_gem_pin_pages(struct drm_gem_object *obj) msm_gem_lock(obj); p = msm_gem_pin_pages_locked(obj, MSM_MADV_WILLNEED); + if (!IS_ERR(p)) + pin_obj_locked(obj); msm_gem_unlock(obj); return p; @@ -463,7 +476,7 @@ int msm_gem_pin_vma_locked(struct drm_gem_object *obj, struct msm_gem_vma *vma) { struct msm_gem_object *msm_obj = to_msm_bo(obj); struct page **pages; - int ret, prot = IOMMU_READ; + int prot = IOMMU_READ; if (!(msm_obj->flags & MSM_BO_GPU_READONLY)) prot |= IOMMU_WRITE; @@ -480,11 +493,7 @@ int msm_gem_pin_vma_locked(struct drm_gem_object *obj, struct msm_gem_vma *vma) if (IS_ERR(pages)) return PTR_ERR(pages); - ret = msm_gem_vma_map(vma, prot, msm_obj->sgt, obj->size); - if (ret) - msm_gem_unpin_locked(obj); - - return ret; + return msm_gem_vma_map(vma, prot, msm_obj->sgt, obj->size); } void msm_gem_unpin_locked(struct drm_gem_object *obj) @@ -536,8 +545,10 @@ static int get_and_pin_iova_range_locked(struct drm_gem_object *obj, return PTR_ERR(vma); ret = msm_gem_pin_vma_locked(obj, vma); - if (!ret) + if (!ret) { *iova = vma->iova; + pin_obj_locked(obj); + } return ret; } @@ -700,6 +711,8 @@ static void *get_vaddr(struct drm_gem_object *obj, unsigned madv) if (IS_ERR(pages)) return ERR_CAST(pages); + pin_obj_locked(obj); + /* increment vmap_count *before* vmap() call, so shrinker can * check vmap_count (is_vunmapable()) outside of msm_obj lock. * This guarantees that we won't try to msm_gem_vunmap() this diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h index 31b370474fa8..2ddd896aac68 100644 --- a/drivers/gpu/drm/msm/msm_gem.h +++ b/drivers/gpu/drm/msm/msm_gem.h @@ -142,6 +142,7 @@ int msm_gem_get_and_pin_iova(struct drm_gem_object *obj, struct msm_gem_address_space *aspace, uint64_t *iova); void msm_gem_unpin_iova(struct drm_gem_object *obj, struct msm_gem_address_space *aspace); +void msm_gem_pin_obj_locked(struct drm_gem_object *obj); struct page **msm_gem_pin_pages(struct drm_gem_object *obj); void msm_gem_unpin_pages(struct drm_gem_object *obj); int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c index a03bdded1a15..ec5aa6932ea1 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -384,6 +384,7 @@ static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit) static int submit_pin_objects(struct msm_gem_submit *submit) { + struct msm_drm_private *priv = submit->dev->dev_private; int i, ret = 0; submit->valid = true; @@ -403,7 +404,7 @@ static int submit_pin_objects(struct msm_gem_submit *submit) if (ret) break; - submit->bos[i].flags |= BO_OBJ_PINNED | BO_VMA_PINNED; + submit->bos[i].flags |= BO_VMA_PINNED; submit->bos[i].vma = vma; if (vma->iova == submit->bos[i].iova) { @@ -416,6 +417,20 @@ static int submit_pin_objects(struct msm_gem_submit *submit) } } + /* + * A second loop while holding the LRU lock (a) avoids acquiring/dropping + * the LRU lock for each individual bo, while (b) avoiding holding the + * LRU lock while calling msm_gem_pin_vma_locked() (which could trigger + * get_pages() which could trigger reclaim.. and if we held the LRU lock + * could trigger deadlock with the shrinker). + */ + mutex_lock(&priv->lru.lock); + for (i = 0; i < submit->nr_bos; i++) { + msm_gem_pin_obj_locked(submit->bos[i].obj); + submit->bos[i].flags |= BO_OBJ_PINNED; + } + mutex_unlock(&priv->lru.lock); + return ret; } From 7391c282ba0f0e82ac131658e2faf712215ed6a2 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 2 Aug 2023 15:21:52 -0700 Subject: [PATCH 112/118] drm/msm: Remove vma use tracking This was not strictly necessary, as page unpinning (ie. shrinker) only cares about the resv. It did give us some extra sanity checking for userspace controlled iova, and was useful to catch issues on kernel and userspace side when enabling userspace iova. But if userspace screws this up, it just corrupts it's own gpu buffers and/or gets iova faults. So we can just let userspace shoot it's own foot and drop the extra per- buffer SUBMIT overhead. Signed-off-by: Rob Clark Acked-by: Daniel Vetter Patchwork: https://patchwork.freedesktop.org/patch/551023/ --- drivers/gpu/drm/msm/msm_gem.c | 9 +--- drivers/gpu/drm/msm/msm_gem.h | 12 +---- drivers/gpu/drm/msm/msm_gem_submit.c | 14 ++---- drivers/gpu/drm/msm/msm_gem_vma.c | 67 +--------------------------- drivers/gpu/drm/msm/msm_ringbuffer.c | 3 +- 5 files changed, 9 insertions(+), 96 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 1c81ff6115ac..ce1ed0f9ad2d 100644 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -607,9 +607,6 @@ static int clear_iova(struct drm_gem_object *obj, if (!vma) return 0; - if (msm_gem_vma_inuse(vma)) - return -EBUSY; - msm_gem_vma_purge(vma); msm_gem_vma_close(vma); del_vma(vma); @@ -660,7 +657,6 @@ void msm_gem_unpin_iova(struct drm_gem_object *obj, msm_gem_lock(obj); vma = lookup_vma(obj, aspace); if (!GEM_WARN_ON(!vma)) { - msm_gem_vma_unpin(vma); msm_gem_unpin_locked(obj); } msm_gem_unlock(obj); @@ -991,11 +987,10 @@ void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m, } else { name = comm = NULL; } - seq_printf(m, " [%s%s%s: aspace=%p, %08llx,%s,inuse=%d]", + seq_printf(m, " [%s%s%s: aspace=%p, %08llx,%s]", name, comm ? ":" : "", comm ? comm : "", vma->aspace, vma->iova, - vma->mapped ? "mapped" : "unmapped", - msm_gem_vma_inuse(vma)); + vma->mapped ? "mapped" : "unmapped"); kfree(comm); } diff --git a/drivers/gpu/drm/msm/msm_gem.h b/drivers/gpu/drm/msm/msm_gem.h index 2ddd896aac68..8ddef5443140 100644 --- a/drivers/gpu/drm/msm/msm_gem.h +++ b/drivers/gpu/drm/msm/msm_gem.h @@ -59,24 +59,16 @@ struct msm_fence_context; struct msm_gem_vma { struct drm_mm_node node; - spinlock_t lock; uint64_t iova; struct msm_gem_address_space *aspace; struct list_head list; /* node in msm_gem_object::vmas */ bool mapped; - int inuse; - uint32_t fence_mask; - uint32_t fence[MSM_GPU_MAX_RINGS]; - struct msm_fence_context *fctx[MSM_GPU_MAX_RINGS]; }; struct msm_gem_vma *msm_gem_vma_new(struct msm_gem_address_space *aspace); int msm_gem_vma_init(struct msm_gem_vma *vma, int size, u64 range_start, u64 range_end); -bool msm_gem_vma_inuse(struct msm_gem_vma *vma); void msm_gem_vma_purge(struct msm_gem_vma *vma); -void msm_gem_vma_unpin(struct msm_gem_vma *vma); -void msm_gem_vma_unpin_fenced(struct msm_gem_vma *vma, struct msm_fence_context *fctx); int msm_gem_vma_map(struct msm_gem_vma *vma, int prot, struct sg_table *sgt, int size); void msm_gem_vma_close(struct msm_gem_vma *vma); @@ -298,15 +290,13 @@ struct msm_gem_submit { /* make sure these don't conflict w/ MSM_SUBMIT_BO_x */ #define BO_VALID 0x8000 /* is current addr in cmdstream correct/valid? */ #define BO_LOCKED 0x4000 /* obj lock is held */ -#define BO_OBJ_PINNED 0x2000 /* obj (pages) is pinned and on active list */ -#define BO_VMA_PINNED 0x1000 /* vma (virtual address) is pinned */ +#define BO_PINNED 0x2000 /* obj (pages) is pinned and on active list */ uint32_t flags; union { struct drm_gem_object *obj; uint32_t handle; }; uint64_t iova; - struct msm_gem_vma *vma; } bos[]; }; diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c index ec5aa6932ea1..99744de6c05a 100644 --- a/drivers/gpu/drm/msm/msm_gem_submit.c +++ b/drivers/gpu/drm/msm/msm_gem_submit.c @@ -261,10 +261,7 @@ static void submit_cleanup_bo(struct msm_gem_submit *submit, int i, */ submit->bos[i].flags &= ~cleanup_flags; - if (flags & BO_VMA_PINNED) - msm_gem_vma_unpin(submit->bos[i].vma); - - if (flags & BO_OBJ_PINNED) + if (flags & BO_PINNED) msm_gem_unpin_locked(obj); if (flags & BO_LOCKED) @@ -273,7 +270,7 @@ static void submit_cleanup_bo(struct msm_gem_submit *submit, int i, static void submit_unlock_unpin_bo(struct msm_gem_submit *submit, int i) { - unsigned cleanup_flags = BO_VMA_PINNED | BO_OBJ_PINNED | BO_LOCKED; + unsigned cleanup_flags = BO_PINNED | BO_LOCKED; submit_cleanup_bo(submit, i, cleanup_flags); if (!(submit->bos[i].flags & BO_VALID)) @@ -404,9 +401,6 @@ static int submit_pin_objects(struct msm_gem_submit *submit) if (ret) break; - submit->bos[i].flags |= BO_VMA_PINNED; - submit->bos[i].vma = vma; - if (vma->iova == submit->bos[i].iova) { submit->bos[i].flags |= BO_VALID; } else { @@ -427,7 +421,7 @@ static int submit_pin_objects(struct msm_gem_submit *submit) mutex_lock(&priv->lru.lock); for (i = 0; i < submit->nr_bos; i++) { msm_gem_pin_obj_locked(submit->bos[i].obj); - submit->bos[i].flags |= BO_OBJ_PINNED; + submit->bos[i].flags |= BO_PINNED; } mutex_unlock(&priv->lru.lock); @@ -554,7 +548,7 @@ static void submit_cleanup(struct msm_gem_submit *submit, bool error) unsigned i; if (error) - cleanup_flags |= BO_VMA_PINNED | BO_OBJ_PINNED; + cleanup_flags |= BO_PINNED; for (i = 0; i < submit->nr_bos; i++) { struct drm_gem_object *obj = submit->bos[i].obj; diff --git a/drivers/gpu/drm/msm/msm_gem_vma.c b/drivers/gpu/drm/msm/msm_gem_vma.c index 98287ed99960..11e842dda73c 100644 --- a/drivers/gpu/drm/msm/msm_gem_vma.c +++ b/drivers/gpu/drm/msm/msm_gem_vma.c @@ -38,41 +38,12 @@ msm_gem_address_space_get(struct msm_gem_address_space *aspace) return aspace; } -bool msm_gem_vma_inuse(struct msm_gem_vma *vma) -{ - bool ret = true; - - spin_lock(&vma->lock); - - if (vma->inuse > 0) - goto out; - - while (vma->fence_mask) { - unsigned idx = ffs(vma->fence_mask) - 1; - - if (!msm_fence_completed(vma->fctx[idx], vma->fence[idx])) - goto out; - - vma->fence_mask &= ~BIT(idx); - } - - ret = false; - -out: - spin_unlock(&vma->lock); - - return ret; -} - /* Actually unmap memory for the vma */ void msm_gem_vma_purge(struct msm_gem_vma *vma) { struct msm_gem_address_space *aspace = vma->aspace; unsigned size = vma->node.size; - /* Print a message if we try to purge a vma in use */ - GEM_WARN_ON(msm_gem_vma_inuse(vma)); - /* Don't do anything if the memory isn't mapped */ if (!vma->mapped) return; @@ -82,33 +53,6 @@ void msm_gem_vma_purge(struct msm_gem_vma *vma) vma->mapped = false; } -static void vma_unpin_locked(struct msm_gem_vma *vma) -{ - if (GEM_WARN_ON(!vma->inuse)) - return; - if (!GEM_WARN_ON(!vma->iova)) - vma->inuse--; -} - -/* Remove reference counts for the mapping */ -void msm_gem_vma_unpin(struct msm_gem_vma *vma) -{ - spin_lock(&vma->lock); - vma_unpin_locked(vma); - spin_unlock(&vma->lock); -} - -/* Replace pin reference with fence: */ -void msm_gem_vma_unpin_fenced(struct msm_gem_vma *vma, struct msm_fence_context *fctx) -{ - spin_lock(&vma->lock); - vma->fctx[fctx->index] = fctx; - vma->fence[fctx->index] = fctx->last_fence; - vma->fence_mask |= BIT(fctx->index); - vma_unpin_locked(vma); - spin_unlock(&vma->lock); -} - /* Map and pin vma: */ int msm_gem_vma_map(struct msm_gem_vma *vma, int prot, @@ -120,11 +64,6 @@ msm_gem_vma_map(struct msm_gem_vma *vma, int prot, if (GEM_WARN_ON(!vma->iova)) return -EINVAL; - /* Increase the usage counter */ - spin_lock(&vma->lock); - vma->inuse++; - spin_unlock(&vma->lock); - if (vma->mapped) return 0; @@ -146,9 +85,6 @@ msm_gem_vma_map(struct msm_gem_vma *vma, int prot, if (ret) { vma->mapped = false; - spin_lock(&vma->lock); - vma->inuse--; - spin_unlock(&vma->lock); } return ret; @@ -159,7 +95,7 @@ void msm_gem_vma_close(struct msm_gem_vma *vma) { struct msm_gem_address_space *aspace = vma->aspace; - GEM_WARN_ON(msm_gem_vma_inuse(vma) || vma->mapped); + GEM_WARN_ON(vma->mapped); spin_lock(&aspace->lock); if (vma->iova) @@ -179,7 +115,6 @@ struct msm_gem_vma *msm_gem_vma_new(struct msm_gem_address_space *aspace) if (!vma) return NULL; - spin_lock_init(&vma->lock); vma->aspace = aspace; return vma; diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c index 6fa427d2992e..7f5e0a961bba 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.c +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c @@ -26,9 +26,8 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job) for (i = 0; i < submit->nr_bos; i++) { struct drm_gem_object *obj = submit->bos[i].obj; - msm_gem_vma_unpin_fenced(submit->bos[i].vma, fctx); msm_gem_unpin_active(obj); - submit->bos[i].flags &= ~(BO_VMA_PINNED | BO_OBJ_PINNED); + submit->bos[i].flags &= ~BO_PINNED; } mutex_unlock(&priv->lru.lock); From 18ff50e582a08eb365729b7c5507a86c41f2edf8 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Fri, 11 Aug 2023 09:05:03 -0700 Subject: [PATCH 113/118] drm/msm/a690: Switch to a660_gmu.bin There isn't actually a a690_gmu.bin. But it appears that the normal a660_gmu.bin works fine. Normally all the devices within a sub- generation (or "family") will use the same fw, and a690 is in the a660 family. Signed-off-by: Rob Clark Fixes: 5e7665b5e484 ("drm/msm/adreno: Add Adreno A690 support") Reviewed-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/552406/ --- drivers/gpu/drm/msm/adreno/adreno_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 9cda403ebc7b..e46497ef8acd 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -480,7 +480,7 @@ static const struct adreno_info gpulist[] = { .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", - [ADRENO_FW_GMU] = "a690_gmu.bin", + [ADRENO_FW_GMU] = "a660_gmu.bin", }, .gmem = SZ_4M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, From abe2023b4cea192ab266b351fd38dc9dbd846df0 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 10 Aug 2023 14:31:41 -0700 Subject: [PATCH 114/118] drm/msm/gpu: Push gpu lock down past runpm Avoid holding gpu lock when calling runpm, to avoid this lockdep splat: ====================================================== WARNING: possible circular locking dependency detected 6.4.3-debug+ #14 Not tainted ------------------------------------------------------ ring0/373 is trying to acquire lock: ffffffead86efb98 (prepare_lock){+.+.}-{3:3}, at: clk_prepare_lock+0x70/0x98 but task is already holding lock: ffffff809cd19170 (&gpu->lock){+.+.}-{3:3}, at: msm_job_run+0x7c/0x128 [msm] which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #4 (&gpu->lock){+.+.}-{3:3}: __mutex_lock+0xc8/0x388 mutex_lock_nested+0x2c/0x38 msm_job_run+0x7c/0x128 [msm] drm_sched_main+0x264/0x354 [gpu_sched] kthread+0xf0/0x100 ret_from_fork+0x10/0x20 -> #3 (dma_fence_map){++++}-{0:0}: __dma_fence_might_wait+0x74/0xc0 dma_resv_lockdep+0x1f0/0x2e8 do_one_initcall+0xb4/0x214 kernel_init_freeable+0x338/0x33c kernel_init+0x30/0x134 ret_from_fork+0x10/0x20 -> #2 (mmu_notifier_invalidate_range_start){+.+.}-{0:0}: fs_reclaim_acquire+0x7c/0x9c slab_pre_alloc_hook.constprop.0+0x40/0x250 __kmem_cache_alloc_node+0x60/0x18c kmalloc_node_trace+0x40/0x84 alloc_worker+0x2c/0x64 init_rescuer+0x34/0xe0 workqueue_init+0x168/0x1fc kernel_init_freeable+0x15c/0x33c kernel_init+0x30/0x134 ret_from_fork+0x10/0x20 -> #1 (fs_reclaim){+.+.}-{0:0}: __fs_reclaim_acquire+0x3c/0x48 fs_reclaim_acquire+0x50/0x9c slab_pre_alloc_hook.constprop.0+0x40/0x250 __kmem_cache_alloc_node+0x60/0x18c kmalloc_trace+0x44/0x88 clk_rcg2_dfs_determine_rate+0x60/0x214 clk_core_determine_round_nolock+0xb8/0xf0 clk_core_round_rate_nolock+0x84/0x118 clk_core_round_rate_nolock+0xd8/0x118 clk_round_rate+0x6c/0xd0 geni_se_clk_tbl_get+0x78/0xc0 geni_se_clk_freq_match+0x44/0xe4 get_spi_clk_cfg+0x50/0xf4 geni_spi_set_clock_and_bw+0x54/0x104 spi_geni_prepare_message+0x130/0x174 __spi_pump_transfer_message+0x200/0x4d8 __spi_sync+0x13c/0x23c spi_sync_locked+0x18/0x24 do_cros_ec_pkt_xfer_spi+0x124/0x3f0 cros_ec_xfer_high_pri_work+0x28/0x3c kthread_worker_fn+0x14c/0x27c kthread+0xf0/0x100 ret_from_fork+0x10/0x20 -> #0 (prepare_lock){+.+.}-{3:3}: __lock_acquire+0xdf8/0x109c lock_acquire+0x234/0x284 __mutex_lock+0xc8/0x388 mutex_lock_nested+0x2c/0x38 clk_prepare_lock+0x70/0x98 clk_prepare+0x24/0x50 clk_bulk_prepare+0x50/0x9c a6xx_gmu_resume+0x94/0x800 [msm] a6xx_gmu_pm_resume+0x38/0x158 [msm] adreno_runtime_resume+0x2c/0x38 [msm] pm_generic_runtime_resume+0x30/0x44 __rpm_callback+0x4c/0x134 rpm_callback+0x78/0x7c rpm_resume+0x3a4/0x46c __pm_runtime_resume+0x78/0xbc pm_runtime_get_sync.isra.0+0x14/0x20 [msm] msm_gpu_submit+0x4c/0x12c [msm] msm_job_run+0x88/0x128 [msm] drm_sched_main+0x264/0x354 [gpu_sched] kthread+0xf0/0x100 ret_from_fork+0x10/0x20 other info that might help us debug this: Chain exists of: prepare_lock --> dma_fence_map --> &gpu->lock Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&gpu->lock); lock(dma_fence_map); lock(&gpu->lock); lock(prepare_lock); *** DEADLOCK *** 2 locks held by ring0/373: #0: ffffffead875ae50 (dma_fence_map){++++}-{0:0}, at: drm_sched_main+0x54/0x354 [gpu_sched] #1: ffffff809cd19170 (&gpu->lock){+.+.}-{3:3}, at: msm_job_run+0x7c/0x128 [msm] stack backtrace: CPU: 2 PID: 373 Comm: ring0 Not tainted 6.4.3-debug+ #14 Hardware name: Google Villager (rev1+) with LTE (DT) Call trace: dump_backtrace+0xb4/0xf0 show_stack+0x20/0x30 dump_stack_lvl+0x60/0x84 dump_stack+0x18/0x24 print_circular_bug+0x1cc/0x234 check_noncircular+0x78/0xac __lock_acquire+0xdf8/0x109c lock_acquire+0x234/0x284 __mutex_lock+0xc8/0x388 mutex_lock_nested+0x2c/0x38 clk_prepare_lock+0x70/0x98 clk_prepare+0x24/0x50 clk_bulk_prepare+0x50/0x9c a6xx_gmu_resume+0x94/0x800 [msm] a6xx_gmu_pm_resume+0x38/0x158 [msm] adreno_runtime_resume+0x2c/0x38 [msm] pm_generic_runtime_resume+0x30/0x44 __rpm_callback+0x4c/0x134 rpm_callback+0x78/0x7c rpm_resume+0x3a4/0x46c __pm_runtime_resume+0x78/0xbc pm_runtime_get_sync.isra.0+0x14/0x20 [msm] msm_gpu_submit+0x4c/0x12c [msm] msm_job_run+0x88/0x128 [msm] drm_sched_main+0x264/0x354 [gpu_sched] kthread+0xf0/0x100 ret_from_fork+0x10/0x20 Signed-off-by: Rob Clark Patchwork: https://patchwork.freedesktop.org/patch/552298/ --- drivers/gpu/drm/msm/msm_gpu.c | 11 ++++++----- drivers/gpu/drm/msm/msm_ringbuffer.c | 7 ++----- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 5c10b559a595..7f64c6667300 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -749,13 +749,11 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) struct msm_ringbuffer *ring = submit->ring; unsigned long flags; - WARN_ON(!mutex_is_locked(&gpu->lock)); - pm_runtime_get_sync(&gpu->pdev->dev); - msm_gpu_hw_init(gpu); + mutex_lock(&gpu->lock); - submit->seqno = submit->hw_fence->seqno; + msm_gpu_hw_init(gpu); update_sw_cntrs(gpu); @@ -781,8 +779,11 @@ void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) gpu->funcs->submit(gpu, submit); gpu->cur_ctx_seqno = submit->queue->ctx->seqno; - pm_runtime_put(&gpu->pdev->dev); hangcheck_timer_reset(gpu); + + mutex_unlock(&gpu->lock); + + pm_runtime_put(&gpu->pdev->dev); } /* diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c index 7f5e0a961bba..40c0bc35a44c 100644 --- a/drivers/gpu/drm/msm/msm_ringbuffer.c +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c @@ -21,6 +21,8 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job) msm_fence_init(submit->hw_fence, fctx); + submit->seqno = submit->hw_fence->seqno; + mutex_lock(&priv->lru.lock); for (i = 0; i < submit->nr_bos; i++) { @@ -32,13 +34,8 @@ static struct dma_fence *msm_job_run(struct drm_sched_job *job) mutex_unlock(&priv->lru.lock); - /* TODO move submit path over to using a per-ring lock.. */ - mutex_lock(&gpu->lock); - msm_gpu_submit(gpu, submit); - mutex_unlock(&gpu->lock); - return dma_fence_get(submit->hw_fence); } From cb0aacde1e2c734119a53ecb313093e30b821f28 Mon Sep 17 00:00:00 2001 From: Juerg Haefliger Date: Tue, 20 Jun 2023 07:40:31 +0200 Subject: [PATCH 115/118] drm/msm/adreno: Add missing MODULE_FIRMWARE macros The driver references some firmware files that don't have corresponding MODULE_FIRMWARE macros and thus won't be listed via modinfo. Fix that. Signed-off-by: Juerg Haefliger Reviewed-by: Dmitry Baryshkov Reviewed-by: Joel Fernandes (Google) Patchwork: https://patchwork.freedesktop.org/patch/543290/ [rob: drop a690_gmu.bin as a690 is using same fw as a660 now] Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_device.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index e46497ef8acd..575e7c56219f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -506,10 +506,20 @@ MODULE_FIRMWARE("qcom/a530_zap.mdt"); MODULE_FIRMWARE("qcom/a530_zap.b00"); MODULE_FIRMWARE("qcom/a530_zap.b01"); MODULE_FIRMWARE("qcom/a530_zap.b02"); +MODULE_FIRMWARE("qcom/a540_gpmu.fw2"); MODULE_FIRMWARE("qcom/a619_gmu.bin"); MODULE_FIRMWARE("qcom/a630_sqe.fw"); MODULE_FIRMWARE("qcom/a630_gmu.bin"); MODULE_FIRMWARE("qcom/a630_zap.mbn"); +MODULE_FIRMWARE("qcom/a640_gmu.bin"); +MODULE_FIRMWARE("qcom/a650_gmu.bin"); +MODULE_FIRMWARE("qcom/a650_sqe.fw"); +MODULE_FIRMWARE("qcom/a660_gmu.bin"); +MODULE_FIRMWARE("qcom/a660_sqe.fw"); +MODULE_FIRMWARE("qcom/leia_pfp_470.fw"); +MODULE_FIRMWARE("qcom/leia_pm4_470.fw"); +MODULE_FIRMWARE("qcom/yamato_pfp.fw"); +MODULE_FIRMWARE("qcom/yamato_pm4.fw"); static const struct adreno_info *adreno_info(uint32_t chip_id) { From 26ed8d3dc06dd154583db19c3bd19824d989e8d8 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 8 Aug 2023 23:02:43 +0200 Subject: [PATCH 116/118] drm/msm/a6xx: Introduce a6xx_llc_read Add a helper that does exactly what it says on the can, it'll be required for A7xx. Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/551828/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 1ed202c4e497..0fef92f71c4e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1740,6 +1740,11 @@ static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or) return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); } +static u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) +{ + return msm_readl(a6xx_gpu->llc_mmio + (reg << 2)); +} + static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value) { msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2)); From c5597e58a56c4eb233ae2d15d06ed39fd94b2405 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 8 Aug 2023 23:02:44 +0200 Subject: [PATCH 117/118] drm/msm/a6xx: Move LLC accessors to the common header Move these wrappers in preparation for use in a6xx_gmu.c Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/551824/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 --------------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 0fef92f71c4e..6dd6d72bcd86 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1735,21 +1735,6 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu) return IRQ_HANDLED; } -static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or) -{ - return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); -} - -static u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) -{ - return msm_readl(a6xx_gpu->llc_mmio + (reg << 2)); -} - -static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value) -{ - msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2)); -} - static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu) { llcc_slice_deactivate(a6xx_gpu->llc_slice); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index ab66d281828c..34822b080759 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -62,6 +62,21 @@ static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) return true; } +static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or) +{ + return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); +} + +static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) +{ + return msm_readl(a6xx_gpu->llc_mmio + (reg << 2)); +} + +static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value) +{ + msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2)); +} + #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \ ((_ring)->id * sizeof(uint32_t))) From 34b149ecae852d13ae3275e707fce93081ef5e4a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 8 Aug 2023 23:02:45 +0200 Subject: [PATCH 118/118] drm/msm/a6xx: Bail out early if setting GPU OOB fails If the GMU can't guarantee the required resources are up, trying to bring up the GPU is a lost cause. Return early if setting GPU OOB fails. Tested-by: Neil Armstrong # on SM8550-QRD Tested-by: Dmitry Baryshkov # sm8450 Signed-off-by: Konrad Dybcio Patchwork: https://patchwork.freedesktop.org/patch/551830/ Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 6dd6d72bcd86..d4e85e24002f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1201,7 +1201,9 @@ static int hw_init(struct msm_gpu *gpu) if (!adreno_has_gmu_wrapper(adreno_gpu)) { /* Make sure the GMU keeps the GPU on while we set it up */ - a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); + if (ret) + return ret; } /* Clear GBIF halt in case GX domain was not collapsed */