Merge branch 'remotes/lorenzo/pci/dwc'
- Return error instead of success if DMA mapping of MSI area fails (Jiantao Zhang) - Drop tegra194 MSI register save/restore, which is unnecessary since the DWC core does it (Jisheng Zhang) - Factor out qcom enable/disable resources code (Dmitry Baryshkov) - Remove "snps,dw-pcie" from rockchip-dwc DT "compatible" property because it's not fully compatible with rockchip (Peter Geis) - Reset rockchip-dwc controller at probe (Peter Geis) - Add rockchip-dwc INTx support (Peter Geis) * remotes/lorenzo/pci/dwc: PCI: rockchip-dwc: Add legacy interrupt support PCI: rockchip-dwc: Reset core at driver probe dt-bindings: PCI: Remove fallback from Rockchip DesignWare binding PCI: qcom-ep: Move enable/disable resources code to common functions PCI: tegra194: Remove unnecessary MSI enable reg save and restore PCI: dwc: Fix setting error return on MSI DMA mapping failure
This commit is contained in:
Bjorn Helgaas
commit
39348d2eb2
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@ -19,20 +19,10 @@ description: |+
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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# We need a select here so we don't match all nodes with 'snps,dw-pcie'
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select:
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properties:
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compatible:
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contains:
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const: rockchip,rk3568-pcie
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required:
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- compatible
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properties:
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compatible:
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items:
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- const: rockchip,rk3568-pcie
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- const: snps,dw-pcie
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reg:
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items:
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@ -110,7 +100,7 @@ examples:
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#size-cells = <2>;
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pcie3x2: pcie@fe280000 {
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compatible = "rockchip,rk3568-pcie", "snps,dw-pcie";
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compatible = "rockchip,rk3568-pcie";
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reg = <0x3 0xc0800000 0x0 0x390000>,
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<0x0 0xfe280000 0x0 0x10000>,
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<0x3 0x80000000 0x0 0x100000>;
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@ -396,7 +396,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
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sizeof(pp->msi_msg),
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DMA_FROM_DEVICE,
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DMA_ATTR_SKIP_CPU_SYNC);
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if (dma_mapping_error(pci->dev, pp->msi_data)) {
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ret = dma_mapping_error(pci->dev, pp->msi_data);
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if (ret) {
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dev_err(pci->dev, "Failed to map MSI data\n");
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pp->msi_data = 0;
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goto err_free_msi;
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@ -10,9 +10,12 @@
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#include <linux/clk.h>
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#include <linux/gpio/consumer.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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@ -26,6 +29,7 @@
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*/
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#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
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#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
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#define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val)
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#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
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@ -36,10 +40,12 @@
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#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
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#define PCIE_L0S_ENTRY 0x11
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#define PCIE_CLIENT_GENERAL_CONTROL 0x0
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#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
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#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
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#define PCIE_CLIENT_GENERAL_DEBUG 0x104
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#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
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#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
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#define PCIE_CLIENT_LTSSM_STATUS 0x300
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#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
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#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
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#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
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struct rockchip_pcie {
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@ -51,6 +57,7 @@ struct rockchip_pcie {
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struct reset_control *rst;
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struct gpio_desc *rst_gpio;
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struct regulator *vpcie3v3;
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struct irq_domain *irq_domain;
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};
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static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip,
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@ -65,6 +72,78 @@ static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip,
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writel_relaxed(val, rockchip->apb_base + reg);
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}
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static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
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unsigned long reg, hwirq;
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chained_irq_enter(chip, desc);
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reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY);
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for_each_set_bit(hwirq, ®, 4)
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generic_handle_domain_irq(rockchip->irq_domain, hwirq);
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chained_irq_exit(chip, desc);
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}
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static void rockchip_intx_mask(struct irq_data *data)
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{
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rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
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HIWORD_UPDATE_BIT(BIT(data->hwirq)),
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PCIE_CLIENT_INTR_MASK_LEGACY);
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};
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static void rockchip_intx_unmask(struct irq_data *data)
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{
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rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
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HIWORD_DISABLE_BIT(BIT(data->hwirq)),
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PCIE_CLIENT_INTR_MASK_LEGACY);
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};
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static struct irq_chip rockchip_intx_irq_chip = {
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.name = "INTx",
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.irq_mask = rockchip_intx_mask,
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.irq_unmask = rockchip_intx_unmask,
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.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
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};
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static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops intx_domain_ops = {
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.map = rockchip_pcie_intx_map,
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};
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static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
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{
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struct device *dev = rockchip->pci.dev;
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struct device_node *intc;
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intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller");
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if (!intc) {
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dev_err(dev, "missing child interrupt-controller node\n");
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return -EINVAL;
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}
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rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
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&intx_domain_ops, rockchip);
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of_node_put(intc);
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if (!rockchip->irq_domain) {
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dev_err(dev, "failed to get a INTx IRQ domain\n");
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return -EINVAL;
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}
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return 0;
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}
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static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
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{
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rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
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@ -111,7 +190,20 @@ static int rockchip_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
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struct device *dev = rockchip->pci.dev;
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u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
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int irq, ret;
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irq = of_irq_get_byname(dev->of_node, "legacy");
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if (irq < 0)
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return irq;
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ret = rockchip_pcie_init_irq_domain(rockchip);
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if (ret < 0)
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dev_err(dev, "failed to init irq domain\n");
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irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler,
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rockchip);
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/* LTSSM enable control mode */
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rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
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@ -152,6 +244,11 @@ static int rockchip_pcie_resource_get(struct platform_device *pdev,
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if (IS_ERR(rockchip->rst_gpio))
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return PTR_ERR(rockchip->rst_gpio);
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rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev);
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if (IS_ERR(rockchip->rst))
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return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst),
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"failed to get reset lines\n");
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return 0;
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}
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@ -182,18 +279,6 @@ static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip)
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phy_power_off(rockchip->phy);
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}
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static int rockchip_pcie_reset_control_release(struct rockchip_pcie *rockchip)
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{
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struct device *dev = rockchip->pci.dev;
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rockchip->rst = devm_reset_control_array_get_exclusive(dev);
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if (IS_ERR(rockchip->rst))
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return dev_err_probe(dev, PTR_ERR(rockchip->rst),
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"failed to get reset lines\n");
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return reset_control_deassert(rockchip->rst);
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}
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static const struct dw_pcie_ops dw_pcie_ops = {
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.link_up = rockchip_pcie_link_up,
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.start_link = rockchip_pcie_start_link,
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@ -222,6 +307,10 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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ret = reset_control_assert(rockchip->rst);
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if (ret)
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return ret;
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/* DON'T MOVE ME: must be enable before PHY init */
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rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
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if (IS_ERR(rockchip->vpcie3v3)) {
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@ -241,7 +330,7 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
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if (ret)
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goto disable_regulator;
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ret = rockchip_pcie_reset_control_release(rockchip);
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ret = reset_control_deassert(rockchip->rst);
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if (ret)
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goto deinit_phy;
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|
|
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|||
|
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@ -223,11 +223,8 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)
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disable_irq(pcie_ep->perst_irq);
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}
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static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
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static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
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{
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struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
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struct device *dev = pci->dev;
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u32 val, offset;
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int ret;
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ret = clk_bulk_prepare_enable(ARRAY_SIZE(qcom_pcie_ep_clks),
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@ -247,6 +244,38 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
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if (ret)
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goto err_phy_exit;
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||||
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||||
return 0;
|
||||
|
||||
err_phy_exit:
|
||||
phy_exit(pcie_ep->phy);
|
||||
err_disable_clk:
|
||||
clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks),
|
||||
qcom_pcie_ep_clks);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep)
|
||||
{
|
||||
phy_power_off(pcie_ep->phy);
|
||||
phy_exit(pcie_ep->phy);
|
||||
clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks),
|
||||
qcom_pcie_ep_clks);
|
||||
}
|
||||
|
||||
static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
|
||||
{
|
||||
struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
|
||||
struct device *dev = pci->dev;
|
||||
u32 val, offset;
|
||||
int ret;
|
||||
|
||||
ret = qcom_pcie_enable_resources(pcie_ep);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to enable resources: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Assert WAKE# to RC to indicate device is ready */
|
||||
gpiod_set_value_cansleep(pcie_ep->wake, 1);
|
||||
usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500);
|
||||
|
|
@ -335,7 +364,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
|
|||
ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to complete initialization: %d\n", ret);
|
||||
goto err_phy_power_off;
|
||||
goto err_disable_resources;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -355,13 +384,8 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
|
|||
|
||||
return 0;
|
||||
|
||||
err_phy_power_off:
|
||||
phy_power_off(pcie_ep->phy);
|
||||
err_phy_exit:
|
||||
phy_exit(pcie_ep->phy);
|
||||
err_disable_clk:
|
||||
clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks),
|
||||
qcom_pcie_ep_clks);
|
||||
err_disable_resources:
|
||||
qcom_pcie_disable_resources(pcie_ep);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -376,10 +400,7 @@ static void qcom_pcie_perst_assert(struct dw_pcie *pci)
|
|||
return;
|
||||
}
|
||||
|
||||
phy_power_off(pcie_ep->phy);
|
||||
phy_exit(pcie_ep->phy);
|
||||
clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks),
|
||||
qcom_pcie_ep_clks);
|
||||
qcom_pcie_disable_resources(pcie_ep);
|
||||
pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;
|
||||
}
|
||||
|
||||
|
|
@ -643,43 +664,26 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_bulk_prepare_enable(ARRAY_SIZE(qcom_pcie_ep_clks),
|
||||
qcom_pcie_ep_clks);
|
||||
if (ret)
|
||||
ret = qcom_pcie_enable_resources(pcie_ep);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to enable resources: %d\n", ret);
|
||||
return ret;
|
||||
|
||||
ret = qcom_pcie_ep_core_reset(pcie_ep);
|
||||
if (ret)
|
||||
goto err_disable_clk;
|
||||
|
||||
ret = phy_init(pcie_ep->phy);
|
||||
if (ret)
|
||||
goto err_disable_clk;
|
||||
|
||||
/* PHY needs to be powered on for dw_pcie_ep_init() */
|
||||
ret = phy_power_on(pcie_ep->phy);
|
||||
if (ret)
|
||||
goto err_phy_exit;
|
||||
}
|
||||
|
||||
ret = dw_pcie_ep_init(&pcie_ep->pci.ep);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to initialize endpoint: %d\n", ret);
|
||||
goto err_phy_power_off;
|
||||
goto err_disable_resources;
|
||||
}
|
||||
|
||||
ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep);
|
||||
if (ret)
|
||||
goto err_phy_power_off;
|
||||
goto err_disable_resources;
|
||||
|
||||
return 0;
|
||||
|
||||
err_phy_power_off:
|
||||
phy_power_off(pcie_ep->phy);
|
||||
err_phy_exit:
|
||||
phy_exit(pcie_ep->phy);
|
||||
err_disable_clk:
|
||||
clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks),
|
||||
qcom_pcie_ep_clks);
|
||||
err_disable_resources:
|
||||
qcom_pcie_disable_resources(pcie_ep);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -691,10 +695,7 @@ static int qcom_pcie_ep_remove(struct platform_device *pdev)
|
|||
if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED)
|
||||
return 0;
|
||||
|
||||
phy_power_off(pcie_ep->phy);
|
||||
phy_exit(pcie_ep->phy);
|
||||
clk_bulk_disable_unprepare(ARRAY_SIZE(qcom_pcie_ep_clks),
|
||||
qcom_pcie_ep_clks);
|
||||
qcom_pcie_disable_resources(pcie_ep);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -186,8 +186,6 @@
|
|||
#define N_FTS_VAL 52
|
||||
#define FTS_VAL 52
|
||||
|
||||
#define PORT_LOGIC_MSI_CTRL_INT_0_EN 0x828
|
||||
|
||||
#define GEN3_EQ_CONTROL_OFF 0x8a8
|
||||
#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT 8
|
||||
#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
|
||||
|
|
@ -2189,9 +2187,6 @@ static int tegra194_pcie_suspend_noirq(struct device *dev)
|
|||
if (!pcie->link_state)
|
||||
return 0;
|
||||
|
||||
/* Save MSI interrupt vector */
|
||||
pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci,
|
||||
PORT_LOGIC_MSI_CTRL_INT_0_EN);
|
||||
tegra_pcie_downstream_dev_to_D0(pcie);
|
||||
tegra194_pcie_pme_turnoff(pcie);
|
||||
tegra_pcie_unconfig_controller(pcie);
|
||||
|
|
@ -2223,10 +2218,6 @@ static int tegra194_pcie_resume_noirq(struct device *dev)
|
|||
if (ret < 0)
|
||||
goto fail_host_init;
|
||||
|
||||
/* Restore MSI interrupt vector */
|
||||
dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN,
|
||||
pcie->msi_ctrl_int);
|
||||
|
||||
return 0;
|
||||
|
||||
fail_host_init:
|
||||
|
|
|
|||
Loading…
Reference in New Issue