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clk: tegra: Initialize DSI low-power clocks
The low-power DSI clocks are used during host-driven transactions on the DSI bus. Documentation recommends that they be children of PLLP and run at a frequency of at least 52 MHz. Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -1299,6 +1299,8 @@ static struct tegra_clk_init_table init_table[] __initdata = {
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{TEGRA114_CLK_DISP2, TEGRA114_CLK_PLL_P, 0, 0},
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{TEGRA114_CLK_GR2D, TEGRA114_CLK_PLL_C2, 300000000, 0},
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{TEGRA114_CLK_GR3D, TEGRA114_CLK_PLL_C2, 300000000, 0},
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{TEGRA114_CLK_DSIALP, TEGRA114_CLK_PLL_P, 68000000, 0},
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{TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0},
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/* This MUST be the last entry. */
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{TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0},
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