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net/mlx5: Fix typo in comments
Fix typo: *vectores ==> vectors *realeased ==> released *erros ==> errors *namepsace ==> namespace *trafic ==> traffic *proccessed ==> processed *retore ==> restore *Currenlty ==> Currently *crated ==> created *chane ==> change *cannnot ==> cannot *usuallly ==> usually *failes ==> fails *importent ==> important *reenabled ==> re-enabled *alocation ==> allocation *recived ==> received *tanslation ==> translation Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
Cai Huoqing
Saeed Mahameed
parent
88be326349
commit
39c538d644
16 changed files with 19 additions and 19 deletions
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@ -520,7 +520,7 @@ int mlx5e_tc_tun_create_header_ipv6(struct mlx5e_priv *priv,
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e->out_dev = attr.out_dev;
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e->route_dev_ifindex = attr.route_dev->ifindex;
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/* It's importent to add the neigh to the hash table before checking
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/* It's important to add the neigh to the hash table before checking
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* the neigh validity state. So if we'll get a notification, in case the
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* neigh changes it's validity state, we would find the relevant neigh
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* in the hash.
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@ -126,7 +126,7 @@ int mlx5e_open_xsk(struct mlx5e_priv *priv, struct mlx5e_params *params,
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/* Create a separate SQ, so that when the buff pool is disabled, we could
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* close this SQ safely and stop receiving CQEs. In other case, e.g., if
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* the XDPSQ was used instead, we might run into trouble when the buff pool
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* is disabled and then reenabled, but the SQ continues receiving CQEs
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* is disabled and then re-enabled, but the SQ continues receiving CQEs
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* from the old buff pool.
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*/
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err = mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, pool, &c->xsksq, true);
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@ -33,7 +33,7 @@
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#include "en.h"
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/* mlx5e global resources should be placed in this file.
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* Global resources are common to all the netdevices crated on the same nic.
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* Global resources are common to all the netdevices created on the same nic.
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*/
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void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc)
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@ -146,7 +146,7 @@ struct mlx5e_neigh_hash_entry {
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*/
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refcount_t refcnt;
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/* Save the last reported time offloaded trafic pass over one of the
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/* Save the last reported time offloaded traffic pass over one of the
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* neigh hash entry flows. Use it to periodically update the neigh
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* 'used' value and avoid neigh deleting by the kernel.
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*/
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@ -97,7 +97,7 @@ struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
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[MARK_TO_REG] = mark_to_reg_ct,
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[LABELS_TO_REG] = labels_to_reg_ct,
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[FTEID_TO_REG] = fteid_to_reg_ct,
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/* For NIC rules we store the retore metadata directly
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/* For NIC rules we store the restore metadata directly
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* into reg_b that is passed to SW since we don't
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* jump between steering domains.
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*/
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@ -2448,7 +2448,7 @@ static int __parse_cls_flower(struct mlx5e_priv *priv,
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spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
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}
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}
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/* Currenlty supported only for MPLS over UDP */
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/* Currently supported only for MPLS over UDP */
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if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
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!netif_is_bareudp(filter_dev)) {
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NL_SET_ERR_MSG_MOD(extack,
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@ -1492,7 +1492,7 @@ int mlx5_eswitch_enable_locked(struct mlx5_eswitch *esw, int mode, int num_vfs)
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/**
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* mlx5_eswitch_enable - Enable eswitch
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* @esw: Pointer to eswitch
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* @num_vfs: Enable eswitch swich for given number of VFs.
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* @num_vfs: Enable eswitch switch for given number of VFs.
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* Caller must pass num_vfs > 0 when enabling eswitch for
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* vf vports.
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* mlx5_eswitch_enable() returns 0 on success or error code on failure.
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@ -27,7 +27,7 @@ static int pcie_core(struct notifier_block *, unsigned long, void *);
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static int forward_event(struct notifier_block *, unsigned long, void *);
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static struct mlx5_nb events_nbs_ref[] = {
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/* Events to be proccessed by mlx5_core */
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/* Events to be processed by mlx5_core */
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{.nb.notifier_call = any_notifier, .event_type = MLX5_EVENT_TYPE_NOTIFY_ANY },
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{.nb.notifier_call = temp_warn, .event_type = MLX5_EVENT_TYPE_TEMP_WARN_EVENT },
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{.nb.notifier_call = port_module, .event_type = MLX5_EVENT_TYPE_PORT_MODULE_EVENT },
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@ -1516,7 +1516,7 @@ static int mlx5_fpga_esp_modify_xfrm(struct mlx5_accel_esp_xfrm *xfrm,
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mutex_lock(&fpga_xfrm->lock);
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if (!fpga_xfrm->sa_ctx)
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/* Unbounded xfrm, chane only sw attrs */
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/* Unbounded xfrm, change only sw attrs */
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goto change_sw_xfrm_attrs;
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/* copy original hw sa */
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@ -2493,7 +2493,7 @@ static void set_prio_attrs_in_prio(struct fs_prio *prio, int acc_level)
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acc_level_ns = set_prio_attrs_in_ns(ns, acc_level);
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/* If this a prio with chains, and we can jump from one chain
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* (namepsace) to another, so we accumulate the levels
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* (namespace) to another, so we accumulate the levels
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*/
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if (prio->node.type == FS_TYPE_PRIO_CHAINS)
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acc_level = acc_level_ns;
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@ -170,7 +170,7 @@ static bool reset_fw_if_needed(struct mlx5_core_dev *dev)
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/* The reset only needs to be issued by one PF. The health buffer is
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* shared between all functions, and will be cleared during a reset.
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* Check again to avoid a redundant 2nd reset. If the fatal erros was
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* Check again to avoid a redundant 2nd reset. If the fatal errors was
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* PCI related a reset won't help.
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*/
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fatal_error = mlx5_health_check_fatal_sensors(dev);
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@ -749,7 +749,7 @@ static int mlx5_pps_event(struct notifier_block *nb,
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} else {
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ptp_event.type = PTP_CLOCK_EXTTS;
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}
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/* TODOL clock->ptp can be NULL if ptp_clock_register failes */
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/* TODOL clock->ptp can be NULL if ptp_clock_register fails */
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ptp_clock_event(clock->ptp, &ptp_event);
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break;
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case PTP_PF_PEROUT:
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@ -40,7 +40,7 @@
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struct mlx5_vxlan {
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struct mlx5_core_dev *mdev;
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/* max_num_ports is usuallly 4, 16 buckets is more than enough */
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/* max_num_ports is usually 4, 16 buckets is more than enough */
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DECLARE_HASHTABLE(htable, 4);
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struct mutex sync_lock; /* sync add/del port HW operations */
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};
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@ -18,7 +18,7 @@
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#define MLX5_SFS_PER_CTRL_IRQ 64
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#define MLX5_IRQ_CTRL_SF_MAX 8
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/* min num of vectores for SFs to be enabled */
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/* min num of vectors for SFs to be enabled */
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#define MLX5_IRQ_VEC_COMP_BASE_SF 2
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#define MLX5_EQ_SHARE_IRQ_MAX_COMP (8)
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@ -597,7 +597,7 @@ void mlx5_irq_table_destroy(struct mlx5_core_dev *dev)
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return;
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/* There are cases where IRQs still will be in used when we reaching
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* to here. Hence, making sure all the irqs are realeased.
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* to here. Hence, making sure all the irqs are released.
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*/
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irq_pools_destroy(table);
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pci_free_irq_vectors(dev->pdev);
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@ -476,7 +476,7 @@ static void mlx5_sf_table_disable(struct mlx5_sf_table *table)
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return;
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/* Balances with refcount_set; drop the reference so that new user cmd cannot start
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* and new vhca event handler cannnot run.
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* and new vhca event handler cannot run.
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*/
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mlx5_sf_table_put(table);
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wait_for_completion(&table->disable_complete);
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@ -1038,7 +1038,7 @@ enum {
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struct mlx5_mkey_seg {
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/* This is a two bit field occupying bits 31-30.
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* bit 31 is always 0,
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* bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
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* bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have translation
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*/
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u8 status;
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u8 pcie_control;
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@ -581,7 +581,7 @@ struct mlx5_priv {
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/* end: qp staff */
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/* start: alloc staff */
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/* protect buffer alocation according to numa node */
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/* protect buffer allocation according to numa node */
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struct mutex alloc_mutex;
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int numa_node;
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@ -1111,7 +1111,7 @@ static inline u8 mlx5_mkey_variant(u32 mkey)
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}
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/* Async-atomic event notifier used by mlx5 core to forward FW
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* evetns recived from event queue to mlx5 consumers.
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* evetns received from event queue to mlx5 consumers.
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* Optimise event queue dipatching.
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*/
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int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
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