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mvebu SoC changes for v3.17 (round 4)
- Armada XP
- Fix return value check in pmsu code
- Document URLs for new public datasheets (Thanks, Marvell & free-electrons!)
- Armada 370/38x
- Add cpuidle support
- mvebu
- Fix build when no platforms are selected
- Update EBU SoC status in docs
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Merge tag 'mvebu-soc-3.17-4' of git://git.infradead.org/linux-mvebu into next/soc
Merge "mvebu SoC changes for v3.17 (round 4)" from Jason Cooper:
- Armada XP
- Fix return value check in pmsu code
- Document URLs for new public datasheets (Thanks, Marvell & free-electrons!)
- Armada 370/38x
- Add cpuidle support
- mvebu
- Fix build when no platforms are selected
- Update EBU SoC status in docs
* tag 'mvebu-soc-3.17-4' of git://git.infradead.org/linux-mvebu: (21 commits)
Documentation: arm: misc updates to Marvell EBU SoC status
Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
ARM: mvebu: fix build without platforms selected
ARM: mvebu: add cpuidle support for Armada 38x
ARM: mvebu: add cpuidle support for Armada 370
cpuidle: mvebu: add Armada 38x support
cpuidle: mvebu: add Armada 370 support
cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
ARM: mvebu: export the SCU address
ARM: mvebu: make the snoop disabling optional in mvebu_v7_pmsu_idle_prepare()
ARM: mvebu: use a local variable to store the resume address
ARM: mvebu: make the cpuidle initialization more generic
ARM: mvebu: rename the armada_370_xp symbols to mvebu_v7 in pmsu.c
ARM: mvebu: use the common function for Armada 375 SMP workaround
ARM: mvebu: add a common function for the boot address work around
ARM: mvebu: sort the #include of pmsu.c in alphabetic order
ARM: mvebu: split again armada_370_xp_pmsu_idle_enter() in PMSU code
ARM: mvebu: fix return value check in armada_xp_pmsu_cpufreq_init()
clk: mvebu: extend clk-cpu for dynamic frequency scaling
ARM: mvebu: extend PMSU code to support dynamic frequency scaling
...
Conflicts:
arch/arm/mach-mvebu/Kconfig
drivers/cpuidle/cpuidle-armada-370-xp.c
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
39fbf98408
20 changed files with 761 additions and 215 deletions
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@ -53,8 +53,8 @@ Kirkwood family
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|||
Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
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Homepage: http://www.marvell.com/embedded-processors/kirkwood/
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Core: Feroceon ARMv5 compatible
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Linux kernel mach directory: arch/arm/mach-kirkwood
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Linux kernel plat directory: arch/arm/plat-orion
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Linux kernel mach directory: arch/arm/mach-mvebu
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Linux kernel plat directory: none
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Discovery family
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----------------
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@ -102,8 +102,7 @@ EBU Armada family
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MV78460
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NOTE: not to be confused with the non-SMP 78xx0 SoCs
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Product Brief: http://www.marvell.com/embedded-processors/armada-xp/assets/Marvell-ArmadaXP-SoC-product%20brief.pdf
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No public datasheet available.
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Functional Spec: http://www.marvell.com/embedded-processors/armada-xp/assets/ARMADA-XP-Functional-SpecDatasheet.pdf
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Core: Sheeva ARMv7 compatible
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@ -137,7 +136,9 @@ Dove family (application processor)
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Functional Spec : http://www.marvell.com/application-processors/armada-500/assets/Armada-510-Functional-Spec.pdf
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Homepage: http://www.marvell.com/application-processors/armada-500/
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Core: ARMv7 compatible
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Directory: arch/arm/mach-dove
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Directory: arch/arm/mach-mvebu (DT enabled platforms)
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arch/arm/mach-dove (non-DT enabled platforms)
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PXA 2xx/3xx/93x/95x family
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--------------------------
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@ -255,10 +256,10 @@ Berlin family (Digital Entertainment)
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Long-term plans
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---------------
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* Unify the mach-dove/, mach-mv78xx0/, mach-orion5x/ and
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mach-kirkwood/ into the mach-mvebu/ to support all SoCs from the
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Marvell EBU (Engineering Business Unit) in a single mach-<foo>
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directory. The plat-orion/ would therefore disappear.
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* Unify the mach-dove/, mach-mv78xx0/, mach-orion5x/ into the
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mach-mvebu/ to support all SoCs from the Marvell EBU (Engineering
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Business Unit) in a single mach-<foo> directory. The plat-orion/
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would therefore disappear.
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* Unify the mach-mmp/ and mach-pxa/ into the same mach-pxa
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directory. The plat-pxa/ would therefore disappear.
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@ -3,14 +3,15 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
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Required properties:
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- compatible : shall be one of the following:
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"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
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- reg : Address and length of the clock complex register set
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- reg : Address and length of the clock complex register set, followed
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by address and length of the PMU DFS registers
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- #clock-cells : should be set to 1.
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- clocks : shall be the input parent clock phandle for the clock.
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cpuclk: clock-complex@d0018700 {
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#clock-cells = <1>;
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compatible = "marvell,armada-xp-cpu-clock";
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reg = <0xd0018700 0xA0>;
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reg = <0xd0018700 0xA0>, <0x1c054 0x10>;
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clocks = <&coreclk 1>;
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}
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@ -14,11 +14,15 @@ menuconfig ARCH_MVEBU
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if ARCH_MVEBU
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config MACH_MVEBU_ANY
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bool
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config MACH_MVEBU_V7
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bool
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select ARMADA_370_XP_TIMER
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select CACHE_L2X0
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select ARM_CPU_SUSPEND
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select MACH_MVEBU_ANY
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config MACH_ARMADA_370
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bool "Marvell Armada 370 boards" if ARCH_MULTI_V7
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@ -75,6 +79,7 @@ config MACH_DOVE
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select CACHE_L2X0
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select CPU_PJ4
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select DOVE_CLK
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select MACH_MVEBU_ANY
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select ORION_IRQCHIP
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select ORION_TIMER
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select PINCTRL_DOVE
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@ -87,6 +92,7 @@ config MACH_KIRKWOOD
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select ARCH_REQUIRE_GPIOLIB
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select CPU_FEROCEON
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select KIRKWOOD_CLK
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select MACH_MVEBU_ANY
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select ORION_IRQCHIP
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select ORION_TIMER
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select PCI
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|
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@ -4,7 +4,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
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AFLAGS_coherency_ll.o := -Wa,-march=armv7-a
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CFLAGS_pmsu.o := -march=armv7-a
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obj-y += system-controller.o mvebu-soc-id.o
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obj-$(CONFIG_MACH_MVEBU_ANY) += system-controller.o mvebu-soc-id.o
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ifeq ($(CONFIG_MACH_MVEBU_V7),y)
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obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o
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@ -25,6 +25,5 @@ extern struct smp_operations armada_xp_smp_ops;
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#endif
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int armada_370_xp_pmsu_idle_enter(unsigned long deepidle);
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void armada_370_xp_pmsu_idle_exit(void);
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#endif /* __MACH_ARMADA_370_XP_H */
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@ -34,14 +34,14 @@
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#include "coherency.h"
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#include "mvebu-soc-id.h"
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static void __iomem *scu_base;
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/*
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* Enables the SCU when available. Obviously, this is only useful on
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* Cortex-A based SOCs, not on PJ4B based ones.
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*/
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static void __init mvebu_scu_enable(void)
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{
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void __iomem *scu_base;
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struct device_node *np =
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of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (np) {
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@ -51,6 +51,11 @@ static void __init mvebu_scu_enable(void)
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}
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}
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void __iomem *mvebu_get_scu_base(void)
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{
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return scu_base;
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}
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/*
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* Early versions of Armada 375 SoC have a bug where the BootROM
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* leaves an external data abort pending. The kernel is hit by this
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@ -23,4 +23,6 @@ void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr);
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void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr);
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int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev);
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void __iomem *mvebu_get_scu_base(void);
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#endif
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@ -18,21 +18,6 @@
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#include <asm/assembler.h>
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__CPUINIT
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#define CPU_RESUME_ADDR_REG 0xf10182d4
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.global armada_375_smp_cpu1_enable_code_start
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.global armada_375_smp_cpu1_enable_code_end
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armada_375_smp_cpu1_enable_code_start:
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ARM_BE8(setend be)
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adr r0, 1f
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ldr r0, [r0]
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ldr r1, [r0]
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ARM_BE8(rev r1, r1)
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mov pc, r1
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1:
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.word CPU_RESUME_ADDR_REG
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armada_375_smp_cpu1_enable_code_end:
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ENTRY(mvebu_cortex_a9_secondary_startup)
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ARM_BE8(setend be)
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@ -20,33 +20,8 @@
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#include <asm/smp_scu.h>
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#include <asm/smp_plat.h>
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#include "common.h"
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#include "mvebu-soc-id.h"
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#include "pmsu.h"
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#define CRYPT0_ENG_ID 41
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#define CRYPT0_ENG_ATTR 0x1
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#define SRAM_PHYS_BASE 0xFFFF0000
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#define BOOTROM_BASE 0xFFF00000
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#define BOOTROM_SIZE 0x100000
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extern unsigned char armada_375_smp_cpu1_enable_code_end;
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extern unsigned char armada_375_smp_cpu1_enable_code_start;
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static void armada_375_smp_cpu1_enable_wa(void)
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{
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void __iomem *sram_virt_base;
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mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
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mvebu_mbus_add_window_by_id(CRYPT0_ENG_ID, CRYPT0_ENG_ATTR,
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SRAM_PHYS_BASE, SZ_64K);
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sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
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memcpy(sram_virt_base, &armada_375_smp_cpu1_enable_code_start,
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&armada_375_smp_cpu1_enable_code_end
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- &armada_375_smp_cpu1_enable_code_start);
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}
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extern void mvebu_cortex_a9_secondary_startup(void);
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static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
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@ -63,21 +38,10 @@ static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
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* address.
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*/
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hw_cpu = cpu_logical_map(cpu);
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if (of_machine_is_compatible("marvell,armada375")) {
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u32 dev, rev;
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if (mvebu_get_soc_id(&dev, &rev) == 0 &&
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rev == ARMADA_375_Z1_REV)
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armada_375_smp_cpu1_enable_wa();
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if (of_machine_is_compatible("marvell,armada375"))
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mvebu_system_controller_set_cpu_boot_addr(mvebu_cortex_a9_secondary_startup);
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}
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else {
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mvebu_pmsu_set_cpu_boot_addr(hw_cpu,
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mvebu_cortex_a9_secondary_startup);
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}
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else
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mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cortex_a9_secondary_startup);
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smp_wmb();
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ret = mvebu_cpu_reset_deassert(hw_cpu);
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if (ret) {
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|
|
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|
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@ -67,6 +67,7 @@ static void __init set_secondary_cpus_clock(void)
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if (!cpu_clk)
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return;
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clk_set_rate(cpu_clk, rate);
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clk_prepare_enable(cpu_clk);
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}
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}
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@ -108,7 +109,7 @@ static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
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*/
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static void armada_xp_secondary_init(unsigned int cpu)
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{
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armada_370_xp_pmsu_idle_exit();
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mvebu_v7_pmsu_idle_exit();
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}
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static void __init armada_xp_smp_init_cpus(void)
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|
|
|
|||
|
|
@ -18,22 +18,29 @@
|
|||
|
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#define pr_fmt(fmt) "mvebu-pmsu: " fmt
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|
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#include <linux/clk.h>
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#include <linux/cpu_pm.h>
|
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#include <linux/kernel.h>
|
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#include <linux/delay.h>
|
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#include <linux/init.h>
|
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#include <linux/of_address.h>
|
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#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
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#include <linux/mbus.h>
|
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#include <linux/of_address.h>
|
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#include <linux/of_device.h>
|
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#include <linux/platform_device.h>
|
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#include <linux/smp.h>
|
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#include <linux/pm_opp.h>
|
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#include <linux/resource.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/smp.h>
|
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#include <asm/cacheflush.h>
|
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#include <asm/cp15.h>
|
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#include <asm/smp_scu.h>
|
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#include <asm/smp_plat.h>
|
||||
#include <asm/suspend.h>
|
||||
#include <asm/tlbflush.h>
|
||||
#include "common.h"
|
||||
#include "armada-370-xp.h"
|
||||
|
||||
static void __iomem *pmsu_mp_base;
|
||||
|
||||
#define PMSU_BASE_OFFSET 0x100
|
||||
#define PMSU_REG_SIZE 0x1000
|
||||
|
|
@ -57,20 +64,45 @@ static void __iomem *pmsu_mp_base;
|
|||
#define PMSU_STATUS_AND_MASK_IRQ_MASK BIT(24)
|
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#define PMSU_STATUS_AND_MASK_FIQ_MASK BIT(25)
|
||||
|
||||
#define PMSU_EVENT_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x120)
|
||||
#define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE BIT(1)
|
||||
#define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK BIT(17)
|
||||
|
||||
#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
|
||||
|
||||
/* PMSU fabric registers */
|
||||
#define L2C_NFABRIC_PM_CTL 0x4
|
||||
#define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20)
|
||||
|
||||
/* PMSU delay registers */
|
||||
#define PMSU_POWERDOWN_DELAY 0xF04
|
||||
#define PMSU_POWERDOWN_DELAY_PMU BIT(1)
|
||||
#define PMSU_POWERDOWN_DELAY_MASK 0xFFFE
|
||||
#define PMSU_DFLT_ARMADA38X_DELAY 0x64
|
||||
|
||||
/* CA9 MPcore SoC Control registers */
|
||||
|
||||
#define MPCORE_RESET_CTL 0x64
|
||||
#define MPCORE_RESET_CTL_L2 BIT(0)
|
||||
#define MPCORE_RESET_CTL_DEBUG BIT(16)
|
||||
|
||||
#define SRAM_PHYS_BASE 0xFFFF0000
|
||||
#define BOOTROM_BASE 0xFFF00000
|
||||
#define BOOTROM_SIZE 0x100000
|
||||
|
||||
#define ARMADA_370_CRYPT0_ENG_TARGET 0x9
|
||||
#define ARMADA_370_CRYPT0_ENG_ATTR 0x1
|
||||
|
||||
extern void ll_disable_coherency(void);
|
||||
extern void ll_enable_coherency(void);
|
||||
|
||||
extern void armada_370_xp_cpu_resume(void);
|
||||
extern void armada_38x_cpu_resume(void);
|
||||
|
||||
static struct platform_device armada_xp_cpuidle_device = {
|
||||
.name = "cpuidle-armada-370-xp",
|
||||
};
|
||||
static phys_addr_t pmsu_mp_phys_base;
|
||||
static void __iomem *pmsu_mp_base;
|
||||
|
||||
static void *mvebu_cpu_resume;
|
||||
|
||||
static struct of_device_id of_pmsu_table[] = {
|
||||
{ .compatible = "marvell,armada-370-pmsu", },
|
||||
|
|
@ -85,7 +117,49 @@ void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
|
|||
PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
|
||||
}
|
||||
|
||||
static int __init armada_370_xp_pmsu_init(void)
|
||||
extern unsigned char mvebu_boot_wa_start;
|
||||
extern unsigned char mvebu_boot_wa_end;
|
||||
|
||||
/*
|
||||
* This function sets up the boot address workaround needed for SMP
|
||||
* boot on Armada 375 Z1 and cpuidle on Armada 370. It unmaps the
|
||||
* BootROM Mbus window, and instead remaps a crypto SRAM into which a
|
||||
* custom piece of code is copied to replace the problematic BootROM.
|
||||
*/
|
||||
int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
|
||||
unsigned int crypto_eng_attribute,
|
||||
phys_addr_t resume_addr_reg)
|
||||
{
|
||||
void __iomem *sram_virt_base;
|
||||
u32 code_len = &mvebu_boot_wa_end - &mvebu_boot_wa_start;
|
||||
|
||||
mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
|
||||
mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute,
|
||||
SRAM_PHYS_BASE, SZ_64K);
|
||||
|
||||
sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
|
||||
if (!sram_virt_base) {
|
||||
pr_err("Unable to map SRAM to setup the boot address WA\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
memcpy(sram_virt_base, &mvebu_boot_wa_start, code_len);
|
||||
|
||||
/*
|
||||
* The last word of the code copied in SRAM must contain the
|
||||
* physical base address of the PMSU register. We
|
||||
* intentionally store this address in the native endianness
|
||||
* of the system.
|
||||
*/
|
||||
__raw_writel((unsigned long)resume_addr_reg,
|
||||
sram_virt_base + code_len - 4);
|
||||
|
||||
iounmap(sram_virt_base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init mvebu_v7_pmsu_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct resource res;
|
||||
|
|
@ -116,6 +190,8 @@ static int __init armada_370_xp_pmsu_init(void)
|
|||
goto out;
|
||||
}
|
||||
|
||||
pmsu_mp_phys_base = res.start;
|
||||
|
||||
pmsu_mp_base = ioremap(res.start, resource_size(&res));
|
||||
if (!pmsu_mp_base) {
|
||||
pr_err("unable to map registers\n");
|
||||
|
|
@ -129,7 +205,7 @@ static int __init armada_370_xp_pmsu_init(void)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
|
||||
static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
|
|
@ -142,8 +218,14 @@ static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
|
|||
writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
|
||||
}
|
||||
|
||||
enum pmsu_idle_prepare_flags {
|
||||
PMSU_PREPARE_NORMAL = 0,
|
||||
PMSU_PREPARE_DEEP_IDLE = BIT(0),
|
||||
PMSU_PREPARE_SNOOP_DISABLE = BIT(1),
|
||||
};
|
||||
|
||||
/* No locking is needed because we only access per-CPU registers */
|
||||
int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
|
||||
static int mvebu_v7_pmsu_idle_prepare(unsigned long flags)
|
||||
{
|
||||
unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
|
||||
u32 reg;
|
||||
|
|
@ -167,17 +249,34 @@ int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
|
|||
|
||||
reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
|
||||
/* ask HW to power down the L2 Cache if needed */
|
||||
if (deepidle)
|
||||
if (flags & PMSU_PREPARE_DEEP_IDLE)
|
||||
reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
|
||||
|
||||
/* request power down */
|
||||
reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
|
||||
writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
|
||||
|
||||
/* Disable snoop disable by HW - SW is taking care of it */
|
||||
reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
|
||||
reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
|
||||
writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
|
||||
if (flags & PMSU_PREPARE_SNOOP_DISABLE) {
|
||||
/* Disable snoop disable by HW - SW is taking care of it */
|
||||
reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
|
||||
reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
|
||||
writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
|
||||
{
|
||||
unsigned long flags = PMSU_PREPARE_SNOOP_DISABLE;
|
||||
int ret;
|
||||
|
||||
if (deepidle)
|
||||
flags |= PMSU_PREPARE_DEEP_IDLE;
|
||||
|
||||
ret = mvebu_v7_pmsu_idle_prepare(flags);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
v7_exit_coherency_flush(all);
|
||||
|
||||
|
|
@ -203,7 +302,7 @@ int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
|
|||
"isb "
|
||||
: : : "r0");
|
||||
|
||||
pr_warn("Failed to suspend the system\n");
|
||||
pr_debug("Failed to suspend the system\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -213,15 +312,40 @@ static int armada_370_xp_cpu_suspend(unsigned long deepidle)
|
|||
return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
|
||||
}
|
||||
|
||||
static int armada_38x_do_cpu_suspend(unsigned long deepidle)
|
||||
{
|
||||
unsigned long flags = 0;
|
||||
|
||||
if (deepidle)
|
||||
flags |= PMSU_PREPARE_DEEP_IDLE;
|
||||
|
||||
mvebu_v7_pmsu_idle_prepare(flags);
|
||||
/*
|
||||
* Already flushed cache, but do it again as the outer cache
|
||||
* functions dirty the cache with spinlocks
|
||||
*/
|
||||
v7_exit_coherency_flush(louis);
|
||||
|
||||
scu_power_mode(mvebu_get_scu_base(), SCU_PM_POWEROFF);
|
||||
|
||||
cpu_do_idle();
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int armada_38x_cpu_suspend(unsigned long deepidle)
|
||||
{
|
||||
return cpu_suspend(false, armada_38x_do_cpu_suspend);
|
||||
}
|
||||
|
||||
/* No locking is needed because we only access per-CPU registers */
|
||||
void armada_370_xp_pmsu_idle_exit(void)
|
||||
void mvebu_v7_pmsu_idle_exit(void)
|
||||
{
|
||||
unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
|
||||
u32 reg;
|
||||
|
||||
if (pmsu_mp_base == NULL)
|
||||
return;
|
||||
|
||||
/* cancel ask HW to power down the L2 Cache if possible */
|
||||
reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
|
||||
reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
|
||||
|
|
@ -236,53 +360,292 @@ void armada_370_xp_pmsu_idle_exit(void)
|
|||
writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
|
||||
}
|
||||
|
||||
static int armada_370_xp_cpu_pm_notify(struct notifier_block *self,
|
||||
static int mvebu_v7_cpu_pm_notify(struct notifier_block *self,
|
||||
unsigned long action, void *hcpu)
|
||||
{
|
||||
if (action == CPU_PM_ENTER) {
|
||||
unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
|
||||
mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume);
|
||||
mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cpu_resume);
|
||||
} else if (action == CPU_PM_EXIT) {
|
||||
armada_370_xp_pmsu_idle_exit();
|
||||
mvebu_v7_pmsu_idle_exit();
|
||||
}
|
||||
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
static struct notifier_block armada_370_xp_cpu_pm_notifier = {
|
||||
.notifier_call = armada_370_xp_cpu_pm_notify,
|
||||
static struct notifier_block mvebu_v7_cpu_pm_notifier = {
|
||||
.notifier_call = mvebu_v7_cpu_pm_notify,
|
||||
};
|
||||
|
||||
static int __init armada_370_xp_cpu_pm_init(void)
|
||||
static struct platform_device mvebu_v7_cpuidle_device;
|
||||
|
||||
static __init int armada_370_cpuidle_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
/*
|
||||
* Check that all the requirements are available to enable
|
||||
* cpuidle. So far, it is only supported on Armada XP, cpuidle
|
||||
* needs the coherency fabric and the PMSU enabled
|
||||
*/
|
||||
|
||||
if (!of_machine_is_compatible("marvell,armadaxp"))
|
||||
return 0;
|
||||
phys_addr_t redirect_reg;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
|
||||
if (!np)
|
||||
return 0;
|
||||
return -ENODEV;
|
||||
of_node_put(np);
|
||||
|
||||
/*
|
||||
* On Armada 370, there is "a slow exit process from the deep
|
||||
* idle state due to heavy L1/L2 cache cleanup operations
|
||||
* performed by the BootROM software". To avoid this, we
|
||||
* replace the restart code of the bootrom by a a simple jump
|
||||
* to the boot address. Then the code located at this boot
|
||||
* address will take care of the initialization.
|
||||
*/
|
||||
redirect_reg = pmsu_mp_phys_base + PMSU_BOOT_ADDR_REDIRECT_OFFSET(0);
|
||||
mvebu_setup_boot_addr_wa(ARMADA_370_CRYPT0_ENG_TARGET,
|
||||
ARMADA_370_CRYPT0_ENG_ATTR,
|
||||
redirect_reg);
|
||||
|
||||
mvebu_cpu_resume = armada_370_xp_cpu_resume;
|
||||
mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
|
||||
mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __init int armada_38x_cpuidle_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
void __iomem *mpsoc_base;
|
||||
u32 reg;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL,
|
||||
"marvell,armada-380-coherency-fabric");
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
of_node_put(np);
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL,
|
||||
"marvell,armada-380-mpcore-soc-ctrl");
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
mpsoc_base = of_iomap(np, 0);
|
||||
BUG_ON(!mpsoc_base);
|
||||
of_node_put(np);
|
||||
|
||||
/* Set up reset mask when powering down the cpus */
|
||||
reg = readl(mpsoc_base + MPCORE_RESET_CTL);
|
||||
reg |= MPCORE_RESET_CTL_L2;
|
||||
reg |= MPCORE_RESET_CTL_DEBUG;
|
||||
writel(reg, mpsoc_base + MPCORE_RESET_CTL);
|
||||
iounmap(mpsoc_base);
|
||||
|
||||
/* Set up delay */
|
||||
reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY);
|
||||
reg &= ~PMSU_POWERDOWN_DELAY_MASK;
|
||||
reg |= PMSU_DFLT_ARMADA38X_DELAY;
|
||||
reg |= PMSU_POWERDOWN_DELAY_PMU;
|
||||
writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY);
|
||||
|
||||
mvebu_cpu_resume = armada_38x_cpu_resume;
|
||||
mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
|
||||
mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __init int armada_xp_cpuidle_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
|
||||
if (!np)
|
||||
return -ENODEV;
|
||||
of_node_put(np);
|
||||
|
||||
mvebu_cpu_resume = armada_370_xp_cpu_resume;
|
||||
mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
|
||||
mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init mvebu_v7_cpu_pm_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
int ret;
|
||||
|
||||
np = of_find_matching_node(NULL, of_pmsu_table);
|
||||
if (!np)
|
||||
return 0;
|
||||
of_node_put(np);
|
||||
|
||||
armada_370_xp_pmsu_enable_l2_powerdown_onidle();
|
||||
armada_xp_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
|
||||
platform_device_register(&armada_xp_cpuidle_device);
|
||||
cpu_pm_register_notifier(&armada_370_xp_cpu_pm_notifier);
|
||||
if (of_machine_is_compatible("marvell,armadaxp"))
|
||||
ret = armada_xp_cpuidle_init();
|
||||
else if (of_machine_is_compatible("marvell,armada370"))
|
||||
ret = armada_370_cpuidle_init();
|
||||
else if (of_machine_is_compatible("marvell,armada380"))
|
||||
ret = armada_38x_cpuidle_init();
|
||||
else
|
||||
return 0;
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mvebu_v7_pmsu_enable_l2_powerdown_onidle();
|
||||
platform_device_register(&mvebu_v7_cpuidle_device);
|
||||
cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(armada_370_xp_cpu_pm_init);
|
||||
early_initcall(armada_370_xp_pmsu_init);
|
||||
arch_initcall(mvebu_v7_cpu_pm_init);
|
||||
early_initcall(mvebu_v7_pmsu_init);
|
||||
|
||||
static void mvebu_pmsu_dfs_request_local(void *data)
|
||||
{
|
||||
u32 reg;
|
||||
u32 cpu = smp_processor_id();
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
/* Prepare to enter idle */
|
||||
reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
|
||||
reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |
|
||||
PMSU_STATUS_AND_MASK_IRQ_MASK |
|
||||
PMSU_STATUS_AND_MASK_FIQ_MASK;
|
||||
writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
|
||||
|
||||
/* Request the DFS transition */
|
||||
reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
|
||||
reg |= PMSU_CONTROL_AND_CONFIG_DFS_REQ;
|
||||
writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
|
||||
|
||||
/* The fact of entering idle will trigger the DFS transition */
|
||||
wfi();
|
||||
|
||||
/*
|
||||
* We're back from idle, the DFS transition has completed,
|
||||
* clear the idle wait indication.
|
||||
*/
|
||||
reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
|
||||
reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
|
||||
writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
|
||||
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
int mvebu_pmsu_dfs_request(int cpu)
|
||||
{
|
||||
unsigned long timeout;
|
||||
int hwcpu = cpu_logical_map(cpu);
|
||||
u32 reg;
|
||||
|
||||
/* Clear any previous DFS DONE event */
|
||||
reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
|
||||
reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE;
|
||||
writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
|
||||
|
||||
/* Mask the DFS done interrupt, since we are going to poll */
|
||||
reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
|
||||
reg |= PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
|
||||
writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
|
||||
|
||||
/* Trigger the DFS on the appropriate CPU */
|
||||
smp_call_function_single(cpu, mvebu_pmsu_dfs_request_local,
|
||||
NULL, false);
|
||||
|
||||
/* Poll until the DFS done event is generated */
|
||||
timeout = jiffies + HZ;
|
||||
while (time_before(jiffies, timeout)) {
|
||||
reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
|
||||
if (reg & PMSU_EVENT_STATUS_AND_MASK_DFS_DONE)
|
||||
break;
|
||||
udelay(10);
|
||||
}
|
||||
|
||||
if (time_after(jiffies, timeout))
|
||||
return -ETIME;
|
||||
|
||||
/* Restore the DFS mask to its original state */
|
||||
reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
|
||||
reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
|
||||
writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init armada_xp_pmsu_cpufreq_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct resource res;
|
||||
int ret, cpu;
|
||||
|
||||
if (!of_machine_is_compatible("marvell,armadaxp"))
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* In order to have proper cpufreq handling, we need to ensure
|
||||
* that the Device Tree description of the CPU clock includes
|
||||
* the definition of the PMU DFS registers. If not, we do not
|
||||
* register the clock notifier and the cpufreq driver. This
|
||||
* piece of code is only for compatibility with old Device
|
||||
* Trees.
|
||||
*/
|
||||
np = of_find_compatible_node(NULL, NULL, "marvell,armada-xp-cpu-clock");
|
||||
if (!np)
|
||||
return 0;
|
||||
|
||||
ret = of_address_to_resource(np, 1, &res);
|
||||
if (ret) {
|
||||
pr_warn(FW_WARN "not enabling cpufreq, deprecated armada-xp-cpu-clock binding\n");
|
||||
of_node_put(np);
|
||||
return 0;
|
||||
}
|
||||
|
||||
of_node_put(np);
|
||||
|
||||
/*
|
||||
* For each CPU, this loop registers the operating points
|
||||
* supported (which are the nominal CPU frequency and half of
|
||||
* it), and registers the clock notifier that will take care
|
||||
* of doing the PMSU part of a frequency transition.
|
||||
*/
|
||||
for_each_possible_cpu(cpu) {
|
||||
struct device *cpu_dev;
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
cpu_dev = get_cpu_device(cpu);
|
||||
if (!cpu_dev) {
|
||||
pr_err("Cannot get CPU %d\n", cpu);
|
||||
continue;
|
||||
}
|
||||
|
||||
clk = clk_get(cpu_dev, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("Cannot get clock for CPU %d\n", cpu);
|
||||
return PTR_ERR(clk);
|
||||
}
|
||||
|
||||
/*
|
||||
* In case of a failure of dev_pm_opp_add(), we don't
|
||||
* bother with cleaning up the registered OPP (there's
|
||||
* no function to do so), and simply cancel the
|
||||
* registration of the cpufreq device.
|
||||
*/
|
||||
ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk), 0);
|
||||
if (ret) {
|
||||
clk_put(clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk) / 2, 0);
|
||||
if (ret) {
|
||||
clk_put(clk);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
platform_device_register_simple("cpufreq-generic", -1, NULL, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
device_initcall(armada_xp_pmsu_cpufreq_init);
|
||||
|
|
|
|||
|
|
@ -12,5 +12,10 @@
|
|||
#define __MACH_MVEBU_PMSU_H
|
||||
|
||||
int armada_xp_boot_cpu(unsigned int cpu_id, void *phys_addr);
|
||||
int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
|
||||
unsigned int crypto_eng_attribute,
|
||||
phys_addr_t resume_addr_reg);
|
||||
|
||||
void mvebu_v7_pmsu_idle_exit(void);
|
||||
|
||||
#endif /* __MACH_370_XP_PMSU_H */
|
||||
|
|
|
|||
|
|
@ -23,3 +23,39 @@ ARM_BE8(setend be ) @ go BE8 if entered LE
|
|||
b cpu_resume
|
||||
ENDPROC(armada_370_xp_cpu_resume)
|
||||
|
||||
ENTRY(armada_38x_cpu_resume)
|
||||
/* do we need it for Armada 38x*/
|
||||
ARM_BE8(setend be ) @ go BE8 if entered LE
|
||||
bl v7_invalidate_l1
|
||||
mrc p15, 4, r1, c15, c0 @ get SCU base address
|
||||
orr r1, r1, #0x8 @ SCU CPU Power Status Register
|
||||
mrc 15, 0, r0, cr0, cr0, 5 @ get the CPU ID
|
||||
and r0, r0, #15
|
||||
add r1, r1, r0
|
||||
mov r0, #0x0
|
||||
strb r0, [r1] @ switch SCU power state to Normal mode
|
||||
b cpu_resume
|
||||
ENDPROC(armada_38x_cpu_resume)
|
||||
|
||||
.global mvebu_boot_wa_start
|
||||
.global mvebu_boot_wa_end
|
||||
|
||||
/* The following code will be executed from SRAM */
|
||||
ENTRY(mvebu_boot_wa_start)
|
||||
mvebu_boot_wa_start:
|
||||
ARM_BE8(setend be)
|
||||
adr r0, 1f
|
||||
ldr r0, [r0] @ load the address of the
|
||||
@ resume register
|
||||
ldr r0, [r0] @ load the value in the
|
||||
@ resume register
|
||||
ARM_BE8(rev r0, r0) @ the value is stored LE
|
||||
mov pc, r0 @ jump to this value
|
||||
/*
|
||||
* the last word of this piece of code will be filled by the physical
|
||||
* address of the boot address register just after being copied in SRAM
|
||||
*/
|
||||
1:
|
||||
.long .
|
||||
mvebu_boot_wa_end:
|
||||
ENDPROC(mvebu_boot_wa_end)
|
||||
|
|
|
|||
|
|
@ -28,8 +28,14 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/reboot.h>
|
||||
#include "common.h"
|
||||
#include "mvebu-soc-id.h"
|
||||
#include "pmsu.h"
|
||||
|
||||
#define ARMADA_375_CRYPT0_ENG_TARGET 41
|
||||
#define ARMADA_375_CRYPT0_ENG_ATTR 1
|
||||
|
||||
static void __iomem *system_controller_base;
|
||||
static phys_addr_t system_controller_phys_base;
|
||||
|
||||
struct mvebu_system_controller {
|
||||
u32 rstoutn_mask_offset;
|
||||
|
|
@ -121,10 +127,32 @@ int mvebu_system_controller_get_soc_id(u32 *dev, u32 *rev)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
void mvebu_armada375_smp_wa_init(void)
|
||||
{
|
||||
u32 dev, rev;
|
||||
phys_addr_t resume_addr_reg;
|
||||
|
||||
if (mvebu_get_soc_id(&dev, &rev) != 0)
|
||||
return;
|
||||
|
||||
if (rev != ARMADA_375_Z1_REV)
|
||||
return;
|
||||
|
||||
resume_addr_reg = system_controller_phys_base +
|
||||
mvebu_sc->resume_boot_addr;
|
||||
mvebu_setup_boot_addr_wa(ARMADA_375_CRYPT0_ENG_TARGET,
|
||||
ARMADA_375_CRYPT0_ENG_ATTR,
|
||||
resume_addr_reg);
|
||||
}
|
||||
|
||||
void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
|
||||
{
|
||||
BUG_ON(system_controller_base == NULL);
|
||||
BUG_ON(mvebu_sc->resume_boot_addr == 0);
|
||||
|
||||
if (of_machine_is_compatible("marvell,armada375"))
|
||||
mvebu_armada375_smp_wa_init();
|
||||
|
||||
writel(virt_to_phys(boot_addr), system_controller_base +
|
||||
mvebu_sc->resume_boot_addr);
|
||||
}
|
||||
|
|
@ -138,7 +166,10 @@ static int __init mvebu_system_controller_init(void)
|
|||
np = of_find_matching_node_and_match(NULL, of_system_controller_table,
|
||||
&match);
|
||||
if (np) {
|
||||
struct resource res;
|
||||
system_controller_base = of_iomap(np, 0);
|
||||
of_address_to_resource(np, 0, &res);
|
||||
system_controller_phys_base = res.start;
|
||||
mvebu_sc = (struct mvebu_system_controller *)match->data;
|
||||
of_node_put(np);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -16,10 +16,19 @@
|
|||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/mvebu-pmsu.h>
|
||||
#include <asm/smp_plat.h>
|
||||
|
||||
#define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET 0x0
|
||||
#define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET 0xC
|
||||
#define SYS_CTRL_CLK_DIVIDER_MASK 0x3F
|
||||
#define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET 0x0
|
||||
#define SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL 0xff
|
||||
#define SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT 8
|
||||
#define SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET 0x8
|
||||
#define SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT 16
|
||||
#define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET 0xC
|
||||
#define SYS_CTRL_CLK_DIVIDER_MASK 0x3F
|
||||
|
||||
#define PMU_DFS_RATIO_SHIFT 16
|
||||
#define PMU_DFS_RATIO_MASK 0x3F
|
||||
|
||||
#define MAX_CPU 4
|
||||
struct cpu_clk {
|
||||
|
|
@ -28,6 +37,7 @@ struct cpu_clk {
|
|||
const char *clk_name;
|
||||
const char *parent_name;
|
||||
void __iomem *reg_base;
|
||||
void __iomem *pmu_dfs;
|
||||
};
|
||||
|
||||
static struct clk **clks;
|
||||
|
|
@ -62,8 +72,9 @@ static long clk_cpu_round_rate(struct clk_hw *hwclk, unsigned long rate,
|
|||
return *parent_rate / div;
|
||||
}
|
||||
|
||||
static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
static int clk_cpu_off_set_rate(struct clk_hw *hwclk, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
|
||||
{
|
||||
struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
|
||||
u32 reg, div;
|
||||
|
|
@ -95,6 +106,58 @@ static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int clk_cpu_on_set_rate(struct clk_hw *hwclk, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
u32 reg;
|
||||
unsigned long fabric_div, target_div, cur_rate;
|
||||
struct cpu_clk *cpuclk = to_cpu_clk(hwclk);
|
||||
|
||||
/*
|
||||
* PMU DFS registers are not mapped, Device Tree does not
|
||||
* describes them. We cannot change the frequency dynamically.
|
||||
*/
|
||||
if (!cpuclk->pmu_dfs)
|
||||
return -ENODEV;
|
||||
|
||||
cur_rate = __clk_get_rate(hwclk->clk);
|
||||
|
||||
reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET);
|
||||
fabric_div = (reg >> SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT) &
|
||||
SYS_CTRL_CLK_DIVIDER_MASK;
|
||||
|
||||
/* Frequency is going up */
|
||||
if (rate == 2 * cur_rate)
|
||||
target_div = fabric_div / 2;
|
||||
/* Frequency is going down */
|
||||
else
|
||||
target_div = fabric_div;
|
||||
|
||||
if (target_div == 0)
|
||||
target_div = 1;
|
||||
|
||||
reg = readl(cpuclk->pmu_dfs);
|
||||
reg &= ~(PMU_DFS_RATIO_MASK << PMU_DFS_RATIO_SHIFT);
|
||||
reg |= (target_div << PMU_DFS_RATIO_SHIFT);
|
||||
writel(reg, cpuclk->pmu_dfs);
|
||||
|
||||
reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
|
||||
reg |= (SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL <<
|
||||
SYS_CTRL_CLK_DIVIDER_CTRL_RESET_SHIFT);
|
||||
writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);
|
||||
|
||||
return mvebu_pmsu_dfs_request(cpuclk->cpu);
|
||||
}
|
||||
|
||||
static int clk_cpu_set_rate(struct clk_hw *hwclk, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
if (__clk_is_enabled(hwclk->clk))
|
||||
return clk_cpu_on_set_rate(hwclk, rate, parent_rate);
|
||||
else
|
||||
return clk_cpu_off_set_rate(hwclk, rate, parent_rate);
|
||||
}
|
||||
|
||||
static const struct clk_ops cpu_ops = {
|
||||
.recalc_rate = clk_cpu_recalc_rate,
|
||||
.round_rate = clk_cpu_round_rate,
|
||||
|
|
@ -105,6 +168,7 @@ static void __init of_cpu_clk_setup(struct device_node *node)
|
|||
{
|
||||
struct cpu_clk *cpuclk;
|
||||
void __iomem *clock_complex_base = of_iomap(node, 0);
|
||||
void __iomem *pmu_dfs_base = of_iomap(node, 1);
|
||||
int ncpus = 0;
|
||||
struct device_node *dn;
|
||||
|
||||
|
|
@ -114,6 +178,10 @@ static void __init of_cpu_clk_setup(struct device_node *node)
|
|||
return;
|
||||
}
|
||||
|
||||
if (pmu_dfs_base == NULL)
|
||||
pr_warn("%s: pmu-dfs base register not set, dynamic frequency scaling not available\n",
|
||||
__func__);
|
||||
|
||||
for_each_node_by_type(dn, "cpu")
|
||||
ncpus++;
|
||||
|
||||
|
|
@ -146,6 +214,8 @@ static void __init of_cpu_clk_setup(struct device_node *node)
|
|||
cpuclk[cpu].clk_name = clk_name;
|
||||
cpuclk[cpu].cpu = cpu;
|
||||
cpuclk[cpu].reg_base = clock_complex_base;
|
||||
if (pmu_dfs_base)
|
||||
cpuclk[cpu].pmu_dfs = pmu_dfs_base + 4 * cpu;
|
||||
cpuclk[cpu].hw.init = &init;
|
||||
|
||||
init.name = cpuclk[cpu].clk_name;
|
||||
|
|
|
|||
|
|
@ -1,12 +1,6 @@
|
|||
#
|
||||
# ARM CPU Idle drivers
|
||||
#
|
||||
config ARM_ARMADA_370_XP_CPUIDLE
|
||||
bool "CPU Idle Driver for Armada 370/XP family processors"
|
||||
depends on ARCH_MVEBU
|
||||
help
|
||||
Select this to enable cpuidle on Armada 370/XP processors.
|
||||
|
||||
config ARM_BIG_LITTLE_CPUIDLE
|
||||
bool "Support for ARM big.LITTLE processors"
|
||||
depends on ARCH_VEXPRESS_TC2_PM || ARCH_EXYNOS
|
||||
|
|
@ -61,3 +55,9 @@ config ARM_EXYNOS_CPUIDLE
|
|||
depends on ARCH_EXYNOS
|
||||
help
|
||||
Select this to enable cpuidle for Exynos processors
|
||||
|
||||
config ARM_MVEBU_V7_CPUIDLE
|
||||
bool "CPU Idle Driver for mvebu v7 family processors"
|
||||
depends on ARCH_MVEBU
|
||||
help
|
||||
Select this to enable cpuidle on Armada 370, 38x and XP processors.
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ obj-$(CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED) += coupled.o
|
|||
|
||||
##################################################################################
|
||||
# ARM SoC drivers
|
||||
obj-$(CONFIG_ARM_ARMADA_370_XP_CPUIDLE) += cpuidle-armada-370-xp.o
|
||||
obj-$(CONFIG_ARM_MVEBU_V7_CPUIDLE) += cpuidle-mvebu-v7.o
|
||||
obj-$(CONFIG_ARM_BIG_LITTLE_CPUIDLE) += cpuidle-big_little.o
|
||||
obj-$(CONFIG_ARM_CLPS711X_CPUIDLE) += cpuidle-clps711x.o
|
||||
obj-$(CONFIG_ARM_HIGHBANK_CPUIDLE) += cpuidle-calxeda.o
|
||||
|
|
|
|||
|
|
@ -1,93 +0,0 @@
|
|||
/*
|
||||
* Marvell Armada 370 and Armada XP SoC cpuidle driver
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Nadav Haklai <nadavh@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Maintainer: Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*/
|
||||
|
||||
#include <linux/cpu_pm.h>
|
||||
#include <linux/cpuidle.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <asm/cpuidle.h>
|
||||
|
||||
#define ARMADA_370_XP_MAX_STATES 3
|
||||
#define ARMADA_370_XP_FLAG_DEEP_IDLE 0x10000
|
||||
|
||||
static int (*armada_370_xp_cpu_suspend)(int);
|
||||
|
||||
static int armada_370_xp_enter_idle(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv,
|
||||
int index)
|
||||
{
|
||||
int ret;
|
||||
bool deepidle = false;
|
||||
cpu_pm_enter();
|
||||
|
||||
if (drv->states[index].flags & ARMADA_370_XP_FLAG_DEEP_IDLE)
|
||||
deepidle = true;
|
||||
|
||||
ret = armada_370_xp_cpu_suspend(deepidle);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
cpu_pm_exit();
|
||||
|
||||
return index;
|
||||
}
|
||||
|
||||
static struct cpuidle_driver armada_370_xp_idle_driver = {
|
||||
.name = "armada_370_xp_idle",
|
||||
.states[0] = ARM_CPUIDLE_WFI_STATE,
|
||||
.states[1] = {
|
||||
.enter = armada_370_xp_enter_idle,
|
||||
.exit_latency = 10,
|
||||
.power_usage = 50,
|
||||
.target_residency = 100,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.name = "Idle",
|
||||
.desc = "CPU power down",
|
||||
},
|
||||
.states[2] = {
|
||||
.enter = armada_370_xp_enter_idle,
|
||||
.exit_latency = 100,
|
||||
.power_usage = 5,
|
||||
.target_residency = 1000,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID |
|
||||
ARMADA_370_XP_FLAG_DEEP_IDLE,
|
||||
.name = "Deep idle",
|
||||
.desc = "CPU and L2 Fabric power down",
|
||||
},
|
||||
.state_count = ARMADA_370_XP_MAX_STATES,
|
||||
};
|
||||
|
||||
static int armada_370_xp_cpuidle_probe(struct platform_device *pdev)
|
||||
{
|
||||
|
||||
armada_370_xp_cpu_suspend = (void *)(pdev->dev.platform_data);
|
||||
return cpuidle_register(&armada_370_xp_idle_driver, NULL);
|
||||
}
|
||||
|
||||
static struct platform_driver armada_370_xp_cpuidle_plat_driver = {
|
||||
.driver = {
|
||||
.name = "cpuidle-armada-370-xp",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = armada_370_xp_cpuidle_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(armada_370_xp_cpuidle_plat_driver);
|
||||
|
||||
MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
|
||||
MODULE_DESCRIPTION("Armada 370/XP cpu idle driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
150
drivers/cpuidle/cpuidle-mvebu-v7.c
Normal file
150
drivers/cpuidle/cpuidle-mvebu-v7.c
Normal file
|
|
@ -0,0 +1,150 @@
|
|||
/*
|
||||
* Marvell Armada 370, 38x and XP SoC cpuidle driver
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Nadav Haklai <nadavh@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Maintainer: Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*/
|
||||
|
||||
#include <linux/cpu_pm.h>
|
||||
#include <linux/cpuidle.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <asm/cpuidle.h>
|
||||
|
||||
#define MVEBU_V7_FLAG_DEEP_IDLE 0x10000
|
||||
|
||||
static int (*mvebu_v7_cpu_suspend)(int);
|
||||
|
||||
static int mvebu_v7_enter_idle(struct cpuidle_device *dev,
|
||||
struct cpuidle_driver *drv,
|
||||
int index)
|
||||
{
|
||||
int ret;
|
||||
bool deepidle = false;
|
||||
cpu_pm_enter();
|
||||
|
||||
if (drv->states[index].flags & MVEBU_V7_FLAG_DEEP_IDLE)
|
||||
deepidle = true;
|
||||
|
||||
ret = mvebu_v7_cpu_suspend(deepidle);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
cpu_pm_exit();
|
||||
|
||||
return index;
|
||||
}
|
||||
|
||||
static struct cpuidle_driver armadaxp_idle_driver = {
|
||||
.name = "armada_xp_idle",
|
||||
.states[0] = ARM_CPUIDLE_WFI_STATE,
|
||||
.states[1] = {
|
||||
.enter = mvebu_v7_enter_idle,
|
||||
.exit_latency = 10,
|
||||
.power_usage = 50,
|
||||
.target_residency = 100,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.name = "MV CPU IDLE",
|
||||
.desc = "CPU power down",
|
||||
},
|
||||
.states[2] = {
|
||||
.enter = mvebu_v7_enter_idle,
|
||||
.exit_latency = 100,
|
||||
.power_usage = 5,
|
||||
.target_residency = 1000,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID |
|
||||
MVEBU_V7_FLAG_DEEP_IDLE,
|
||||
.name = "MV CPU DEEP IDLE",
|
||||
.desc = "CPU and L2 Fabric power down",
|
||||
},
|
||||
.state_count = 3,
|
||||
};
|
||||
|
||||
static struct cpuidle_driver armada370_idle_driver = {
|
||||
.name = "armada_370_idle",
|
||||
.states[0] = ARM_CPUIDLE_WFI_STATE,
|
||||
.states[1] = {
|
||||
.enter = mvebu_v7_enter_idle,
|
||||
.exit_latency = 100,
|
||||
.power_usage = 5,
|
||||
.target_residency = 1000,
|
||||
.flags = (CPUIDLE_FLAG_TIME_VALID |
|
||||
MVEBU_V7_FLAG_DEEP_IDLE),
|
||||
.name = "Deep Idle",
|
||||
.desc = "CPU and L2 Fabric power down",
|
||||
},
|
||||
.state_count = 2,
|
||||
};
|
||||
|
||||
static struct cpuidle_driver armada38x_idle_driver = {
|
||||
.name = "armada_38x_idle",
|
||||
.states[0] = ARM_CPUIDLE_WFI_STATE,
|
||||
.states[1] = {
|
||||
.enter = mvebu_v7_enter_idle,
|
||||
.exit_latency = 10,
|
||||
.power_usage = 5,
|
||||
.target_residency = 100,
|
||||
.flags = CPUIDLE_FLAG_TIME_VALID,
|
||||
.name = "Idle",
|
||||
.desc = "CPU and SCU power down",
|
||||
},
|
||||
.state_count = 2,
|
||||
};
|
||||
|
||||
static int mvebu_v7_cpuidle_probe(struct platform_device *pdev)
|
||||
{
|
||||
mvebu_v7_cpu_suspend = pdev->dev.platform_data;
|
||||
|
||||
if (!strcmp(pdev->dev.driver->name, "cpuidle-armada-xp"))
|
||||
return cpuidle_register(&armadaxp_idle_driver, NULL);
|
||||
else if (!strcmp(pdev->dev.driver->name, "cpuidle-armada-370"))
|
||||
return cpuidle_register(&armada370_idle_driver, NULL);
|
||||
else if (!strcmp(pdev->dev.driver->name, "cpuidle-armada-38x"))
|
||||
return cpuidle_register(&armada38x_idle_driver, NULL);
|
||||
else
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static struct platform_driver armadaxp_cpuidle_plat_driver = {
|
||||
.driver = {
|
||||
.name = "cpuidle-armada-xp",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = mvebu_v7_cpuidle_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(armadaxp_cpuidle_plat_driver);
|
||||
|
||||
static struct platform_driver armada370_cpuidle_plat_driver = {
|
||||
.driver = {
|
||||
.name = "cpuidle-armada-370",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = mvebu_v7_cpuidle_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(armada370_cpuidle_plat_driver);
|
||||
|
||||
static struct platform_driver armada38x_cpuidle_plat_driver = {
|
||||
.driver = {
|
||||
.name = "cpuidle-armada-38x",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.probe = mvebu_v7_cpuidle_probe,
|
||||
};
|
||||
|
||||
module_platform_driver(armada38x_cpuidle_plat_driver);
|
||||
|
||||
MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
|
||||
MODULE_DESCRIPTION("Marvell EBU v7 cpuidle driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
20
include/linux/mvebu-pmsu.h
Normal file
20
include/linux/mvebu-pmsu.h
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef __MVEBU_PMSU_H__
|
||||
#define __MVEBU_PMSU_H__
|
||||
|
||||
#ifdef CONFIG_MACH_MVEBU_V7
|
||||
int mvebu_pmsu_dfs_request(int cpu);
|
||||
#else
|
||||
static inline int mvebu_pmsu_dfs_request(int cpu) { return -ENODEV; }
|
||||
#endif
|
||||
|
||||
#endif /* __MVEBU_PMSU_H__ */
|
||||
Loading…
Reference in a new issue