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clk: sunxi: Remove old probe and protection code
Now that we don't have any user left for the old registration code, we can remove it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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c087230875
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1 changed files with 0 additions and 108 deletions
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@ -1080,111 +1080,3 @@ static void __init sun6i_pll6_clk_setup(struct device_node *node)
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}
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CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
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sun6i_pll6_clk_setup);
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/* Matches for factors clocks */
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static const struct of_device_id clk_factors_match[] __initconst = {
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{}
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};
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/* Matches for divider clocks */
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static const struct of_device_id clk_div_match[] __initconst = {
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{}
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};
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/* Matches for divided outputs */
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static const struct of_device_id clk_divs_match[] __initconst = {
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{}
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};
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/* Matches for mux clocks */
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static const struct of_device_id clk_mux_match[] __initconst = {
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{}
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};
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static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
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void *function)
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{
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struct device_node *np;
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const struct div_data *data;
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const struct of_device_id *match;
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void (*setup_function)(struct device_node *, const void *) = function;
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for_each_matching_node_and_match(np, clk_match, &match) {
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data = match->data;
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setup_function(np, data);
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}
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}
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static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
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{
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unsigned int i;
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/* Register divided output clocks */
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of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
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/* Register factor clocks */
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of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
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/* Register divider clocks */
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of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
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/* Register mux clocks */
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of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
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/* Protect the clocks that needs to stay on */
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for (i = 0; i < nclocks; i++) {
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struct clk *clk = clk_get(NULL, clocks[i]);
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if (!IS_ERR(clk))
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clk_prepare_enable(clk);
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}
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}
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static const char *sun4i_a10_critical_clocks[] __initdata = {
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"pll5_ddr",
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};
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static void __init sun4i_a10_init_clocks(struct device_node *node)
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{
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sunxi_init_clocks(sun4i_a10_critical_clocks,
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ARRAY_SIZE(sun4i_a10_critical_clocks));
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}
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CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
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static const char *sun5i_critical_clocks[] __initdata = {
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"cpu",
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"pll5_ddr",
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};
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static void __init sun5i_init_clocks(struct device_node *node)
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{
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sunxi_init_clocks(sun5i_critical_clocks,
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ARRAY_SIZE(sun5i_critical_clocks));
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}
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CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
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CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
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CLK_OF_DECLARE(sun5i_r8_clk_init, "allwinner,sun5i-r8", sun5i_init_clocks);
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CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
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static const char *sun6i_critical_clocks[] __initdata = {
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"cpu",
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};
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static void __init sun6i_init_clocks(struct device_node *node)
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{
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sunxi_init_clocks(sun6i_critical_clocks,
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ARRAY_SIZE(sun6i_critical_clocks));
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}
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CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
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CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
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CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
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CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
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CLK_OF_DECLARE(sun8i_h3_clk_init, "allwinner,sun8i-h3", sun6i_init_clocks);
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static void __init sun9i_init_clocks(struct device_node *node)
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{
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sunxi_init_clocks(NULL, 0);
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}
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CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);
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