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via-velocity: remove private #define
Registers and their bits from mii.h. Courtesy from ed. Signed-off-by: Francois Romieu <romieu@fr.zoreil.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
4cf46eaa5e
commit
3a7f8681ff
2 changed files with 60 additions and 131 deletions
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@ -719,30 +719,30 @@ static u32 mii_check_media_mode(struct mac_regs __iomem *regs)
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u32 status = 0;
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u16 ANAR;
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if (!MII_REG_BITS_IS_ON(BMSR_LNK, MII_REG_BMSR, regs))
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if (!MII_REG_BITS_IS_ON(BMSR_LSTATUS, MII_BMSR, regs))
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status |= VELOCITY_LINK_FAIL;
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if (MII_REG_BITS_IS_ON(G1000CR_1000FD, MII_REG_G1000CR, regs))
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if (MII_REG_BITS_IS_ON(ADVERTISE_1000FULL, MII_CTRL1000, regs))
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status |= VELOCITY_SPEED_1000 | VELOCITY_DUPLEX_FULL;
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else if (MII_REG_BITS_IS_ON(G1000CR_1000, MII_REG_G1000CR, regs))
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else if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF, MII_CTRL1000, regs))
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status |= (VELOCITY_SPEED_1000);
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else {
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velocity_mii_read(regs, MII_REG_ANAR, &ANAR);
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if (ANAR & ANAR_TXFD)
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velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
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if (ANAR & ADVERTISE_100FULL)
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status |= (VELOCITY_SPEED_100 | VELOCITY_DUPLEX_FULL);
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else if (ANAR & ANAR_TX)
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else if (ANAR & ADVERTISE_100HALF)
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status |= VELOCITY_SPEED_100;
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else if (ANAR & ANAR_10FD)
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else if (ANAR & ADVERTISE_10FULL)
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status |= (VELOCITY_SPEED_10 | VELOCITY_DUPLEX_FULL);
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else
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status |= (VELOCITY_SPEED_10);
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}
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if (MII_REG_BITS_IS_ON(BMCR_AUTO, MII_REG_BMCR, regs)) {
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velocity_mii_read(regs, MII_REG_ANAR, &ANAR);
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if ((ANAR & (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10))
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== (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10)) {
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if (MII_REG_BITS_IS_ON(G1000CR_1000 | G1000CR_1000FD, MII_REG_G1000CR, regs))
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if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) {
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velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
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if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF))
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== (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) {
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if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
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status |= VELOCITY_AUTONEG_ENABLE;
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}
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}
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@ -801,23 +801,23 @@ static void set_mii_flow_control(struct velocity_info *vptr)
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/*Enable or Disable PAUSE in ANAR */
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switch (vptr->options.flow_cntl) {
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case FLOW_CNTL_TX:
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MII_REG_BITS_OFF(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs);
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MII_REG_BITS_ON(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs);
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MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
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MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
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break;
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case FLOW_CNTL_RX:
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MII_REG_BITS_ON(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs);
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MII_REG_BITS_ON(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs);
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MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
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MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
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break;
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case FLOW_CNTL_TX_RX:
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MII_REG_BITS_ON(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs);
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MII_REG_BITS_ON(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs);
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MII_REG_BITS_ON(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
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MII_REG_BITS_ON(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
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break;
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case FLOW_CNTL_DISABLE:
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MII_REG_BITS_OFF(ANAR_PAUSE, MII_REG_ANAR, vptr->mac_regs);
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MII_REG_BITS_OFF(ANAR_ASMDIR, MII_REG_ANAR, vptr->mac_regs);
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MII_REG_BITS_OFF(ADVERTISE_PAUSE_CAP, MII_ADVERTISE, vptr->mac_regs);
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MII_REG_BITS_OFF(ADVERTISE_PAUSE_ASYM, MII_ADVERTISE, vptr->mac_regs);
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break;
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default:
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break;
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@ -832,10 +832,10 @@ static void set_mii_flow_control(struct velocity_info *vptr)
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*/
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static void mii_set_auto_on(struct velocity_info *vptr)
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{
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if (MII_REG_BITS_IS_ON(BMCR_AUTO, MII_REG_BMCR, vptr->mac_regs))
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MII_REG_BITS_ON(BMCR_REAUTO, MII_REG_BMCR, vptr->mac_regs);
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if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs))
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MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
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else
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MII_REG_BITS_ON(BMCR_AUTO, MII_REG_BMCR, vptr->mac_regs);
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MII_REG_BITS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs);
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}
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static u32 check_connection_type(struct mac_regs __iomem *regs)
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@ -860,11 +860,11 @@ static u32 check_connection_type(struct mac_regs __iomem *regs)
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else
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status |= VELOCITY_SPEED_100;
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if (MII_REG_BITS_IS_ON(BMCR_AUTO, MII_REG_BMCR, regs)) {
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velocity_mii_read(regs, MII_REG_ANAR, &ANAR);
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if ((ANAR & (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10))
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== (ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10)) {
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if (MII_REG_BITS_IS_ON(G1000CR_1000 | G1000CR_1000FD, MII_REG_G1000CR, regs))
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if (MII_REG_BITS_IS_ON(BMCR_ANENABLE, MII_BMCR, regs)) {
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velocity_mii_read(regs, MII_ADVERTISE, &ANAR);
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if ((ANAR & (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF))
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== (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF)) {
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if (MII_REG_BITS_IS_ON(ADVERTISE_1000HALF | ADVERTISE_1000FULL, MII_CTRL1000, regs))
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status |= VELOCITY_AUTONEG_ENABLE;
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}
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}
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@ -905,7 +905,7 @@ static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status)
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*/
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if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
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MII_REG_BITS_ON(AUXCR_MDPPS, MII_REG_AUXCR, vptr->mac_regs);
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MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
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/*
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* If connection type is AUTO
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@ -915,9 +915,9 @@ static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status)
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/* clear force MAC mode bit */
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BYTE_REG_BITS_OFF(CHIPGCR_FCMODE, ®s->CHIPGCR);
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/* set duplex mode of MAC according to duplex mode of MII */
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MII_REG_BITS_ON(ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10, MII_REG_ANAR, vptr->mac_regs);
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MII_REG_BITS_ON(G1000CR_1000FD | G1000CR_1000, MII_REG_G1000CR, vptr->mac_regs);
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MII_REG_BITS_ON(BMCR_SPEED1G, MII_REG_BMCR, vptr->mac_regs);
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MII_REG_BITS_ON(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF, MII_ADVERTISE, vptr->mac_regs);
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MII_REG_BITS_ON(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
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MII_REG_BITS_ON(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs);
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/* enable AUTO-NEGO mode */
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mii_set_auto_on(vptr);
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@ -952,31 +952,31 @@ static int velocity_set_media_mode(struct velocity_info *vptr, u32 mii_status)
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BYTE_REG_BITS_ON(TCR_TB2BDIS, ®s->TCR);
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}
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MII_REG_BITS_OFF(G1000CR_1000FD | G1000CR_1000, MII_REG_G1000CR, vptr->mac_regs);
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MII_REG_BITS_OFF(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
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if (!(mii_status & VELOCITY_DUPLEX_FULL) && (mii_status & VELOCITY_SPEED_10))
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BYTE_REG_BITS_OFF(TESTCFG_HBDIS, ®s->TESTCFG);
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else
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BYTE_REG_BITS_ON(TESTCFG_HBDIS, ®s->TESTCFG);
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/* MII_REG_BITS_OFF(BMCR_SPEED1G, MII_REG_BMCR, vptr->mac_regs); */
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velocity_mii_read(vptr->mac_regs, MII_REG_ANAR, &ANAR);
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ANAR &= (~(ANAR_TXFD | ANAR_TX | ANAR_10FD | ANAR_10));
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/* MII_REG_BITS_OFF(BMCR_SPEED1000, MII_BMCR, vptr->mac_regs); */
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velocity_mii_read(vptr->mac_regs, MII_ADVERTISE, &ANAR);
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ANAR &= (~(ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL | ADVERTISE_10HALF));
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if (mii_status & VELOCITY_SPEED_100) {
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if (mii_status & VELOCITY_DUPLEX_FULL)
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ANAR |= ANAR_TXFD;
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ANAR |= ADVERTISE_100FULL;
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else
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ANAR |= ANAR_TX;
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ANAR |= ADVERTISE_100HALF;
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} else {
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if (mii_status & VELOCITY_DUPLEX_FULL)
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ANAR |= ANAR_10FD;
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ANAR |= ADVERTISE_10FULL;
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else
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ANAR |= ANAR_10;
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ANAR |= ADVERTISE_10HALF;
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}
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velocity_mii_write(vptr->mac_regs, MII_REG_ANAR, ANAR);
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velocity_mii_write(vptr->mac_regs, MII_ADVERTISE, ANAR);
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/* enable AUTO-NEGO mode */
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mii_set_auto_on(vptr);
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/* MII_REG_BITS_ON(BMCR_AUTO, MII_REG_BMCR, vptr->mac_regs); */
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/* MII_REG_BITS_ON(BMCR_ANENABLE, MII_BMCR, vptr->mac_regs); */
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}
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/* vptr->mii_status=mii_check_media_mode(vptr->mac_regs); */
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/* vptr->mii_status=check_connection_type(vptr->mac_regs); */
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@ -1178,36 +1178,36 @@ static void mii_init(struct velocity_info *vptr, u32 mii_status)
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/*
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* Reset to hardware default
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*/
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MII_REG_BITS_OFF((ANAR_ASMDIR | ANAR_PAUSE), MII_REG_ANAR, vptr->mac_regs);
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MII_REG_BITS_OFF((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
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/*
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* Turn on ECHODIS bit in NWay-forced full mode and turn it
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* off it in NWay-forced half mode for NWay-forced v.s.
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* legacy-forced issue.
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*/
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if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
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MII_REG_BITS_ON(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs);
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MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
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else
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MII_REG_BITS_OFF(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs);
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MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
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/*
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* Turn on Link/Activity LED enable bit for CIS8201
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*/
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MII_REG_BITS_ON(PLED_LALBE, MII_REG_PLED, vptr->mac_regs);
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MII_REG_BITS_ON(PLED_LALBE, MII_TPISTATUS, vptr->mac_regs);
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break;
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case PHYID_VT3216_32BIT:
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case PHYID_VT3216_64BIT:
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/*
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* Reset to hardware default
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*/
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MII_REG_BITS_ON((ANAR_ASMDIR | ANAR_PAUSE), MII_REG_ANAR, vptr->mac_regs);
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MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
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/*
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* Turn on ECHODIS bit in NWay-forced full mode and turn it
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* off it in NWay-forced half mode for NWay-forced v.s.
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* legacy-forced issue
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*/
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if (vptr->mii_status & VELOCITY_DUPLEX_FULL)
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MII_REG_BITS_ON(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs);
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MII_REG_BITS_ON(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
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else
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MII_REG_BITS_OFF(TCSR_ECHODIS, MII_REG_TCSR, vptr->mac_regs);
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MII_REG_BITS_OFF(TCSR_ECHODIS, MII_SREVISION, vptr->mac_regs);
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break;
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case PHYID_MARVELL_1000:
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@ -1219,15 +1219,15 @@ static void mii_init(struct velocity_info *vptr, u32 mii_status)
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/*
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* Reset to hardware default
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*/
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MII_REG_BITS_ON((ANAR_ASMDIR | ANAR_PAUSE), MII_REG_ANAR, vptr->mac_regs);
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MII_REG_BITS_ON((ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP), MII_ADVERTISE, vptr->mac_regs);
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break;
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default:
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;
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}
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velocity_mii_read(vptr->mac_regs, MII_REG_BMCR, &BMCR);
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if (BMCR & BMCR_ISO) {
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BMCR &= ~BMCR_ISO;
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velocity_mii_write(vptr->mac_regs, MII_REG_BMCR, BMCR);
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velocity_mii_read(vptr->mac_regs, MII_BMCR, &BMCR);
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if (BMCR & BMCR_ISOLATE) {
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BMCR &= ~BMCR_ISOLATE;
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velocity_mii_write(vptr->mac_regs, MII_BMCR, BMCR);
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}
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}
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@ -2953,13 +2953,13 @@ static int velocity_set_wol(struct velocity_info *vptr)
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if (vptr->mii_status & VELOCITY_AUTONEG_ENABLE) {
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if (PHYID_GET_PHY_ID(vptr->phy_id) == PHYID_CICADA_CS8201)
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MII_REG_BITS_ON(AUXCR_MDPPS, MII_REG_AUXCR, vptr->mac_regs);
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MII_REG_BITS_ON(AUXCR_MDPPS, MII_NCONFIG, vptr->mac_regs);
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MII_REG_BITS_OFF(G1000CR_1000FD | G1000CR_1000, MII_REG_G1000CR, vptr->mac_regs);
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MII_REG_BITS_OFF(ADVERTISE_1000FULL | ADVERTISE_1000HALF, MII_CTRL1000, vptr->mac_regs);
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}
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if (vptr->mii_status & VELOCITY_SPEED_1000)
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MII_REG_BITS_ON(BMCR_REAUTO, MII_REG_BMCR, vptr->mac_regs);
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MII_REG_BITS_ON(BMCR_ANRESTART, MII_BMCR, vptr->mac_regs);
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BYTE_REG_BITS_ON(CHIPGCR_FCMODE, ®s->CHIPGCR);
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@ -1240,86 +1240,16 @@ struct velocity_context {
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u32 pattern[8];
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};
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/*
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* MII registers.
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*/
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/*
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* Registers in the MII (offset unit is WORD)
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*/
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#define MII_REG_BMCR 0x00 // physical address
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#define MII_REG_BMSR 0x01 //
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#define MII_REG_PHYID1 0x02 // OUI
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#define MII_REG_PHYID2 0x03 // OUI + Module ID + REV ID
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#define MII_REG_ANAR 0x04 //
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#define MII_REG_ANLPAR 0x05 //
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#define MII_REG_G1000CR 0x09 //
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#define MII_REG_G1000SR 0x0A //
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#define MII_REG_MODCFG 0x10 //
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#define MII_REG_TCSR 0x16 //
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#define MII_REG_PLED 0x1B //
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// NS, MYSON only
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#define MII_REG_PCR 0x17 //
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// ESI only
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#define MII_REG_PCSR 0x17 //
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#define MII_REG_AUXCR 0x1C //
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// Marvell 88E1000/88E1000S
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#define MII_REG_PSCR 0x10 // PHY specific control register
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//
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// Bits in the BMCR register
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// Bits in the Silicon revision register
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//
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#define BMCR_RESET 0x8000 //
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#define BMCR_LBK 0x4000 //
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#define BMCR_SPEED100 0x2000 //
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#define BMCR_AUTO 0x1000 //
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#define BMCR_PD 0x0800 //
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#define BMCR_ISO 0x0400 //
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#define BMCR_REAUTO 0x0200 //
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#define BMCR_FDX 0x0100 //
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#define BMCR_SPEED1G 0x0040 //
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//
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// Bits in the BMSR register
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//
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#define BMSR_AUTOCM 0x0020 //
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#define BMSR_LNK 0x0004 //
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//
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// Bits in the ANAR register
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//
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#define ANAR_ASMDIR 0x0800 // Asymmetric PAUSE support
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#define ANAR_PAUSE 0x0400 // Symmetric PAUSE Support
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#define ANAR_T4 0x0200 //
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#define ANAR_TXFD 0x0100 //
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#define ANAR_TX 0x0080 //
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#define ANAR_10FD 0x0040 //
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#define ANAR_10 0x0020 //
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//
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// Bits in the ANLPAR register
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//
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#define ANLPAR_ASMDIR 0x0800 // Asymmetric PAUSE support
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#define ANLPAR_PAUSE 0x0400 // Symmetric PAUSE Support
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#define ANLPAR_T4 0x0200 //
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#define ANLPAR_TXFD 0x0100 //
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#define ANLPAR_TX 0x0080 //
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#define ANLPAR_10FD 0x0040 //
|
||||
#define ANLPAR_10 0x0020 //
|
||||
|
||||
//
|
||||
// Bits in the G1000CR register
|
||||
//
|
||||
#define G1000CR_1000FD 0x0200 // PHY is 1000-T Full-duplex capable
|
||||
#define G1000CR_1000 0x0100 // PHY is 1000-T Half-duplex capable
|
||||
|
||||
//
|
||||
// Bits in the G1000SR register
|
||||
//
|
||||
#define G1000SR_1000FD 0x0800 // LP PHY is 1000-T Full-duplex capable
|
||||
#define G1000SR_1000 0x0400 // LP PHY is 1000-T Half-duplex capable
|
||||
|
||||
#define TCSR_ECHODIS 0x2000 //
|
||||
#define AUXCR_MDPPS 0x0004 //
|
||||
|
@ -1338,7 +1268,6 @@ struct velocity_context {
|
|||
|
||||
#define PHYID_REV_ID_MASK 0x0000000FUL
|
||||
|
||||
#define PHYID_GET_PHY_REV_ID(i) ((i) & PHYID_REV_ID_MASK)
|
||||
#define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK)
|
||||
|
||||
#define MII_REG_BITS_ON(x,i,p) do {\
|
||||
|
@ -1362,8 +1291,8 @@ struct velocity_context {
|
|||
|
||||
#define MII_GET_PHY_ID(p) ({\
|
||||
u32 id;\
|
||||
velocity_mii_read((p),MII_REG_PHYID2,(u16 *) &id);\
|
||||
velocity_mii_read((p),MII_REG_PHYID1,((u16 *) &id)+1);\
|
||||
velocity_mii_read((p),MII_PHYSID2,(u16 *) &id);\
|
||||
velocity_mii_read((p),MII_PHYSID1,((u16 *) &id)+1);\
|
||||
(id);})
|
||||
|
||||
/*
|
||||
|
|
Loading…
Reference in a new issue