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clk: socfpga: allow building N5X clocks with ARCH_N5X
The Intel's eASIC N5X (ARCH_N5X) architecture shares a lot with Agilex (ARCH_AGILEX) so it uses the same socfpga_agilex.dtsi, with minor changes. Also the clock drivers are the same. However the clock drivers won't be build without ARCH_AGILEX. One could assume that ARCH_N5X simply depends on ARCH_AGILEX but this was not modeled in Kconfig. In current stage the ARCH_N5X is simply unbootable. Add a separate Kconfig entry for clocks used by both ARCH_N5X and ARCH_AGILEX so the necessary objects will be built if either of them is selected. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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parent
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commit
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4 changed files with 10 additions and 2 deletions
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@ -394,6 +394,7 @@ source "drivers/clk/renesas/Kconfig"
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source "drivers/clk/rockchip/Kconfig"
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source "drivers/clk/samsung/Kconfig"
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source "drivers/clk/sifive/Kconfig"
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source "drivers/clk/socfpga/Kconfig"
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source "drivers/clk/sprd/Kconfig"
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source "drivers/clk/sunxi/Kconfig"
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source "drivers/clk/sunxi-ng/Kconfig"
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@ -106,6 +106,7 @@ obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
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obj-$(CONFIG_CLK_SIFIVE) += sifive/
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obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
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obj-$(CONFIG_ARCH_AGILEX) += socfpga/
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obj-$(CONFIG_ARCH_N5X) += socfpga/
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obj-$(CONFIG_ARCH_STRATIX10) += socfpga/
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obj-$(CONFIG_PLAT_SPEAR) += spear/
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obj-y += sprd/
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6
drivers/clk/socfpga/Kconfig
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6
drivers/clk/socfpga/Kconfig
Normal file
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@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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config CLK_INTEL_SOCFPGA64
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bool
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# Intel Agilex / N5X clock controller support
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default (ARCH_AGILEX || ARCH_N5X)
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depends on ARCH_AGILEX || ARCH_N5X
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@ -3,5 +3,5 @@ obj-$(CONFIG_ARCH_SOCFPGA) += clk.o clk-gate.o clk-pll.o clk-periph.o
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obj-$(CONFIG_ARCH_SOCFPGA) += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
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obj-$(CONFIG_ARCH_STRATIX10) += clk-s10.o
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obj-$(CONFIG_ARCH_STRATIX10) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
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obj-$(CONFIG_ARCH_AGILEX) += clk-agilex.o
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obj-$(CONFIG_ARCH_AGILEX) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
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obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-agilex.o
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obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o
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