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drm/i915/dg2: use existing mechanisms for SNPS PHY translations
We use encoder->get_buf_trans() in many places, for example intel_ddi_dp_voltage_max(), and the hook was set to some old platform's function for DG2 SNPS PHY. Convert SNPS PHY to use the same translation mechanisms as everything else. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210813115151.19290-2-jani.nikula@intel.com
This commit is contained in:
parent
0707570248
commit
3b4da8315a
5 changed files with 59 additions and 49 deletions
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@ -1388,7 +1388,7 @@ dg2_set_signal_levels(struct intel_dp *intel_dp,
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struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
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int level = intel_ddi_dp_level(intel_dp, crtc_state);
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intel_snps_phy_ddi_vswing_sequence(encoder, level);
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intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level);
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}
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static void
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@ -2392,7 +2392,7 @@ static void dg2_ddi_pre_enable_dp(struct intel_atomic_state *state,
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*/
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/* 5.e Configure voltage swing and related IO settings */
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intel_snps_phy_ddi_vswing_sequence(encoder, level);
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intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level);
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/*
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* 5.f Configure and enable DDI_BUF_CTL
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@ -3061,7 +3061,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
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connector->base.id, connector->name);
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if (IS_DG2(dev_priv))
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intel_snps_phy_ddi_vswing_sequence(encoder, U32_MAX);
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intel_snps_phy_ddi_vswing_sequence(encoder, crtc_state, level);
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else if (DISPLAY_VER(dev_priv) >= 12)
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tgl_ddi_vswing_sequence(encoder, crtc_state, level);
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else if (DISPLAY_VER(dev_priv) == 11)
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@ -983,6 +983,25 @@ static const struct intel_ddi_buf_trans adlp_dkl_phy_ddi_translations_dp_hbr2_hb
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.num_entries = ARRAY_SIZE(_adlp_dkl_phy_ddi_translations_dp_hbr2_hbr3),
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};
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static const union intel_ddi_buf_trans_entry _dg2_snps_translations[] = {
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{ .snps = { 26, 0, 0 } }, /* VS 0, pre-emph 0 */
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{ .snps = { 33, 0, 6 } }, /* VS 0, pre-emph 1 */
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{ .snps = { 38, 0, 12 } }, /* VS 0, pre-emph 2 */
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{ .snps = { 43, 0, 19 } }, /* VS 0, pre-emph 3 */
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{ .snps = { 39, 0, 0 } }, /* VS 1, pre-emph 0 */
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{ .snps = { 44, 0, 8 } }, /* VS 1, pre-emph 1 */
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{ .snps = { 47, 0, 15 } }, /* VS 1, pre-emph 2 */
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{ .snps = { 52, 0, 0 } }, /* VS 2, pre-emph 0 */
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{ .snps = { 51, 0, 10 } }, /* VS 2, pre-emph 1 */
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{ .snps = { 62, 0, 0 } }, /* VS 3, pre-emph 0 */
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};
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static const struct intel_ddi_buf_trans dg2_snps_translations = {
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.entries = _dg2_snps_translations,
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.num_entries = ARRAY_SIZE(_dg2_snps_translations),
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.hdmi_default_entry = ARRAY_SIZE(_dg2_snps_translations) - 1,
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};
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bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
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{
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return table == &tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
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@ -1563,6 +1582,14 @@ adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
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return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
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}
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static const struct intel_ddi_buf_trans *
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dg2_get_snps_buf_trans(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state,
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int *n_entries)
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{
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return intel_get_buf_trans(&dg2_snps_translations, n_entries);
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}
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int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
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const struct intel_crtc_state *crtc_state,
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int *default_entry)
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@ -1588,7 +1615,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
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struct drm_i915_private *i915 = to_i915(encoder->base.dev);
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enum phy phy = intel_port_to_phy(i915, encoder->port);
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if (IS_ALDERLAKE_P(i915)) {
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if (IS_DG2(i915)) {
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encoder->get_buf_trans = dg2_get_snps_buf_trans;
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} else if (IS_ALDERLAKE_P(i915)) {
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if (intel_phy_is_combo(i915, phy))
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encoder->get_buf_trans = adlp_get_combo_buf_trans;
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else
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@ -45,12 +45,19 @@ struct tgl_dkl_phy_ddi_buf_trans {
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u32 dkl_de_emphasis_control;
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};
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struct dg2_snps_phy_buf_trans {
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u8 snps_vswing;
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u8 snps_pre_cursor;
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u8 snps_post_cursor;
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};
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union intel_ddi_buf_trans_entry {
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struct hsw_ddi_buf_trans hsw;
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struct bxt_ddi_buf_trans bxt;
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struct icl_ddi_buf_trans icl;
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struct icl_mg_phy_ddi_buf_trans mg;
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struct tgl_dkl_phy_ddi_buf_trans dkl;
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struct dg2_snps_phy_buf_trans snps;
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};
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struct intel_ddi_buf_trans {
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@ -5,6 +5,7 @@
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#include <linux/util_macros.h>
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#include "intel_ddi_buf_trans.h"
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#include "intel_de.h"
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#include "intel_display_types.h"
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#include "intel_snps_phy.h"
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@ -50,58 +51,30 @@ void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv,
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SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val);
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}
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static const u32 dg2_ddi_translations[] = {
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/* VS 0, pre-emph 0 */
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 26),
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/* VS 0, pre-emph 1 */
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 33) |
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 6),
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/* VS 0, pre-emph 2 */
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 38) |
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 12),
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/* VS 0, pre-emph 3 */
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 43) |
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 19),
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/* VS 1, pre-emph 0 */
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 39),
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/* VS 1, pre-emph 1 */
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 44) |
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 8),
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/* VS 1, pre-emph 2 */
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 47) |
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 15),
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/* VS 2, pre-emph 0 */
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 52),
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/* VS 2, pre-emph 1 */
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 51) |
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 10),
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/* VS 3, pre-emph 0 */
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REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 62),
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};
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void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
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u32 level)
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const struct intel_crtc_state *crtc_state,
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int level)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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const struct intel_ddi_buf_trans *ddi_translations;
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enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
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int n_entries, ln;
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n_entries = ARRAY_SIZE(dg2_ddi_translations);
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if (level >= n_entries)
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ddi_translations = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
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if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
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return;
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if (drm_WARN_ON_ONCE(&dev_priv->drm, level < 0 || level >= n_entries))
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level = n_entries - 1;
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for (ln = 0; ln < 4; ln++)
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intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy),
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dg2_ddi_translations[level]);
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for (ln = 0; ln < 4; ln++) {
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u32 val = 0;
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val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, ddi_translations->entries[level].snps.snps_vswing);
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val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, ddi_translations->entries[level].snps.snps_pre_cursor);
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val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, ddi_translations->entries[level].snps.snps_post_cursor);
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intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy), val);
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}
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}
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/*
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@ -30,6 +30,7 @@ int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
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int intel_snps_phy_check_hdmi_link_rate(int clock);
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void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
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u32 level);
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const struct intel_crtc_state *crtc_state,
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int level);
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#endif /* __INTEL_SNPS_PHY_H__ */
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