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drm/i915/display/psr: Lock and unlock PSR around pipe updates
Frontbuffer rendering and page flips can race with each other and this can potentialy cause issues with PSR2 selective fetch. And because pipe/crtc updates are time sentive we can't grab the PSR lock after intel_pipe_update_start() and before intel_pipe_update_end(). So here adding the lock and unlock functions and calls, the proper PSR2 selective fetch handling will come in a separated patch. v2: - fixed new functions documentation Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Cc: Jouni Högander <jouni.hogander@intel.com> Cc: Mika Kahola <mika.kahola@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220405155344.47219-2-jose.souza@intel.com
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aa94bf3089
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3 changed files with 70 additions and 10 deletions
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@ -507,6 +507,8 @@ void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
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VBLANK_EVASION_TIME_US);
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max = vblank_start - 1;
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intel_psr_lock(new_crtc_state);
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if (min <= 0 || max <= 0)
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goto irq_disable;
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@ -518,7 +520,7 @@ void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state)
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* VBL interrupts will start the PSR exit and prevent a PSR
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* re-entry as well.
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*/
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intel_psr_wait_for_idle(new_crtc_state);
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intel_psr_wait_for_idle_locked(new_crtc_state);
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local_irq_disable();
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@ -683,6 +685,8 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
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local_irq_enable();
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intel_psr_unlock(new_crtc_state);
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if (intel_vgpu_active(dev_priv))
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return;
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@ -1548,10 +1548,19 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
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void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
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struct intel_encoder *encoder;
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if (!crtc_state->enable_psr2_sel_fetch)
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return;
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for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder,
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crtc_state->uapi.encoder_mask) {
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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lockdep_assert_held(&intel_dp->psr.lock);
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break;
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}
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intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(crtc_state->cpu_transcoder),
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crtc_state->psr2_man_track_ctl);
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}
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@ -1919,13 +1928,13 @@ static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp)
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}
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/**
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* intel_psr_wait_for_idle - wait for PSR be ready for a pipe update
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* intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
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* @new_crtc_state: new CRTC state
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*
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* This function is expected to be called from pipe_update_start() where it is
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* not expected to race with PSR enable or disable.
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*/
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void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
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void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state)
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{
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struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev);
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struct intel_encoder *encoder;
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@ -1938,12 +1947,10 @@ void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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int ret;
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mutex_lock(&intel_dp->psr.lock);
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lockdep_assert_held(&intel_dp->psr.lock);
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if (!intel_dp->psr.enabled) {
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mutex_unlock(&intel_dp->psr.lock);
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if (!intel_dp->psr.enabled)
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continue;
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}
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if (intel_dp->psr.psr2_enabled)
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ret = _psr2_ready_for_pipe_update_locked(intel_dp);
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@ -1952,8 +1959,6 @@ void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state)
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if (ret)
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drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n");
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mutex_unlock(&intel_dp->psr.lock);
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}
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}
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@ -2444,3 +2449,51 @@ bool intel_psr_enabled(struct intel_dp *intel_dp)
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return ret;
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}
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/**
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* intel_psr_lock - grab PSR lock
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* @crtc_state: the crtc state
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*
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* This is initially meant to be used by around CRTC update, when
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* vblank sensitive registers are updated and we need grab the lock
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* before it to avoid vblank evasion.
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*/
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void intel_psr_lock(const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
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struct intel_encoder *encoder;
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if (!crtc_state->has_psr)
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return;
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for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
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crtc_state->uapi.encoder_mask) {
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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mutex_lock(&intel_dp->psr.lock);
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break;
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}
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}
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/**
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* intel_psr_unlock - release PSR lock
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* @crtc_state: the crtc state
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*
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* Release the PSR lock that was held during pipe update.
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*/
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void intel_psr_unlock(const struct intel_crtc_state *crtc_state)
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{
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struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
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struct intel_encoder *encoder;
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if (!crtc_state->has_psr)
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return;
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for_each_intel_encoder_mask_with_psr(&i915->drm, encoder,
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crtc_state->uapi.encoder_mask) {
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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mutex_unlock(&intel_dp->psr.lock);
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break;
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}
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}
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@ -41,7 +41,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
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struct intel_crtc_state *pipe_config);
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void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
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void intel_psr_short_pulse(struct intel_dp *intel_dp);
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void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
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void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_state);
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bool intel_psr_enabled(struct intel_dp *intel_dp);
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int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
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struct intel_crtc *crtc);
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@ -55,4 +55,7 @@ void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
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void intel_psr_pause(struct intel_dp *intel_dp);
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void intel_psr_resume(struct intel_dp *intel_dp);
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void intel_psr_lock(const struct intel_crtc_state *crtc_state);
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void intel_psr_unlock(const struct intel_crtc_state *crtc_state);
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#endif /* __INTEL_PSR_H__ */
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