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dt-bindings: interrupt-controller: Add RISC-V advanced PLIC
Add DT bindings document for RISC-V advanced platform level interrupt controller (APLIC) defined by the RISC-V advanced interrupt architecture (AIA) specification. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Björn Töpel <bjorn@rivosinc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Björn Töpel <bjorn@rivosinc.com> Link: https://lore.kernel.org/r/20240307140307.646078-6-apatel@ventanamicro.com
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
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maintainers:
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- Anup Patel <anup@brainfault.org>
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description:
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The RISC-V advanced interrupt architecture (AIA) defines an advanced
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platform level interrupt controller (APLIC) for handling wired interrupts
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in a RISC-V platform. The RISC-V AIA specification can be found at
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https://github.com/riscv/riscv-aia.
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The RISC-V APLIC is implemented as hierarchical APLIC domains where all
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interrupt sources connect to the root APLIC domain and a parent APLIC
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domain can delegate interrupt sources to it's child APLIC domains. There
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is one device tree node for each APLIC domain.
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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properties:
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compatible:
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items:
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- enum:
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- qemu,aplic
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- const: riscv,aplic
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reg:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells":
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const: 2
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interrupts-extended:
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minItems: 1
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maxItems: 16384
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description:
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Given APLIC domain directly injects external interrupts to a set of
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RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
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node, which has a CPU node (i.e. RISC-V HART) as parent.
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msi-parent:
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description:
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Given APLIC domain forwards wired interrupts as MSIs to a AIA incoming
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message signaled interrupt controller (IMSIC). If both "msi-parent" and
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"interrupts-extended" properties are present then it means the APLIC
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domain supports both MSI mode and Direct mode in HW. In this case, the
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APLIC driver has to choose between MSI mode or Direct mode.
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riscv,num-sources:
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 1023
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description:
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Specifies the number of wired interrupt sources supported by this
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APLIC domain.
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riscv,children:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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minItems: 1
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maxItems: 1024
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items:
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maxItems: 1
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description:
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A list of child APLIC domains for the given APLIC domain. Each child
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APLIC domain is assigned a child index in increasing order, with the
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first child APLIC domain assigned child index 0. The APLIC domain child
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index is used by firmware to delegate interrupts from the given APLIC
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domain to a particular child APLIC domain.
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riscv,delegation:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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minItems: 1
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maxItems: 1024
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items:
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items:
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- description: child APLIC domain phandle
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- description: first interrupt number of the parent APLIC domain (inclusive)
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- description: last interrupt number of the parent APLIC domain (inclusive)
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description:
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A interrupt delegation list where each entry is a triple consisting
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of child APLIC domain phandle, first interrupt number of the parent
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APLIC domain, and last interrupt number of the parent APLIC domain.
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Firmware must configure interrupt delegation registers based on
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interrupt delegation list.
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dependencies:
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riscv,delegation: [ "riscv,children" ]
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required:
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- compatible
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- reg
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- interrupt-controller
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- "#interrupt-cells"
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- riscv,num-sources
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anyOf:
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- required:
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- interrupts-extended
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- required:
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- msi-parent
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unevaluatedProperties: false
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examples:
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- |
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// Example 1 (APLIC domains directly injecting interrupt to HARTs):
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interrupt-controller@c000000 {
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compatible = "qemu,aplic", "riscv,aplic";
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interrupts-extended = <&cpu1_intc 11>,
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<&cpu2_intc 11>,
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<&cpu3_intc 11>,
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<&cpu4_intc 11>;
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reg = <0xc000000 0x4080>;
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interrupt-controller;
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#interrupt-cells = <2>;
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riscv,num-sources = <63>;
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riscv,children = <&aplic1>, <&aplic2>;
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riscv,delegation = <&aplic1 1 63>;
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};
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aplic1: interrupt-controller@d000000 {
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compatible = "qemu,aplic", "riscv,aplic";
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interrupts-extended = <&cpu1_intc 9>,
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<&cpu2_intc 9>;
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reg = <0xd000000 0x4080>;
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interrupt-controller;
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#interrupt-cells = <2>;
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riscv,num-sources = <63>;
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};
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aplic2: interrupt-controller@e000000 {
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compatible = "qemu,aplic", "riscv,aplic";
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interrupts-extended = <&cpu3_intc 9>,
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<&cpu4_intc 9>;
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reg = <0xe000000 0x4080>;
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interrupt-controller;
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#interrupt-cells = <2>;
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riscv,num-sources = <63>;
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};
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- |
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// Example 2 (APLIC domains forwarding interrupts as MSIs):
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interrupt-controller@c000000 {
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compatible = "qemu,aplic", "riscv,aplic";
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msi-parent = <&imsic_mlevel>;
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reg = <0xc000000 0x4000>;
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interrupt-controller;
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#interrupt-cells = <2>;
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riscv,num-sources = <63>;
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riscv,children = <&aplic3>;
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riscv,delegation = <&aplic3 1 63>;
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};
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aplic3: interrupt-controller@d000000 {
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compatible = "qemu,aplic", "riscv,aplic";
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msi-parent = <&imsic_slevel>;
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reg = <0xd000000 0x4000>;
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interrupt-controller;
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#interrupt-cells = <2>;
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riscv,num-sources = <63>;
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};
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...
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