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synced 2024-08-22 17:01:14 +00:00
qed: Add APIs for configuring grc dump config flags.
The patch adds driver support for configuring the grc dump config flags. Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com> Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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4 changed files with 127 additions and 0 deletions
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@ -1756,6 +1756,15 @@ static u32 qed_read_unaligned_dword(u8 *buf)
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return dword;
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return dword;
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}
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}
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/* Sets the value of the specified GRC param */
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static void qed_grc_set_param(struct qed_hwfn *p_hwfn,
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enum dbg_grc_params grc_param, u32 val)
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{
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struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
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dev_data->grc.param_val[grc_param] = val;
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}
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/* Returns the value of the specified GRC param */
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/* Returns the value of the specified GRC param */
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static u32 qed_grc_get_param(struct qed_hwfn *p_hwfn,
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static u32 qed_grc_get_param(struct qed_hwfn *p_hwfn,
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enum dbg_grc_params grc_param)
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enum dbg_grc_params grc_param)
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@ -5119,6 +5128,69 @@ bool qed_read_fw_info(struct qed_hwfn *p_hwfn,
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return false;
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return false;
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}
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}
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enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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enum dbg_grc_params grc_param, u32 val)
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{
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enum dbg_status status;
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int i;
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DP_VERBOSE(p_hwfn, QED_MSG_DEBUG,
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"dbg_grc_config: paramId = %d, val = %d\n", grc_param, val);
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status = qed_dbg_dev_init(p_hwfn, p_ptt);
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if (status != DBG_STATUS_OK)
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return status;
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/* Initializes the GRC parameters (if not initialized). Needed in order
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* to set the default parameter values for the first time.
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*/
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qed_dbg_grc_init_params(p_hwfn);
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if (grc_param >= MAX_DBG_GRC_PARAMS)
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return DBG_STATUS_INVALID_ARGS;
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if (val < s_grc_param_defs[grc_param].min ||
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val > s_grc_param_defs[grc_param].max)
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return DBG_STATUS_INVALID_ARGS;
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if (s_grc_param_defs[grc_param].is_preset) {
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/* Preset param */
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/* Disabling a preset is not allowed. Call
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* dbg_grc_set_params_default instead.
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*/
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if (!val)
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return DBG_STATUS_INVALID_ARGS;
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/* Update all params with the preset values */
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for (i = 0; i < MAX_DBG_GRC_PARAMS; i++) {
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u32 preset_val;
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/* Skip persistent params */
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if (s_grc_param_defs[i].is_persistent)
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continue;
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/* Find preset value */
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if (grc_param == DBG_GRC_PARAM_EXCLUDE_ALL)
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preset_val =
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s_grc_param_defs[i].exclude_all_preset_val;
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else if (grc_param == DBG_GRC_PARAM_CRASH)
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preset_val =
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s_grc_param_defs[i].crash_preset_val;
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else
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return DBG_STATUS_INVALID_ARGS;
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qed_grc_set_param(p_hwfn,
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(enum dbg_grc_params)i, preset_val);
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}
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} else {
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/* Regular param - set its value */
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qed_grc_set_param(p_hwfn, grc_param, val);
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}
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return DBG_STATUS_OK;
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}
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/* Assign default GRC param values */
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/* Assign default GRC param values */
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void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn)
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void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn)
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{
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{
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@ -7997,9 +8069,16 @@ static u32 qed_calc_regdump_header(enum debug_print_features feature,
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int qed_dbg_all_data(struct qed_dev *cdev, void *buffer)
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int qed_dbg_all_data(struct qed_dev *cdev, void *buffer)
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{
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{
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u8 cur_engine, omit_engine = 0, org_engine;
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u8 cur_engine, omit_engine = 0, org_engine;
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struct qed_hwfn *p_hwfn =
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&cdev->hwfns[cdev->dbg_params.engine_for_debug];
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struct dbg_tools_data *dev_data = &p_hwfn->dbg_info;
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int grc_params[MAX_DBG_GRC_PARAMS], i;
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u32 offset = 0, feature_size;
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u32 offset = 0, feature_size;
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int rc;
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int rc;
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for (i = 0; i < MAX_DBG_GRC_PARAMS; i++)
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grc_params[i] = dev_data->grc.param_val[i];
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if (cdev->num_hwfns == 1)
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if (cdev->num_hwfns == 1)
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omit_engine = 1;
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omit_engine = 1;
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@ -8087,6 +8166,9 @@ int qed_dbg_all_data(struct qed_dev *cdev, void *buffer)
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rc);
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rc);
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}
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}
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for (i = 0; i < MAX_DBG_GRC_PARAMS; i++)
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dev_data->grc.param_val[i] = grc_params[i];
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/* GRC dump - must be last because when mcp stuck it will
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/* GRC dump - must be last because when mcp stuck it will
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* clutter idle_chk, reg_fifo, ...
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* clutter idle_chk, reg_fifo, ...
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*/
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*/
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@ -3024,6 +3024,21 @@ void qed_read_regs(struct qed_hwfn *p_hwfn,
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*/
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*/
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bool qed_read_fw_info(struct qed_hwfn *p_hwfn,
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bool qed_read_fw_info(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, struct fw_info *fw_info);
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struct qed_ptt *p_ptt, struct fw_info *fw_info);
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/**
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* @brief qed_dbg_grc_config - Sets the value of a GRC parameter.
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*
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* @param p_hwfn - HW device data
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* @param grc_param - GRC parameter
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* @param val - Value to set.
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*
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* @return error if one of the following holds:
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* - the version wasn't set
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* - grc_param is invalid
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* - val is outside the allowed boundaries
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*/
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enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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enum dbg_grc_params grc_param, u32 val);
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/**
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/**
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* @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
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* @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
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@ -2583,6 +2583,26 @@ static int qed_read_module_eeprom(struct qed_dev *cdev, char *buf,
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return rc;
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return rc;
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}
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}
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static int qed_set_grc_config(struct qed_dev *cdev, u32 cfg_id, u32 val)
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{
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struct qed_hwfn *hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *ptt;
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int rc = 0;
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if (IS_VF(cdev))
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return 0;
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ptt = qed_ptt_acquire(hwfn);
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if (!ptt)
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return -EAGAIN;
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rc = qed_dbg_grc_config(hwfn, ptt, cfg_id, val);
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qed_ptt_release(hwfn, ptt);
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return rc;
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}
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static u8 qed_get_affin_hwfn_idx(struct qed_dev *cdev)
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static u8 qed_get_affin_hwfn_idx(struct qed_dev *cdev)
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{
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{
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return QED_AFFIN_HWFN_IDX(cdev);
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return QED_AFFIN_HWFN_IDX(cdev);
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@ -2637,6 +2657,7 @@ const struct qed_common_ops qed_common_ops_pass = {
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.read_module_eeprom = &qed_read_module_eeprom,
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.read_module_eeprom = &qed_read_module_eeprom,
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.get_affin_hwfn_idx = &qed_get_affin_hwfn_idx,
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.get_affin_hwfn_idx = &qed_get_affin_hwfn_idx,
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.read_nvm_cfg = &qed_nvm_flash_cfg_read,
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.read_nvm_cfg = &qed_nvm_flash_cfg_read,
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.set_grc_config = &qed_set_grc_config,
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};
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};
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void qed_get_protocol_stats(struct qed_dev *cdev,
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void qed_get_protocol_stats(struct qed_dev *cdev,
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@ -1143,6 +1143,15 @@ struct qed_common_ops {
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*/
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*/
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int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
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int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
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u32 entity_id);
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u32 entity_id);
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/**
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* @brief set_grc_config - Configure value for grc config id.
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* @param cdev
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* @param cfg_id - grc config id
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* @param val - grc config value
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*
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*/
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int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val);
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};
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};
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#define MASK_FIELD(_name, _value) \
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#define MASK_FIELD(_name, _value) \
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