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gpio: ich: Add support for Intel Avoton
This patch adds support for Atom C2000 series (Avoton and Rangeley). And has the following options: - New addresses register. - Caching output levels (see Intel external design spec, table 48-29) - No hardware blink. Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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1 changed files with 25 additions and 1 deletions
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@ -1,5 +1,5 @@
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/*
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* Intel ICH6-10, Series 5 and 6 GPIO driver
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* Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
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*
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* Copyright (C) 2010 Extreme Engineering Solutions.
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*
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@ -55,6 +55,16 @@ static const u8 ichx_reglen[3] = {
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0x30, 0x10, 0x10,
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};
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static const u8 avoton_regs[4][3] = {
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{0x00, 0x80, 0x00},
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{0x04, 0x84, 0x00},
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{0x08, 0x88, 0x00},
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};
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static const u8 avoton_reglen[3] = {
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0x10, 0x10, 0x00,
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};
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#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
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#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
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@ -353,6 +363,17 @@ static struct ichx_desc intel5_desc = {
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.reglen = ichx_reglen,
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};
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/* Avoton */
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static struct ichx_desc avoton_desc = {
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/* Avoton has only 59 GPIOs, but we assume the first set of register
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* (Core) has 32 instead of 31 to keep gpio-ich compliance
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*/
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.ngpio = 60,
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.regs = avoton_regs,
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.reglen = avoton_reglen,
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.use_outlvl_cache = true,
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};
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static int ichx_gpio_request_regions(struct resource *res_base,
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const char *name, u8 use_gpio)
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{
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@ -427,6 +448,9 @@ static int ichx_gpio_probe(struct platform_device *pdev)
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case ICH_V10CONS_GPIO:
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ichx_priv.desc = &ich10_cons_desc;
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break;
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case AVOTON_GPIO:
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ichx_priv.desc = &avoton_desc;
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break;
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default:
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return -ENODEV;
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}
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