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net: dsa: mv88e6xxx: add field to specify internal phys layout 

mv88e6xxx currently assumes that switch equipped with internal phys have
those phys mapped contiguously starting from port 0 (see
mv88e6xxx_phy_is_internal). However, some switches have internal PHYs but
NOT starting from port 0. For example 88e6393X, 88E6193X and 88E6191X have
integrated PHYs available on ports 1 to 8
To properly support this offset, add a new field to allow specifying an
internal PHYs layout. If field is not set, default layout is assumed (start
at port 0)

Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Alexis Lothoré 2023-05-29 10:02:43 +02:00 committed by Jakub Kicinski
parent 7a2dd00be8
commit 3ba89b28ad
3 changed files with 12 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/net/dsa/mv88e6xxx/chip.c
View File

@ -465,7 +465,9 @@ restore_link:
static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
{
return port < chip->info->num_internal_phys;
return port >= chip->info->internal_phys_offset &&
port < chip->info->num_internal_phys +
chip->info->internal_phys_offset;
}
static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)

5
drivers/net/dsa/mv88e6xxx/chip.h
View File

@ -167,6 +167,11 @@ struct mv88e6xxx_info {
/* Supports PTP */
bool ptp_support;
/* Internal PHY start index. 0 means that internal PHYs range starts at
* port 0, 1 means internal PHYs range starts at port 1, etc
*/
unsigned int internal_phys_offset;
};
struct mv88e6xxx_atu_entry {

5
drivers/net/dsa/mv88e6xxx/global2.c
View File

@ -1196,9 +1196,12 @@ out:
int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
struct mii_bus *bus)
{
int phy_start = chip->info->internal_phys_offset;
int phy_end = chip->info->internal_phys_offset +
chip->info->num_internal_phys;
int phy, irq;
for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
for (phy = phy_start; phy < phy_end; phy++) {
irq = irq_find_mapping(chip->g2_irq.domain, phy);
if (irq < 0)
return irq;