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net: dsa: mv88e6xxx: add field to specify internal phys layout
mv88e6xxx currently assumes that switch equipped with internal phys have those phys mapped contiguously starting from port 0 (see mv88e6xxx_phy_is_internal). However, some switches have internal PHYs but NOT starting from port 0. For example 88e6393X, 88E6193X and 88E6191X have integrated PHYs available on ports 1 to 8 To properly support this offset, add a new field to allow specifying an internal PHYs layout. If field is not set, default layout is assumed (start at port 0) Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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3 changed files with 12 additions and 2 deletions
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@ -465,7 +465,9 @@ static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
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static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port)
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{
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return port < chip->info->num_internal_phys;
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return port >= chip->info->internal_phys_offset &&
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port < chip->info->num_internal_phys +
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chip->info->internal_phys_offset;
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}
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static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
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@ -167,6 +167,11 @@ struct mv88e6xxx_info {
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/* Supports PTP */
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bool ptp_support;
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/* Internal PHY start index. 0 means that internal PHYs range starts at
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* port 0, 1 means internal PHYs range starts at port 1, etc
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*/
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unsigned int internal_phys_offset;
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};
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struct mv88e6xxx_atu_entry {
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@ -1196,9 +1196,12 @@ int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
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int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
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struct mii_bus *bus)
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{
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int phy_start = chip->info->internal_phys_offset;
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int phy_end = chip->info->internal_phys_offset +
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chip->info->num_internal_phys;
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int phy, irq;
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for (phy = 0; phy < chip->info->num_internal_phys; phy++) {
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for (phy = phy_start; phy < phy_end; phy++) {
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irq = irq_find_mapping(chip->g2_irq.domain, phy);
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if (irq < 0)
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return irq;
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