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arm: zynq: Label whole PL part as fpga_full region
This will simplify dt overlay structure for the whole PL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -42,6 +42,14 @@ cpu1: cpu@1 {
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};
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};
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fpga_full: fpga-full {
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compatible = "fpga-region";
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fpga-mgr = <&devcfg>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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};
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pmu@f8891000 {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 5 4>, <0 6 4>;
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