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ARM: S3C24XX: convert s3c2412 to common clock framework
Convert all machines using these cpus to use the ccf clock driver instead of the legacy Samsung clock implementation. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
parent
ca2e90ac18
commit
3c27f314c6
9 changed files with 40 additions and 813 deletions
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@ -39,9 +39,10 @@ config CPU_S3C2410
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config CPU_S3C2412
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bool "SAMSUNG S3C2412"
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depends on SAMSUNG_CLOCK
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select COMMON_CLK
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select CPU_ARM926T
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select CPU_LLSERIAL_S3C2440
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select S3C2412_COMMON_CLK
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select S3C2412_DMA if S3C24XX_DMA
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select S3C2412_PM if PM
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help
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@ -363,6 +364,11 @@ config S3C2412_PM_SLEEP
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if CPU_S3C2412
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config S3C2412_COMMON_CLK
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bool
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help
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Build the s3c2412 clock driver based on the common clock framework.
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config CPU_S3C2412_ONLY
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bool
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depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \
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@ -21,7 +21,7 @@ obj-$(CONFIG_S3C2410_DMA) += dma-s3c2410.o
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obj-$(CONFIG_S3C2410_PLL) += pll-s3c2410.o
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obj-$(CONFIG_S3C2410_PM) += pm-s3c2410.o sleep-s3c2410.o
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obj-$(CONFIG_CPU_S3C2412) += s3c2412.o clock-s3c2412.o
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obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
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obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o
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obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o
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obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o
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@ -1,760 +0,0 @@
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/* linux/arch/arm/mach-s3c2412/clock.c
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*
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2412,S3C2413 Clock control support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/device.h>
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/serial_core.h>
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#include <linux/serial_s3c.h>
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#include <linux/io.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <mach/regs-clock.h>
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#include <mach/regs-gpio.h>
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#include <plat/clock.h>
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#include <plat/cpu.h>
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/* We currently have to assume that the system is running
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* from the XTPll input, and that all ***REFCLKs are being
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* fed from it, as we cannot read the state of OM[4] from
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* software.
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*
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* It would be possible for each board initialisation to
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* set the correct muxing at initialisation
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*/
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static int s3c2412_clkcon_enable(struct clk *clk, int enable)
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{
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unsigned int clocks = clk->ctrlbit;
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unsigned long clkcon;
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clkcon = __raw_readl(S3C2410_CLKCON);
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if (enable)
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clkcon |= clocks;
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else
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clkcon &= ~clocks;
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__raw_writel(clkcon, S3C2410_CLKCON);
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return 0;
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}
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static int s3c2412_upll_enable(struct clk *clk, int enable)
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{
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unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
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unsigned long orig = upllcon;
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if (!enable)
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upllcon |= S3C2412_PLLCON_OFF;
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else
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upllcon &= ~S3C2412_PLLCON_OFF;
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__raw_writel(upllcon, S3C2410_UPLLCON);
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/* allow ~150uS for the PLL to settle and lock */
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if (enable && (orig & S3C2412_PLLCON_OFF))
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udelay(150);
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return 0;
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}
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/* clock selections */
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static struct clk clk_erefclk = {
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.name = "erefclk",
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};
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static struct clk clk_urefclk = {
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.name = "urefclk",
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};
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static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
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{
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unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
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if (parent == &clk_urefclk)
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clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
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else if (parent == &clk_upll)
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clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
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else
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return -EINVAL;
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clk->parent = parent;
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__raw_writel(clksrc, S3C2412_CLKSRC);
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return 0;
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}
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static struct clk clk_usysclk = {
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.name = "usysclk",
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.parent = &clk_xtal,
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.ops = &(struct clk_ops) {
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.set_parent = s3c2412_setparent_usysclk,
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},
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};
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static struct clk clk_mrefclk = {
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.name = "mrefclk",
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.parent = &clk_xtal,
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};
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static struct clk clk_mdivclk = {
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.name = "mdivclk",
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.parent = &clk_xtal,
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};
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static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
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{
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unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
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if (parent == &clk_usysclk)
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clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
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else if (parent == &clk_h)
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clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
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else
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return -EINVAL;
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clk->parent = parent;
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__raw_writel(clksrc, S3C2412_CLKSRC);
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return 0;
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}
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static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
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unsigned long rate)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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int div;
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if (rate > parent_rate)
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return parent_rate;
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div = parent_rate / rate;
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if (div > 2)
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div = 2;
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return parent_rate / div;
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}
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static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long div = __raw_readl(S3C2410_CLKDIVN);
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return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
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}
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static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
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rate = s3c2412_roundrate_usbsrc(clk, rate);
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if ((parent_rate / rate) == 2)
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clkdivn |= S3C2412_CLKDIVN_USB48DIV;
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else
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clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
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__raw_writel(clkdivn, S3C2410_CLKDIVN);
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return 0;
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}
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static struct clk clk_usbsrc = {
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.name = "usbsrc",
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.ops = &(struct clk_ops) {
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.get_rate = s3c2412_getrate_usbsrc,
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.set_rate = s3c2412_setrate_usbsrc,
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.round_rate = s3c2412_roundrate_usbsrc,
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.set_parent = s3c2412_setparent_usbsrc,
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},
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};
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static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
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{
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unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
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if (parent == &clk_mdivclk)
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clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
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else if (parent == &clk_mpll)
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clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
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else
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return -EINVAL;
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clk->parent = parent;
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__raw_writel(clksrc, S3C2412_CLKSRC);
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return 0;
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}
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static struct clk clk_msysclk = {
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.name = "msysclk",
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.ops = &(struct clk_ops) {
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.set_parent = s3c2412_setparent_msysclk,
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},
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};
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static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
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{
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unsigned long flags;
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unsigned long clkdiv;
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unsigned long dvs;
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/* Note, we current equate fclk andf msysclk for S3C2412 */
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if (parent == &clk_msysclk || parent == &clk_f)
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dvs = 0;
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else if (parent == &clk_h)
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dvs = S3C2412_CLKDIVN_DVSEN;
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else
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return -EINVAL;
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clk->parent = parent;
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/* update this under irq lockdown, clkdivn is not protected
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* by the clock system. */
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local_irq_save(flags);
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clkdiv = __raw_readl(S3C2410_CLKDIVN);
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clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
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clkdiv |= dvs;
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__raw_writel(clkdiv, S3C2410_CLKDIVN);
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local_irq_restore(flags);
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return 0;
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}
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static struct clk clk_armclk = {
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.name = "armclk",
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.parent = &clk_msysclk,
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.ops = &(struct clk_ops) {
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.set_parent = s3c2412_setparent_armclk,
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},
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};
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/* these next clocks have an divider immediately after them,
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* so we can register them with their divider and leave out the
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* intermediate clock stage
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*/
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static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
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unsigned long rate)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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int div;
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if (rate > parent_rate)
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return parent_rate;
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/* note, we remove the +/- 1 calculations as they cancel out */
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div = (rate / parent_rate);
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if (div < 1)
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div = 1;
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else if (div > 16)
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div = 16;
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return parent_rate / div;
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}
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static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
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{
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unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
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if (parent == &clk_erefclk)
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clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
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else if (parent == &clk_mpll)
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clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
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else
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return -EINVAL;
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clk->parent = parent;
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__raw_writel(clksrc, S3C2412_CLKSRC);
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return 0;
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}
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static unsigned long s3c2412_getrate_uart(struct clk *clk)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long div = __raw_readl(S3C2410_CLKDIVN);
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div &= S3C2412_CLKDIVN_UARTDIV_MASK;
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div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
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return parent_rate / (div + 1);
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}
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static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
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rate = s3c2412_roundrate_clksrc(clk, rate);
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clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
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clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
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__raw_writel(clkdivn, S3C2410_CLKDIVN);
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return 0;
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}
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static struct clk clk_uart = {
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.name = "uartclk",
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.ops = &(struct clk_ops) {
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.get_rate = s3c2412_getrate_uart,
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.set_rate = s3c2412_setrate_uart,
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.set_parent = s3c2412_setparent_uart,
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.round_rate = s3c2412_roundrate_clksrc,
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},
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};
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static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
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{
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unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
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if (parent == &clk_erefclk)
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clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
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else if (parent == &clk_mpll)
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clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
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else
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return -EINVAL;
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clk->parent = parent;
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__raw_writel(clksrc, S3C2412_CLKSRC);
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return 0;
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}
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static unsigned long s3c2412_getrate_i2s(struct clk *clk)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long div = __raw_readl(S3C2410_CLKDIVN);
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div &= S3C2412_CLKDIVN_I2SDIV_MASK;
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div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
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return parent_rate / (div + 1);
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}
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static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
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rate = s3c2412_roundrate_clksrc(clk, rate);
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clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
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clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
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__raw_writel(clkdivn, S3C2410_CLKDIVN);
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return 0;
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}
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static struct clk clk_i2s = {
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.name = "i2sclk",
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.ops = &(struct clk_ops) {
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.get_rate = s3c2412_getrate_i2s,
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.set_rate = s3c2412_setrate_i2s,
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.set_parent = s3c2412_setparent_i2s,
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.round_rate = s3c2412_roundrate_clksrc,
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},
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};
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static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
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{
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unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
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if (parent == &clk_usysclk)
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clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
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else if (parent == &clk_h)
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clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
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else
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return -EINVAL;
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clk->parent = parent;
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__raw_writel(clksrc, S3C2412_CLKSRC);
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return 0;
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}
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static unsigned long s3c2412_getrate_cam(struct clk *clk)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long div = __raw_readl(S3C2410_CLKDIVN);
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div &= S3C2412_CLKDIVN_CAMDIV_MASK;
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div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
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return parent_rate / (div + 1);
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}
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static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
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{
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unsigned long parent_rate = clk_get_rate(clk->parent);
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unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
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rate = s3c2412_roundrate_clksrc(clk, rate);
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||||
clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
|
||||
clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
|
||||
|
||||
__raw_writel(clkdivn, S3C2410_CLKDIVN);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct clk clk_cam = {
|
||||
.name = "camif-upll", /* same as 2440 name */
|
||||
.ops = &(struct clk_ops) {
|
||||
.get_rate = s3c2412_getrate_cam,
|
||||
.set_rate = s3c2412_setrate_cam,
|
||||
.set_parent = s3c2412_setparent_cam,
|
||||
.round_rate = s3c2412_roundrate_clksrc,
|
||||
},
|
||||
};
|
||||
|
||||
/* standard clock definitions */
|
||||
|
||||
static struct clk init_clocks_disable[] = {
|
||||
{
|
||||
.name = "nand",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_NAND,
|
||||
}, {
|
||||
.name = "sdi",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_SDI,
|
||||
}, {
|
||||
.name = "adc",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_ADC,
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_IIC,
|
||||
}, {
|
||||
.name = "iis",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_IIS,
|
||||
}, {
|
||||
.name = "spi",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_SPI,
|
||||
}
|
||||
};
|
||||
|
||||
static struct clk init_clocks[] = {
|
||||
{
|
||||
.name = "dma.0",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_DMA0,
|
||||
}, {
|
||||
.name = "dma.1",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_DMA1,
|
||||
}, {
|
||||
.name = "dma.2",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_DMA2,
|
||||
}, {
|
||||
.name = "dma.3",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_DMA3,
|
||||
}, {
|
||||
.name = "lcd",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_LCDC,
|
||||
}, {
|
||||
.name = "gpio",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_GPIO,
|
||||
}, {
|
||||
.name = "usb-host",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_USBH,
|
||||
}, {
|
||||
.name = "usb-device",
|
||||
.parent = &clk_h,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_USBD,
|
||||
}, {
|
||||
.name = "timers",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_PWMT,
|
||||
}, {
|
||||
.name = "uart",
|
||||
.devname = "s3c2412-uart.0",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_UART0,
|
||||
}, {
|
||||
.name = "uart",
|
||||
.devname = "s3c2412-uart.1",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_UART1,
|
||||
}, {
|
||||
.name = "uart",
|
||||
.devname = "s3c2412-uart.2",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_UART2,
|
||||
}, {
|
||||
.name = "rtc",
|
||||
.parent = &clk_p,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_RTC,
|
||||
}, {
|
||||
.name = "watchdog",
|
||||
.parent = &clk_p,
|
||||
.ctrlbit = 0,
|
||||
}, {
|
||||
.name = "usb-bus-gadget",
|
||||
.parent = &clk_usb_bus,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_USB_DEV48,
|
||||
}, {
|
||||
.name = "usb-bus-host",
|
||||
.parent = &clk_usb_bus,
|
||||
.enable = s3c2412_clkcon_enable,
|
||||
.ctrlbit = S3C2412_CLKCON_USB_HOST48,
|
||||
}
|
||||
};
|
||||
|
||||
/* clocks to add where we need to check their parentage */
|
||||
|
||||
struct clk_init {
|
||||
struct clk *clk;
|
||||
unsigned int bit;
|
||||
struct clk *src_0;
|
||||
struct clk *src_1;
|
||||
};
|
||||
|
||||
static struct clk_init clks_src[] __initdata = {
|
||||
{
|
||||
.clk = &clk_usysclk,
|
||||
.bit = S3C2412_CLKSRC_USBCLK_HCLK,
|
||||
.src_0 = &clk_urefclk,
|
||||
.src_1 = &clk_upll,
|
||||
}, {
|
||||
.clk = &clk_i2s,
|
||||
.bit = S3C2412_CLKSRC_I2SCLK_MPLL,
|
||||
.src_0 = &clk_erefclk,
|
||||
.src_1 = &clk_mpll,
|
||||
}, {
|
||||
.clk = &clk_cam,
|
||||
.bit = S3C2412_CLKSRC_CAMCLK_HCLK,
|
||||
.src_0 = &clk_usysclk,
|
||||
.src_1 = &clk_h,
|
||||
}, {
|
||||
.clk = &clk_msysclk,
|
||||
.bit = S3C2412_CLKSRC_MSYSCLK_MPLL,
|
||||
.src_0 = &clk_mdivclk,
|
||||
.src_1 = &clk_mpll,
|
||||
}, {
|
||||
.clk = &clk_uart,
|
||||
.bit = S3C2412_CLKSRC_UARTCLK_MPLL,
|
||||
.src_0 = &clk_erefclk,
|
||||
.src_1 = &clk_mpll,
|
||||
}, {
|
||||
.clk = &clk_usbsrc,
|
||||
.bit = S3C2412_CLKSRC_USBCLK_HCLK,
|
||||
.src_0 = &clk_usysclk,
|
||||
.src_1 = &clk_h,
|
||||
/* here we assume OM[4] select xtal */
|
||||
}, {
|
||||
.clk = &clk_erefclk,
|
||||
.bit = S3C2412_CLKSRC_EREFCLK_EXTCLK,
|
||||
.src_0 = &clk_xtal,
|
||||
.src_1 = &clk_ext,
|
||||
}, {
|
||||
.clk = &clk_urefclk,
|
||||
.bit = S3C2412_CLKSRC_UREFCLK_EXTCLK,
|
||||
.src_0 = &clk_xtal,
|
||||
.src_1 = &clk_ext,
|
||||
},
|
||||
};
|
||||
|
||||
/* s3c2412_clk_initparents
|
||||
*
|
||||
* Initialise the parents for the clocks that we get at start-time
|
||||
*/
|
||||
|
||||
static void __init s3c2412_clk_initparents(void)
|
||||
{
|
||||
unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
|
||||
struct clk_init *cip = clks_src;
|
||||
struct clk *src;
|
||||
int ptr;
|
||||
int ret;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
|
||||
ret = s3c24xx_register_clock(cip->clk);
|
||||
if (ret < 0) {
|
||||
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
||||
cip->clk->name, ret);
|
||||
}
|
||||
|
||||
src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
|
||||
|
||||
printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
|
||||
clk_set_parent(cip->clk, src);
|
||||
}
|
||||
}
|
||||
|
||||
/* clocks to add straight away */
|
||||
|
||||
static struct clk *clks[] __initdata = {
|
||||
&clk_ext,
|
||||
&clk_usb_bus,
|
||||
&clk_mrefclk,
|
||||
&clk_armclk,
|
||||
};
|
||||
|
||||
static struct clk_lookup s3c2412_clk_lookup[] = {
|
||||
CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
|
||||
CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
|
||||
CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
|
||||
};
|
||||
|
||||
int __init s3c2412_baseclk_add(void)
|
||||
{
|
||||
unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
|
||||
unsigned int dvs;
|
||||
struct clk *clkp;
|
||||
int ret;
|
||||
int ptr;
|
||||
|
||||
clk_upll.enable = s3c2412_upll_enable;
|
||||
clk_usb_bus.parent = &clk_usbsrc;
|
||||
clk_usb_bus.rate = 0x0;
|
||||
|
||||
clk_f.parent = &clk_msysclk;
|
||||
|
||||
s3c2412_clk_initparents();
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
|
||||
clkp = clks[ptr];
|
||||
|
||||
ret = s3c24xx_register_clock(clkp);
|
||||
if (ret < 0) {
|
||||
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
||||
clkp->name, ret);
|
||||
}
|
||||
}
|
||||
|
||||
/* set the dvs state according to what we got at boot time */
|
||||
|
||||
dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
|
||||
|
||||
if (dvs)
|
||||
clk_armclk.parent = &clk_h;
|
||||
|
||||
printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
|
||||
|
||||
/* ensure usb bus clock is within correct rate of 48MHz */
|
||||
|
||||
if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
|
||||
printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
|
||||
|
||||
/* for the moment, let's use the UPLL, and see if we can
|
||||
* get 48MHz */
|
||||
|
||||
clk_set_parent(&clk_usysclk, &clk_upll);
|
||||
clk_set_parent(&clk_usbsrc, &clk_usysclk);
|
||||
clk_set_rate(&clk_usbsrc, 48*1000*1000);
|
||||
}
|
||||
|
||||
printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
|
||||
(__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
|
||||
print_mhz(clk_get_rate(&clk_upll)),
|
||||
print_mhz(clk_get_rate(&clk_usb_bus)));
|
||||
|
||||
/* register clocks from clock array */
|
||||
|
||||
clkp = init_clocks;
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
|
||||
/* ensure that we note the clock state */
|
||||
|
||||
clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
|
||||
|
||||
ret = s3c24xx_register_clock(clkp);
|
||||
if (ret < 0) {
|
||||
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
||||
clkp->name, ret);
|
||||
}
|
||||
}
|
||||
|
||||
/* We must be careful disabling the clocks we are not intending to
|
||||
* be using at boot time, as subsystems such as the LCD which do
|
||||
* their own DMA requests to the bus can cause the system to lockup
|
||||
* if they where in the middle of requesting bus access.
|
||||
*
|
||||
* Disabling the LCD clock if the LCD is active is very dangerous,
|
||||
* and therefore the bootloader should be careful to not enable
|
||||
* the LCD clock if it is not needed.
|
||||
*/
|
||||
|
||||
/* install (and disable) the clocks we do not need immediately */
|
||||
|
||||
clkp = init_clocks_disable;
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
|
||||
|
||||
ret = s3c24xx_register_clock(clkp);
|
||||
if (ret < 0) {
|
||||
printk(KERN_ERR "Failed to register clock %s (%d)\n",
|
||||
clkp->name, ret);
|
||||
}
|
||||
|
||||
s3c2412_clkcon_enable(clkp, 0);
|
||||
}
|
||||
|
||||
clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
|
||||
return 0;
|
||||
}
|
|
@ -127,7 +127,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = 0x32412001,
|
||||
.idmask = 0xffffffff,
|
||||
.map_io = s3c2412_map_io,
|
||||
.init_clocks = s3c2412_init_clocks,
|
||||
.init_uarts = s3c2412_init_uarts,
|
||||
.init = s3c2412_init,
|
||||
.name = name_s3c2412,
|
||||
|
@ -136,7 +135,6 @@ static struct cpu_table cpu_ids[] __initdata = {
|
|||
.idcode = 0x32412003,
|
||||
.idmask = 0xffffffff,
|
||||
.map_io = s3c2412_map_io,
|
||||
.init_clocks = s3c2412_init_clocks,
|
||||
.init_uarts = s3c2412_init_uarts,
|
||||
.init = s3c2412_init,
|
||||
.name = name_s3c2412,
|
||||
|
@ -535,6 +533,13 @@ struct platform_device s3c2443_device_dma = {
|
|||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2412
|
||||
void __init s3c2412_init_clocks(int xtal)
|
||||
{
|
||||
s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2416
|
||||
void __init s3c2416_init_clocks(int xtal)
|
||||
{
|
||||
|
|
|
@ -114,6 +114,10 @@ extern struct platform_device s3c2412_device_dma;
|
|||
extern struct platform_device s3c2440_device_dma;
|
||||
extern struct platform_device s3c2443_device_dma;
|
||||
|
||||
#ifdef CONFIG_S3C2412_COMMON_CLK
|
||||
void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
|
||||
unsigned long ext_f, void __iomem *reg_base);
|
||||
#endif
|
||||
#ifdef CONFIG_S3C2443_COMMON_CLK
|
||||
void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
|
||||
int current_soc,
|
||||
|
|
|
@ -507,11 +507,16 @@ static struct syscore_ops jive_pm_syscore_ops = {
|
|||
static void __init jive_map_io(void)
|
||||
{
|
||||
s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init jive_init_time(void)
|
||||
{
|
||||
s3c2412_init_clocks(12000000);
|
||||
samsung_timer_init();
|
||||
}
|
||||
|
||||
static void jive_power_off(void)
|
||||
{
|
||||
printk(KERN_INFO "powering system down...\n");
|
||||
|
@ -665,6 +670,6 @@ MACHINE_START(JIVE, "JIVE")
|
|||
.init_irq = s3c2412_init_irq,
|
||||
.map_io = jive_map_io,
|
||||
.init_machine = jive_machine_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.init_time = jive_init_time,
|
||||
.restart = s3c2412_restart,
|
||||
MACHINE_END
|
||||
|
|
|
@ -106,11 +106,16 @@ static void __init smdk2413_fixup(struct tag *tags, char **cmdline,
|
|||
static void __init smdk2413_map_io(void)
|
||||
{
|
||||
s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init smdk2413_init_time(void)
|
||||
{
|
||||
s3c2412_init_clocks(12000000);
|
||||
samsung_timer_init();
|
||||
}
|
||||
|
||||
static void __init smdk2413_machine_init(void)
|
||||
{ /* Turn off suspend on both USB ports, and switch the
|
||||
* selectable USB port to USB device mode. */
|
||||
|
@ -159,6 +164,6 @@ MACHINE_START(SMDK2413, "SMDK2413")
|
|||
.init_irq = s3c2412_init_irq,
|
||||
.map_io = smdk2413_map_io,
|
||||
.init_machine = smdk2413_machine_init,
|
||||
.init_time = samsung_timer_init,
|
||||
.init_time = smdk2413_init_time,
|
||||
.restart = s3c2412_restart,
|
||||
MACHINE_END
|
||||
|
|
|
@ -142,11 +142,16 @@ static void __init vstms_fixup(struct tag *tags, char **cmdline,
|
|||
static void __init vstms_map_io(void)
|
||||
{
|
||||
s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
||||
static void __init vstms_init_time(void)
|
||||
{
|
||||
s3c2412_init_clocks(12000000);
|
||||
samsung_timer_init();
|
||||
}
|
||||
|
||||
static void __init vstms_init(void)
|
||||
{
|
||||
s3c_i2c0_set_platdata(NULL);
|
||||
|
@ -162,6 +167,6 @@ MACHINE_START(VSTMS, "VSTMS")
|
|||
.init_irq = s3c2412_init_irq,
|
||||
.init_machine = vstms_init,
|
||||
.map_io = vstms_map_io,
|
||||
.init_time = samsung_timer_init,
|
||||
.init_time = vstms_init_time,
|
||||
.restart = s3c2412_restart,
|
||||
MACHINE_END
|
||||
|
|
|
@ -173,49 +173,6 @@ void __init s3c2412_map_io(void)
|
|||
|
||||
void __init_or_cpufreq s3c2412_setup_clocks(void)
|
||||
{
|
||||
struct clk *xtal_clk;
|
||||
unsigned long tmp;
|
||||
unsigned long xtal;
|
||||
unsigned long fclk;
|
||||
unsigned long hclk;
|
||||
unsigned long pclk;
|
||||
|
||||
xtal_clk = clk_get(NULL, "xtal");
|
||||
xtal = clk_get_rate(xtal_clk);
|
||||
clk_put(xtal_clk);
|
||||
|
||||
/* now we've got our machine bits initialised, work out what
|
||||
* clocks we've got */
|
||||
|
||||
fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
|
||||
|
||||
clk_mpll.rate = fclk;
|
||||
|
||||
tmp = __raw_readl(S3C2410_CLKDIVN);
|
||||
|
||||
/* work out clock scalings */
|
||||
|
||||
hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
|
||||
hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
|
||||
pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
|
||||
|
||||
/* print brieft summary of clocks, etc */
|
||||
|
||||
printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
|
||||
print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
|
||||
|
||||
s3c24xx_setup_clocks(fclk, hclk, pclk);
|
||||
}
|
||||
|
||||
void __init s3c2412_init_clocks(int xtal)
|
||||
{
|
||||
/* initialise the clocks here, to allow other things like the
|
||||
* console to use them
|
||||
*/
|
||||
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s3c2412_setup_clocks();
|
||||
s3c2412_baseclk_add();
|
||||
}
|
||||
|
||||
/* need to register the subsystem before we actually register the device, and
|
||||
|
|
Loading…
Reference in a new issue