From 3813a10a5a70f3bb38272f3d8473baf909af0a99 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Wed, 29 Nov 2017 15:35:41 -0800 Subject: [PATCH 01/12] arm64: dts: rockchip: add rk3399 DSI0 reset We've documented this one already, but we didn't add it to the DTSI yet. Suggested-by: Nickey Yang Signed-off-by: Brian Norris Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index d340b58ab184..faf8c90bdc1a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1648,6 +1648,8 @@ mipi_dsi: mipi@ff960000 { <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; clock-names = "ref", "pclk", "phy_cfg", "grf"; power-domains = <&power RK3399_PD_VIO>; + resets = <&cru SRST_P_MIPI_DSI0>; + reset-names = "apb"; rockchip,grf = <&grf>; status = "disabled"; From 1df5d2ab16fb63cd16ae3e85561ded5d251eb0e5 Mon Sep 17 00:00:00 2001 From: Nickey Yang Date: Wed, 29 Nov 2017 17:11:27 -0800 Subject: [PATCH 02/12] arm64: dts: rockchip: add mipi_dsi1 support for rk3399 This patch adds the information for the secondary MIPI DSI controller, e.g., interrupts, grf, clocks, ports and so on. Mirrors the existing definition for dsi0. Signed-off-by: Nickey Yang Signed-off-by: Brian Norris Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 45 ++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index faf8c90bdc1a..33e6a6d73c1c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1526,6 +1526,11 @@ vopl_out_hdmi: endpoint@2 { reg = <2>; remote-endpoint = <&hdmi_in_vopl>; }; + + vopl_out_mipi1: endpoint@3 { + reg = <3>; + remote-endpoint = <&mipi1_in_vopl>; + }; }; }; @@ -1573,6 +1578,11 @@ vopb_out_hdmi: endpoint@2 { reg = <2>; remote-endpoint = <&hdmi_in_vopb>; }; + + vopb_out_mipi1: endpoint@3 { + reg = <3>; + remote-endpoint = <&mipi1_in_vopb>; + }; }; }; @@ -1670,6 +1680,41 @@ mipi_in_vopl: endpoint@1 { }; }; + mipi_dsi1: mipi@ff968000 { + compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xff968000 0x0 0x8000>; + interrupts = ; + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, + <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; + clock-names = "ref", "pclk", "phy_cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + resets = <&cru SRST_P_MIPI_DSI1>; + reset-names = "apb"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_mipi1>; + }; + + mipi1_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_mipi1>; + }; + }; + }; + }; + edp: edp@ff970000 { compatible = "rockchip,rk3399-edp"; reg = <0x0 0xff970000 0x0 0x8000>; From c856cb5d4b6a6d269d8b817f1068325150f69fdb Mon Sep 17 00:00:00 2001 From: Nickey Yang Date: Wed, 29 Nov 2017 10:47:55 -0800 Subject: [PATCH 03/12] arm64: dts: rockchip: update mipi cells for RK3399 We might include additional ports in derivative device trees, so the 'port' node should have an address, and the parent 'ports' node needs /#{addres,size}-cells. Signed-off-by: Nickey Yang Signed-off-by: Brian Norris Reviewed-by: Douglas Anderson Reviewed-by: Laurent Pinchart Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 33e6a6d73c1c..e7e882d06c68 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1664,7 +1664,11 @@ mipi_dsi: mipi@ff960000 { status = "disabled"; ports { - mipi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: port@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; From 926be875fb4811f92228c8332822bd26cb0def93 Mon Sep 17 00:00:00 2001 From: Jeffy Chen Date: Thu, 19 Oct 2017 11:48:03 +0800 Subject: [PATCH 04/12] arm64: dts: rockchip: Enable edp disaplay on kevin Add edp panel and enable related nodes on kevin. Signed-off-by: Jeffy Chen Reviewed-by: Mark Yao Tested-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-gru-kevin.dts | 29 +++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 16 ++++++++++ 2 files changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts index 0384e3121f18..191a6bcb1704 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts @@ -93,6 +93,18 @@ backlight: backlight { pwm-delay-us = <10000>; }; + edp_panel: edp-panel { + compatible = "sharp,lq123p1jx31", "simple-panel"; + backlight = <&backlight>; + power-supply = <&pp3300_disp>; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + thermistor_ppvar_bigcpu: thermistor-ppvar-bigcpu { compatible = "murata,ncp15wb473"; pullup-uv = <1800000>; @@ -268,6 +280,23 @@ touchscreen@4b { }; }; +&edp { + status = "okay"; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + &ppvar_bigcpu_pwm { regulator-min-microvolt = <798674>; regulator-max-microvolt = <1302172>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 5772c52fbfd3..470105d651c2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -927,6 +927,22 @@ &usbdrd_dwc3_1 { dr_mode = "host"; }; +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + #include #include From a1bbaaa42bbd4d6692d31cfe0e8b7497d7ceb7a3 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 15 Dec 2017 12:00:04 +0100 Subject: [PATCH 05/12] arm64: dts: rockchip: add pd_usb3 power-domain node for rk3399 Add the usb3 power-domain, its qos area and assign it to the usb device node. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index e7e882d06c68..76512667ff32 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -415,6 +415,7 @@ usbdrd_dwc3_0: dwc3 { snps,dis_u2_susphy_quirk; snps,dis-del-phy-power-chg-quirk; snps,dis-tx-ipgap-linecheck-quirk; + power-domains = <&power RK3399_PD_USB3>; status = "disabled"; }; }; @@ -443,6 +444,7 @@ usbdrd_dwc3_1: dwc3 { snps,dis_u2_susphy_quirk; snps,dis-del-phy-power-chg-quirk; snps,dis-tx-ipgap-linecheck-quirk; + power-domains = <&power RK3399_PD_USB3>; status = "disabled"; }; }; @@ -991,6 +993,12 @@ pd_sdioaudio@RK3399_PD_SDIOAUDIO { clocks = <&cru HCLK_SDIO>; pm_qos = <&qos_sdioaudio>; }; + pd_usb3@RK3399_PD_USB3 { + reg = ; + clocks = <&cru ACLK_USB3>; + pm_qos = <&qos_usb_otg0>, + <&qos_usb_otg1>; + }; pd_vio@RK3399_PD_VIO { reg = ; #address-cells = <1>; From 9df8a2d91216bbf04583ddfb5bf6657142302bab Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 15 Dec 2017 12:00:02 +0100 Subject: [PATCH 06/12] arm64: dts: rockchip: add the aclk_usb3 clocks for USB3 on rk3399 The aclk_usb3 must be enabled to support USB3 for rk3399. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 76512667ff32..6dacc0a4f43a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -397,9 +397,11 @@ usbdrd3_0: usb@fe800000 { #size-cells = <2>; ranges; clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, - <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>; + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; clock-names = "ref_clk", "suspend_clk", - "bus_clk", "grf_clk"; + "bus_clk", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "grf_clk"; status = "disabled"; usbdrd_dwc3_0: dwc3 { @@ -426,9 +428,11 @@ usbdrd3_1: usb@fe900000 { #size-cells = <2>; ranges; clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, - <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>; + <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; clock-names = "ref_clk", "suspend_clk", - "bus_clk", "grf_clk"; + "bus_clk", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "grf_clk"; status = "disabled"; usbdrd_dwc3_1: dwc3 { From b7e63d95c14dcc264f9d7cedf46a3fd197db65f8 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 15 Dec 2017 12:00:05 +0100 Subject: [PATCH 07/12] arm64: dts: rockchip: add reset property for dwc3 controllers on rk3399 After commit '06c47e6286d usb: dwc3: of-simple: Add support to get resets for the device' you can add the reset property to the dwc3 node, the reset is required for the controller to work properly, otherwise bind / unbind stress testing of the USB controller on rk3399 we'd often end up with lots of failures that looked like this: phy phy-ff800000.phy.9: phy poweron failed --> -110 dwc3 fe900000.dwc3: failed to initialize core dwc3: probe of fe900000.dwc3 failed with error -110 Signed-off-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 6dacc0a4f43a..b4511503878b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -402,6 +402,8 @@ usbdrd3_0: usb@fe800000 { clock-names = "ref_clk", "suspend_clk", "bus_clk", "aclk_usb3_rksoc_axi_perf", "aclk_usb3", "grf_clk"; + resets = <&cru SRST_A_USB3_OTG0>; + reset-names = "usb3-otg"; status = "disabled"; usbdrd_dwc3_0: dwc3 { @@ -433,6 +435,8 @@ usbdrd3_1: usb@fe900000 { clock-names = "ref_clk", "suspend_clk", "bus_clk", "aclk_usb3_rksoc_axi_perf", "aclk_usb3", "grf_clk"; + resets = <&cru SRST_A_USB3_OTG1>; + reset-names = "usb3-otg"; status = "disabled"; usbdrd_dwc3_1: dwc3 { From c301b327aea898af558b2387252a2f5fc0117dee Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 15 Dec 2017 12:00:03 +0100 Subject: [PATCH 08/12] arm64: dts: rockchip: add usb3-phy otg-port support for rk3399 Add the usb3 phyter for the USB3.0 OTG controller. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index b4511503878b..7aa2144e0d47 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -411,8 +411,8 @@ usbdrd_dwc3_0: dwc3 { reg = <0x0 0xfe800000 0x0 0x100000>; interrupts = ; dr_mode = "otg"; - phys = <&u2phy0_otg>; - phy-names = "usb2-phy"; + phys = <&u2phy0_otg>, <&tcphy0_usb3>; + phy-names = "usb2-phy", "usb3-phy"; phy_type = "utmi_wide"; snps,dis_enblslpm_quirk; snps,dis-u2-freeclk-exists-quirk; @@ -444,8 +444,8 @@ usbdrd_dwc3_1: dwc3 { reg = <0x0 0xfe900000 0x0 0x100000>; interrupts = ; dr_mode = "otg"; - phys = <&u2phy1_otg>; - phy-names = "usb2-phy"; + phys = <&u2phy1_otg>, <&tcphy1_usb3>; + phy-names = "usb2-phy", "usb3-phy"; phy_type = "utmi_wide"; snps,dis_enblslpm_quirk; snps,dis-u2-freeclk-exists-quirk; From cea5735c934f64a1659be7ea27c5848190c6c15a Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 15 Dec 2017 12:00:01 +0100 Subject: [PATCH 09/12] arm64: dts: rockchip: add extcon nodes and enable tcphy rk3399-gru Enable tcphy and create the cros-ec's extcon node for the USB Type-C port. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Brian Norris Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 26 ++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 470105d651c2..03f195025390 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -855,6 +855,20 @@ cros_ec_pwm: ec-pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; }; + + usbc_extcon0: extcon@0 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <0>; + + #extcon-cells = <0>; + }; + + usbc_extcon1: extcon@1 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <1>; + + #extcon-cells = <0>; + }; }; }; @@ -865,6 +879,16 @@ &tsadc { rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ }; +&tcphy0 { + status = "okay"; + extcon = <&usbc_extcon0>; +}; + +&tcphy1 { + status = "okay"; + extcon = <&usbc_extcon1>; +}; + &u2phy0 { status = "okay"; }; @@ -911,6 +935,7 @@ &usb_host1_ohci { &usbdrd3_0 { status = "okay"; + extcon = <&usbc_extcon0>; }; &usbdrd_dwc3_0 { @@ -920,6 +945,7 @@ &usbdrd_dwc3_0 { &usbdrd3_1 { status = "okay"; + extcon = <&usbc_extcon1>; }; &usbdrd_dwc3_1 { From c10e65b5874fe08643e40bf8d4d80627cc5e5da5 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 8 Dec 2017 22:44:11 +0100 Subject: [PATCH 10/12] dt-bindings: gpu: mali-utgard: add rockchip,rk3328-mali compatible The rk3328 quad-core Cortex A53 uses a Mali-450MP2 with 2 PPs, so add a compatible for it. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index c6814d7cc2b2..ad876548ab5d 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -17,6 +17,7 @@ Required properties: + rockchip,rk3066-mali + rockchip,rk3188-mali + rockchip,rk3228-mali + + rockchip,rk3328-mali + stericsson,db8500-mali - reg: Physical base address and length of the GPU registers From 752fbc0c8da7403e75cf49bfb6432d474aeeaefa Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Fri, 8 Dec 2017 22:46:45 +0100 Subject: [PATCH 11/12] arm64: dts: rockchip: add rk3328 mali gpu node Add the core gpu node for the rk3328, a Mali450MP2. Signed-off-by: Heiko Stuebner Reviewed-by: Rob Herring --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 41d61840fb99..48f8d4fc34a3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -543,6 +543,28 @@ saradc: adc@ff280000 { status = "disabled"; }; + gpu: gpu@ff300000 { + compatible = "rockchip,rk3328-mali", "arm,mali-450"; + reg = <0x0 0xff300000 0x0 0x40000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1"; + clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; + clock-names = "bus", "core"; + resets = <&cru SRST_GPU_A>; + }; + h265e_mmu: iommu@ff330200 { compatible = "rockchip,iommu"; reg = <0x0 0xff330200 0 0x100>; From 13bc2c0a6a14f430abaa6a859792418644b7febd Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Fri, 4 Aug 2017 11:33:38 +0800 Subject: [PATCH 12/12] arm64: dts: rockchip: Add efuse device node for RK3328 SoC This patch adds an efuse node in the device tree for rk3228 SoC. Signed-off-by: Finley Xiao Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index 48f8d4fc34a3..8f84e5a1c43c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -531,6 +531,31 @@ tsadc: tsadc@ff250000 { status = "disabled"; }; + efuse: efuse@ff260000 { + compatible = "rockchip,rk3328-efuse"; + reg = <0x0 0xff260000 0x0 0x50>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru SCLK_EFUSE>; + clock-names = "pclk_efuse"; + rockchip,efuse-size = <0x20>; + + /* Data cells */ + efuse_id: id@7 { + reg = <0x07 0x10>; + }; + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + logic_leakage: logic-leakage@19 { + reg = <0x19 0x1>; + }; + efuse_cpu_version: cpu-version@1a { + reg = <0x1a 0x1>; + bits = <3 3>; + }; + }; + saradc: adc@ff280000 { compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; reg = <0x0 0xff280000 0x0 0x100>;