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drm/i915/dg2: Tile 4 plane format support
TileF(Tile4 in bspec) format is 4K tile organized into 64B subtiles with same basic shape as for legacy TileY which will be supported by Display13. v2: - Fixed wrong case condition(Jani Nikula) - Increased I915_FORMAT_MOD_F_TILED up to 12(Imre Deak) v3: - s/I915_TILING_F/TILING_4/g - s/I915_FORMAT_MOD_F_TILED/I915_FORMAT_MOD_4_TILED/g - Removed unneeded fencing code v4: - Rebased, fixed merge conflict with new table-oriented format modifier checking(Stan) - Replaced the rest of "Tile F" mentions to "Tile 4"(Stan) v5: - Still had to remove some Tile F mentionings - Moved has_4tile from adlp to DG2(Ramalingam C) - Check specifically for DG2, but not the Display13(Imre) v6: - Moved Tile4 associating struct for modifier/display to the beginning(Imre Deak) - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier checks(Imre Deak) - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12 (Imre Deak) v7: - Fixed display_ver to { 13, 13 }(Imre Deak) - Removed redundant newline(Imre Deak) Reviewed-by: Imre Deak <imre.deak@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211122211420.31584-1-stanislav.lisovskiy@intel.com
This commit is contained in:
parent
448cc2fb3a
commit
3c542cfa82
11 changed files with 37 additions and 8 deletions
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@ -7766,6 +7766,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
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case I915_FORMAT_MOD_X_TILED:
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case I915_FORMAT_MOD_Y_TILED:
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case I915_FORMAT_MOD_Yf_TILED:
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case I915_FORMAT_MOD_4_TILED:
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break;
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default:
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drm_dbg_kms(&i915->drm,
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@ -139,6 +139,9 @@ struct intel_modifier_desc {
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static const struct intel_modifier_desc intel_modifiers[] = {
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{
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.modifier = I915_FORMAT_MOD_4_TILED,
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.display_ver = { 13, 13 },
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}, {
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.modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
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.display_ver = { 12, 13 },
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.plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
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@ -544,6 +547,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
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return 128;
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else
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return 512;
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case I915_FORMAT_MOD_4_TILED:
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/*
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* Each 4K tile consists of 64B(8*8) subtiles, with
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* same shape as Y Tile(i.e 4*16B OWords)
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*/
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return 128;
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case I915_FORMAT_MOD_Y_TILED_CCS:
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if (intel_fb_is_ccs_aux_plane(fb, color_plane))
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return 128;
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@ -898,6 +898,7 @@ static bool tiling_is_valid(struct drm_i915_private *i915,
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case I915_FORMAT_MOD_Y_TILED:
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case I915_FORMAT_MOD_Yf_TILED:
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return DISPLAY_VER(i915) >= 9;
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case I915_FORMAT_MOD_4_TILED:
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case I915_FORMAT_MOD_X_TILED:
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return true;
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default:
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@ -125,6 +125,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
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case DRM_FORMAT_MOD_LINEAR:
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case I915_FORMAT_MOD_X_TILED:
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case I915_FORMAT_MOD_Y_TILED:
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case I915_FORMAT_MOD_4_TILED:
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break;
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default:
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drm_dbg(&dev_priv->drm,
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@ -751,6 +751,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
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return PLANE_CTL_TILED_X;
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case I915_FORMAT_MOD_Y_TILED:
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return PLANE_CTL_TILED_Y;
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case I915_FORMAT_MOD_4_TILED:
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return PLANE_CTL_TILED_4;
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case I915_FORMAT_MOD_Y_TILED_CCS:
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case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
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return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
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@ -1971,9 +1973,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
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case DRM_FORMAT_Y216:
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case DRM_FORMAT_XVYU12_16161616:
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case DRM_FORMAT_XVYU16161616:
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if (modifier == DRM_FORMAT_MOD_LINEAR ||
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modifier == I915_FORMAT_MOD_X_TILED ||
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modifier == I915_FORMAT_MOD_Y_TILED)
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if (!intel_fb_is_ccs_modifier(modifier))
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return true;
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fallthrough;
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default:
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@ -2299,11 +2299,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
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else
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fb->modifier = I915_FORMAT_MOD_Y_TILED;
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break;
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case PLANE_CTL_TILED_YF:
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if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
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fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
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else
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fb->modifier = I915_FORMAT_MOD_Yf_TILED;
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case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
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if (HAS_4TILE(dev_priv)) {
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fb->modifier = I915_FORMAT_MOD_4_TILED;
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} else {
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if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
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fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
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else
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fb->modifier = I915_FORMAT_MOD_Yf_TILED;
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}
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break;
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default:
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MISSING_CASE(tiling);
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@ -1624,6 +1624,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
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#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
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#define HAS_4TILE(dev_priv) (INTEL_INFO(dev_priv)->has_4tile)
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#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
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#define HAS_EDRAM(dev_priv) ((dev_priv)->edram_size_mb)
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#define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)
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@ -1044,6 +1044,7 @@ static const struct intel_device_info dg2_info = {
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DGFX_FEATURES,
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.graphics_rel = 55,
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.media_rel = 55,
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.has_4tile = 1,
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PLATFORM(INTEL_DG2),
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.platform_engine_mask =
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BIT(RCS0) | BIT(BCS0) |
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@ -7210,6 +7210,7 @@ enum {
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#define PLANE_CTL_TILED_X (1 << 10)
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#define PLANE_CTL_TILED_Y (4 << 10)
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#define PLANE_CTL_TILED_YF (5 << 10)
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#define PLANE_CTL_TILED_4 (5 << 10)
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#define PLANE_CTL_ASYNC_FLIP (1 << 9)
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#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
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#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
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@ -125,6 +125,7 @@ enum intel_ppgtt_type {
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func(has_64bit_reloc); \
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func(gpu_reset_clobbers_display); \
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func(has_reset_engine); \
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func(has_4tile); \
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func(has_global_mocs); \
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func(has_gt_uc); \
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func(has_l3_dpf); \
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@ -5386,6 +5386,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
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}
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wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
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modifier == I915_FORMAT_MOD_4_TILED ||
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modifier == I915_FORMAT_MOD_Yf_TILED ||
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modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
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modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
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@ -564,6 +564,14 @@ extern "C" {
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* pitch is required to be a multiple of 4 tile widths.
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*/
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#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
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/*
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* Intel F-tiling(aka Tile4) layout
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*
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* This is a tiled layout using 4Kb tiles in row-major layout.
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* Within the tile pixels are laid out in 64 byte units / sub-tiles in OWORD
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* (16 bytes) chunks column-major..
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*/
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#define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
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/*
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* Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
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