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ARM: dts: imx6: edmqmx6: Add two other i2c buses
Signed-off-by: Silvio Fricke <silvio.fricke@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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1 changed files with 28 additions and 0 deletions
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@ -118,6 +118,13 @@ &fec {
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status = "okay";
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status = "okay";
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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};
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&i2c2 {
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&i2c2 {
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clock-frequency = <100000>;
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-names = "default";
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@ -274,6 +281,13 @@ rtc: m41t62@68 {
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};
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};
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};
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};
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&i2c3 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c3>;
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status = "okay";
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};
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&iomuxc {
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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pinctrl-0 = <&pinctrl_hog>;
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@ -316,6 +330,13 @@ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
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>;
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>;
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};
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
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>;
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};
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pinctrl_i2c2: i2c2grp {
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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fsl,pins = <
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MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
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MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
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@ -323,6 +344,13 @@ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
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>;
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>;
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};
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};
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pinctrl_i2c3: i2c3grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
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MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
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>;
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};
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pinctrl_pcie: pciegrp {
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pinctrl_pcie: pciegrp {
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fsl,pins = <
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fsl,pins = <
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MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1
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MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1
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