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EDAC/igen6: Add Intel Meteor Lake-PS SoCs support
Add Intel Meteor Lake-PS SoC compute die IDs for EDAC support. These SoCs share similar IBECC registers with Alder Lake-P SoCs. The only difference is that IBECC presence is detected through an MMIO-mapped register instead of the capability register in the PCI configuration space. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
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d23627a768
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1 changed files with 44 additions and 0 deletions
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@ -245,6 +245,12 @@ static struct work_struct ecclog_work;
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#define DID_RPL_P_SKU4 0xa716
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#define DID_RPL_P_SKU5 0xa718
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/* Compute die IDs for Meteor Lake-PS with IBECC */
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#define DID_MTL_PS_SKU1 0x7d21
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#define DID_MTL_PS_SKU2 0x7d22
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#define DID_MTL_PS_SKU3 0x7d23
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#define DID_MTL_PS_SKU4 0x7d24
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static int get_mchbar(struct pci_dev *pdev, u64 *mchbar)
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{
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union {
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@ -325,6 +331,29 @@ static bool tgl_ibecc_available(struct pci_dev *pdev)
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return !(CAPID_E_IBECC & v);
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}
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static bool mtl_ps_ibecc_available(struct pci_dev *pdev)
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{
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#define MCHBAR_MEMSS_IBECCDIS 0x13c00
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void __iomem *window;
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u64 mchbar;
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u32 val;
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if (get_mchbar(pdev, &mchbar))
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return false;
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window = ioremap(mchbar, MCHBAR_SIZE * 2);
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if (!window) {
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igen6_printk(KERN_ERR, "Failed to ioremap 0x%llx\n", mchbar);
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return false;
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}
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val = readl(window + MCHBAR_MEMSS_IBECCDIS);
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iounmap(window);
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/* Bit6: 1 - IBECC is disabled, 0 - IBECC isn't disabled */
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return !GET_BITFIELD(val, 6, 6);
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}
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static u64 mem_addr_to_sys_addr(u64 maddr)
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{
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if (maddr < igen6_tolud)
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@ -484,6 +513,17 @@ static struct res_config rpl_p_cfg = {
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.err_addr_to_imc_addr = adl_err_addr_to_imc_addr,
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};
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static struct res_config mtl_ps_cfg = {
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.machine_check = true,
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.num_imc = 2,
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.imc_base = 0xd800,
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.ibecc_base = 0xd400,
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.ibecc_error_log_offset = 0x170,
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.ibecc_available = mtl_ps_ibecc_available,
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.err_addr_to_sys_addr = adl_err_addr_to_sys_addr,
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.err_addr_to_imc_addr = adl_err_addr_to_imc_addr,
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};
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static const struct pci_device_id igen6_pci_tbl[] = {
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{ PCI_VDEVICE(INTEL, DID_EHL_SKU5), (kernel_ulong_t)&ehl_cfg },
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{ PCI_VDEVICE(INTEL, DID_EHL_SKU6), (kernel_ulong_t)&ehl_cfg },
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@ -521,6 +561,10 @@ static const struct pci_device_id igen6_pci_tbl[] = {
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{ PCI_VDEVICE(INTEL, DID_RPL_P_SKU3), (kernel_ulong_t)&rpl_p_cfg },
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{ PCI_VDEVICE(INTEL, DID_RPL_P_SKU4), (kernel_ulong_t)&rpl_p_cfg },
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{ PCI_VDEVICE(INTEL, DID_RPL_P_SKU5), (kernel_ulong_t)&rpl_p_cfg },
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{ PCI_VDEVICE(INTEL, DID_MTL_PS_SKU1), (kernel_ulong_t)&mtl_ps_cfg },
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{ PCI_VDEVICE(INTEL, DID_MTL_PS_SKU2), (kernel_ulong_t)&mtl_ps_cfg },
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{ PCI_VDEVICE(INTEL, DID_MTL_PS_SKU3), (kernel_ulong_t)&mtl_ps_cfg },
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{ PCI_VDEVICE(INTEL, DID_MTL_PS_SKU4), (kernel_ulong_t)&mtl_ps_cfg },
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{ },
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};
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MODULE_DEVICE_TABLE(pci, igen6_pci_tbl);
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