drm/i915/selftests: Perform some basic cycle counting of MI ops
Some basic information that is useful to know, such as how many cycles is a MI_NOOP. v2: Keep volatile pages pinned at all times! (Matthew) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Anna Karas <anna.karas@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191111172716.23733-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
31b61f0ef9
commit
3c7a44bbbf
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@ -526,8 +526,6 @@ static int igt_copy_blt_ctx0(void *arg)
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int i915_gem_object_blt_live_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(perf_fill_blt),
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SUBTEST(perf_copy_blt),
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SUBTEST(igt_fill_blt),
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SUBTEST(igt_fill_blt_ctx0),
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SUBTEST(igt_copy_blt),
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@ -542,3 +540,16 @@ int i915_gem_object_blt_live_selftests(struct drm_i915_private *i915)
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return i915_live_subtests(tests, i915);
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}
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int i915_gem_object_blt_perf_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(perf_fill_blt),
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SUBTEST(perf_copy_blt),
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};
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if (intel_gt_is_wedged(&i915->gt))
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return 0;
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return i915_live_subtests(tests, i915);
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}
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@ -4,7 +4,353 @@
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* Copyright © 2018 Intel Corporation
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*/
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#include "../i915_selftest.h"
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#include <linux/sort.h>
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#include "intel_gt_pm.h"
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#include "intel_rps.h"
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#include "i915_selftest.h"
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#include "selftests/igt_flush_test.h"
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#define COUNT 5
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static int cmp_u32(const void *A, const void *B)
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{
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const u32 *a = A, *b = B;
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return *a - *b;
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}
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static void perf_begin(struct intel_gt *gt)
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{
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intel_gt_pm_get(gt);
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/* Boost gpufreq to max [waitboost] and keep it fixed */
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atomic_inc(>->rps.num_waiters);
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schedule_work(>->rps.work);
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flush_work(>->rps.work);
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}
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static int perf_end(struct intel_gt *gt)
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{
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atomic_dec(>->rps.num_waiters);
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intel_gt_pm_put(gt);
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return igt_flush_test(gt->i915);
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}
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static int write_timestamp(struct i915_request *rq, int slot)
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{
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u32 cmd;
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u32 *cs;
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cs = intel_ring_begin(rq, 4);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
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if (INTEL_GEN(rq->i915) >= 8)
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cmd++;
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*cs++ = cmd;
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*cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
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*cs++ = i915_request_timeline(rq)->hwsp_offset + slot * sizeof(u32);
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*cs++ = 0;
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intel_ring_advance(rq, cs);
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return 0;
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}
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static struct i915_vma *create_empty_batch(struct intel_context *ce)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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u32 *cs;
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int err;
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obj = i915_gem_object_create_internal(ce->engine->i915, PAGE_SIZE);
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if (IS_ERR(obj))
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return ERR_CAST(obj);
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cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
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if (IS_ERR(cs)) {
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err = PTR_ERR(cs);
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goto err_put;
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}
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cs[0] = MI_BATCH_BUFFER_END;
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i915_gem_object_flush_map(obj);
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vma = i915_vma_instance(obj, ce->vm, NULL);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto err_unpin;
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}
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err = i915_vma_pin(vma, 0, 0, PIN_USER);
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if (err)
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goto err_unpin;
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i915_gem_object_unpin_map(obj);
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return vma;
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err_unpin:
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i915_gem_object_unpin_map(obj);
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err_put:
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i915_gem_object_put(obj);
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return ERR_PTR(err);
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}
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static u32 trifilter(u32 *a)
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{
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u64 sum;
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sort(a, COUNT, sizeof(*a), cmp_u32, NULL);
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sum += mul_u32_u32(a[2], 2);
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sum += a[1];
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sum += a[3];
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return sum >> 2;
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}
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static int perf_mi_bb_start(void *arg)
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{
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struct intel_gt *gt = arg;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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int err = 0;
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if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
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return 0;
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perf_begin(gt);
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for_each_engine(engine, gt, id) {
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struct intel_context *ce = engine->kernel_context;
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struct i915_vma *batch;
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u32 cycles[COUNT];
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int i;
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batch = create_empty_batch(ce);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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break;
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}
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err = i915_vma_sync(batch);
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if (err) {
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i915_vma_put(batch);
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break;
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}
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for (i = 0; i < ARRAY_SIZE(cycles); i++) {
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struct i915_request *rq;
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rq = i915_request_create(ce);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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break;
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}
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err = write_timestamp(rq, 2);
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if (err)
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goto out;
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err = rq->engine->emit_bb_start(rq,
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batch->node.start, 8,
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0);
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if (err)
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goto out;
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err = write_timestamp(rq, 3);
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if (err)
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goto out;
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out:
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i915_request_get(rq);
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i915_request_add(rq);
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if (i915_request_wait(rq, 0, HZ / 5) < 0)
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err = -EIO;
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i915_request_put(rq);
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if (err)
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break;
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cycles[i] = rq->hwsp_seqno[3] - rq->hwsp_seqno[2];
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}
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i915_vma_put(batch);
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if (err)
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break;
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pr_info("%s: MI_BB_START cycles: %u\n",
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engine->name, trifilter(cycles));
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}
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if (perf_end(gt))
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err = -EIO;
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return err;
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}
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static struct i915_vma *create_nop_batch(struct intel_context *ce)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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u32 *cs;
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int err;
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obj = i915_gem_object_create_internal(ce->engine->i915, SZ_64K);
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if (IS_ERR(obj))
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return ERR_CAST(obj);
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cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
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if (IS_ERR(cs)) {
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err = PTR_ERR(cs);
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goto err_put;
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}
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memset(cs, 0, SZ_64K);
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cs[SZ_64K / sizeof(*cs) - 1] = MI_BATCH_BUFFER_END;
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i915_gem_object_flush_map(obj);
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vma = i915_vma_instance(obj, ce->vm, NULL);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto err_unpin;
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}
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err = i915_vma_pin(vma, 0, 0, PIN_USER);
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if (err)
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goto err_unpin;
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i915_gem_object_unpin_map(obj);
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return vma;
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err_unpin:
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i915_gem_object_unpin_map(obj);
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err_put:
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i915_gem_object_put(obj);
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return ERR_PTR(err);
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}
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static int perf_mi_noop(void *arg)
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{
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struct intel_gt *gt = arg;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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int err = 0;
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if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
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return 0;
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perf_begin(gt);
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for_each_engine(engine, gt, id) {
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struct intel_context *ce = engine->kernel_context;
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struct i915_vma *base, *nop;
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u32 cycles[COUNT];
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int i;
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base = create_empty_batch(ce);
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if (IS_ERR(base)) {
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err = PTR_ERR(base);
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break;
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}
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err = i915_vma_sync(base);
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if (err) {
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i915_vma_put(base);
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break;
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}
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nop = create_nop_batch(ce);
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if (IS_ERR(nop)) {
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err = PTR_ERR(nop);
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i915_vma_put(base);
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break;
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}
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err = i915_vma_sync(nop);
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if (err) {
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i915_vma_put(nop);
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i915_vma_put(base);
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break;
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}
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for (i = 0; i < ARRAY_SIZE(cycles); i++) {
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struct i915_request *rq;
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rq = i915_request_create(ce);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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break;
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}
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err = write_timestamp(rq, 2);
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if (err)
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goto out;
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err = rq->engine->emit_bb_start(rq,
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base->node.start, 8,
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0);
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if (err)
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goto out;
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err = write_timestamp(rq, 3);
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if (err)
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goto out;
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err = rq->engine->emit_bb_start(rq,
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nop->node.start,
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nop->node.size,
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0);
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if (err)
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goto out;
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err = write_timestamp(rq, 4);
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if (err)
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goto out;
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out:
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i915_request_get(rq);
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i915_request_add(rq);
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if (i915_request_wait(rq, 0, HZ / 5) < 0)
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err = -EIO;
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i915_request_put(rq);
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if (err)
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break;
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cycles[i] =
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(rq->hwsp_seqno[4] - rq->hwsp_seqno[3]) -
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(rq->hwsp_seqno[3] - rq->hwsp_seqno[2]);
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}
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i915_vma_put(nop);
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i915_vma_put(base);
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if (err)
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break;
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pr_info("%s: 16K MI_NOOP cycles: %u\n",
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engine->name, trifilter(cycles));
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}
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if (perf_end(gt))
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err = -EIO;
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return err;
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}
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int intel_engine_cs_perf_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(perf_mi_bb_start),
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SUBTEST(perf_mi_noop),
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};
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if (intel_gt_is_wedged(&i915->gt))
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return 0;
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return intel_gt_live_subtests(tests, &i915->gt);
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}
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static int intel_mmio_bases_check(void *arg)
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{
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@ -1003,6 +1003,12 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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return err > 0 ? -ENOTTY : err;
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}
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err = i915_perf_selftests(pdev);
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if (err) {
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i915_pci_remove(pdev);
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return err > 0 ? -ENOTTY : err;
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}
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return 0;
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}
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@ -36,6 +36,7 @@ struct i915_selftest {
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char *filter;
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int mock;
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int live;
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int perf;
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};
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#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
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@ -45,6 +46,7 @@ extern struct i915_selftest i915_selftest;
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int i915_mock_selftests(void);
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int i915_live_selftests(struct pci_dev *pdev);
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int i915_perf_selftests(struct pci_dev *pdev);
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/* We extract the function declarations from i915_mock_selftests.h and
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* i915_live_selftests.h Add your unit test declarations there!
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@ -61,6 +63,7 @@ int i915_live_selftests(struct pci_dev *pdev);
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#undef selftest
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#define selftest(name, func) int func(struct drm_i915_private *i915);
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#include "selftests/i915_live_selftests.h"
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#include "selftests/i915_perf_selftests.h"
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#undef selftest
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struct i915_subtest {
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@ -109,6 +112,7 @@ int __i915_subtests(const char *caller,
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static inline int i915_mock_selftests(void) { return 0; }
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static inline int i915_live_selftests(struct pci_dev *pdev) { return 0; }
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static inline int i915_perf_selftests(struct pci_dev *pdev) { return 0; }
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#define I915_SELFTEST_DECLARE(x)
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#define I915_SELFTEST_ONLY(x) 0
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@ -0,0 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* List each unit test as selftest(name, function)
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*
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* The name is used as both an enum and expanded as subtest__name to create
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* a module parameter. It must be unique and legal for a C identifier.
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*
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* The function should be of type int function(void). It may be conditionally
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* compiled using #if IS_ENABLED(DRM_I915_SELFTEST).
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*
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* Tests are executed in order by igt/i915_selftest
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*/
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selftest(engine_cs, intel_engine_cs_perf_selftests)
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selftest(blt, i915_gem_object_blt_perf_selftests)
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@ -57,6 +57,12 @@ enum {
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#undef selftest
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};
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enum {
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#define selftest(name, func) perf_##name,
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#include "i915_perf_selftests.h"
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#undef selftest
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};
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struct selftest {
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bool enabled;
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const char *name;
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@ -78,6 +84,12 @@ static struct selftest live_selftests[] = {
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};
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#undef selftest
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#define selftest(n, f) [perf_##n] = { .name = #n, { .live = f } },
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static struct selftest perf_selftests[] = {
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#include "i915_perf_selftests.h"
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};
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#undef selftest
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/* Embed the line number into the parameter name so that we can order tests */
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#define selftest(n, func) selftest_0(n, func, param(n))
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#define param(n) __PASTE(igt__, __PASTE(__LINE__, __mock_##n))
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@ -93,6 +105,13 @@ module_param_named(id, live_selftests[live_##n].enabled, bool, 0400);
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#include "i915_live_selftests.h"
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#undef selftest_0
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#undef param
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#define param(n) __PASTE(igt__, __PASTE(__LINE__, __perf_##n))
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#define selftest_0(n, func, id) \
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module_param_named(id, perf_selftests[perf_##n].enabled, bool, 0400);
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#include "i915_perf_selftests.h"
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#undef selftest_0
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#undef param
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#undef selftest
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static void set_default_test_all(struct selftest *st, unsigned int count)
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@ -200,6 +219,27 @@ int i915_live_selftests(struct pci_dev *pdev)
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|||
return 0;
|
||||
}
|
||||
|
||||
int i915_perf_selftests(struct pci_dev *pdev)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (!i915_selftest.perf)
|
||||
return 0;
|
||||
|
||||
err = run_selftests(perf, pdev_to_i915(pdev));
|
||||
if (err) {
|
||||
i915_selftest.perf = err;
|
||||
return err;
|
||||
}
|
||||
|
||||
if (i915_selftest.perf < 0) {
|
||||
i915_selftest.perf = -ENOTTY;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool apply_subtest_filter(const char *caller, const char *name)
|
||||
{
|
||||
char *filter, *sep, *tok;
|
||||
|
|
@ -365,3 +405,6 @@ MODULE_PARM_DESC(mock_selftests, "Run selftests before loading, using mock hardw
|
|||
|
||||
module_param_named_unsafe(live_selftests, i915_selftest.live, int, 0400);
|
||||
MODULE_PARM_DESC(live_selftests, "Run selftests after driver initialisation on the live system (0:disabled [default], 1:run tests then continue, -1:run tests then exit module)");
|
||||
|
||||
module_param_named_unsafe(perf_selftests, i915_selftest.perf, int, 0400);
|
||||
MODULE_PARM_DESC(perf_selftests, "Run performance orientated selftests after driver initialisation on the live system (0:disabled [default], 1:run tests then continue, -1:run tests then exit module)");
|
||||
|
|
|
|||
Loading…
Reference in New Issue