mirror of
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Merge branch 'for-v3.19/exynos-clk' of git://linuxtv.org/snawrocki/samsung into clk-next-exynos
This commit is contained in:
commit
3c7f4fe810
12 changed files with 2655 additions and 164 deletions
38
Documentation/devicetree/bindings/clock/exynos4415-clock.txt
Normal file
38
Documentation/devicetree/bindings/clock/exynos4415-clock.txt
Normal file
|
@ -0,0 +1,38 @@
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|||
* Samsung Exynos4415 Clock Controller
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|
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The Exynos4415 clock controller generates and supplies clock to various
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consumer devices within the Exynos4415 SoC.
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Required properties:
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- compatible: should be one of the following:
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- "samsung,exynos4415-cmu" - for the main system clocks controller
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(CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
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- "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
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Controller (DMC) domain clock controller.
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- reg: physical base address of the controller and length of memory mapped
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region.
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|
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- #clock-cells: should be 1.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume.
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/exynos4415.h header and can be used in device
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tree sources.
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Example 1: An example of a clock controller node is listed below.
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cmu: clock-controller@10030000 {
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compatible = "samsung,exynos4415-cmu";
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reg = <0x10030000 0x18000>;
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#clock-cells = <1>;
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};
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cmu-dmc: clock-controller@105C0000 {
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compatible = "samsung,exynos4415-cmu-dmc";
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reg = <0x105C0000 0x3000>;
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#clock-cells = <1>;
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};
|
93
Documentation/devicetree/bindings/clock/exynos7-clock.txt
Normal file
93
Documentation/devicetree/bindings/clock/exynos7-clock.txt
Normal file
|
@ -0,0 +1,93 @@
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|||
* Samsung Exynos7 Clock Controller
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Exynos7 clock controller has various blocks which are instantiated
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independently from the device-tree. These clock controllers
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||||
generate and supply clocks to various hardware blocks within
|
||||
the SoC.
|
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|
||||
Each clock is assigned an identifier and client nodes can use
|
||||
this identifier to specify the clock which they consume. All
|
||||
available clocks are defined as preprocessor macros in
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dt-bindings/clock/exynos7-clk.h header and can be used in
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device tree sources.
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External clocks:
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|
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There are several clocks that are generated outside the SoC. It
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is expected that they are defined using standard clock bindings
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with following clock-output-names:
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|
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- "fin_pll" - PLL input clock from XXTI
|
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|
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Required Properties for Clock Controller:
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||||
|
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- compatible: clock controllers will use one of the following
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||||
compatible strings to indicate the clock controller
|
||||
functionality.
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- "samsung,exynos7-clock-topc"
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- "samsung,exynos7-clock-top0"
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- "samsung,exynos7-clock-top1"
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- "samsung,exynos7-clock-ccore"
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- "samsung,exynos7-clock-peric0"
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- "samsung,exynos7-clock-peric1"
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- "samsung,exynos7-clock-peris"
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- "samsung,exynos7-clock-fsys0"
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- "samsung,exynos7-clock-fsys1"
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|
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- reg: physical base address of the controller and the length of
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memory mapped region.
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|
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- #clock-cells: should be 1.
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- clocks: list of clock identifiers which are fed as the input to
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||||
the given clock controller. Please refer the next section to
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find the input clocks for a given controller.
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- clock-names: list of names of clocks which are fed as the input
|
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to the given clock controller.
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|
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Input clocks for top0 clock controller:
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- fin_pll
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- dout_sclk_bus0_pll
|
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- dout_sclk_bus1_pll
|
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- dout_sclk_cc_pll
|
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- dout_sclk_mfc_pll
|
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|
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Input clocks for top1 clock controller:
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- fin_pll
|
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- dout_sclk_bus0_pll
|
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- dout_sclk_bus1_pll
|
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- dout_sclk_cc_pll
|
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- dout_sclk_mfc_pll
|
||||
|
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Input clocks for ccore clock controller:
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- fin_pll
|
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- dout_aclk_ccore_133
|
||||
|
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Input clocks for peric0 clock controller:
|
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- fin_pll
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- dout_aclk_peric0_66
|
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- sclk_uart0
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|
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Input clocks for peric1 clock controller:
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- fin_pll
|
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- dout_aclk_peric1_66
|
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- sclk_uart1
|
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- sclk_uart2
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- sclk_uart3
|
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|
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Input clocks for peris clock controller:
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- fin_pll
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- dout_aclk_peris_66
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|
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Input clocks for fsys0 clock controller:
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- fin_pll
|
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- dout_aclk_fsys0_200
|
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- dout_sclk_mmc2
|
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|
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Input clocks for fsys1 clock controller:
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- fin_pll
|
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- dout_aclk_fsys1_200
|
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- dout_sclk_mmc0
|
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- dout_sclk_mmc1
|
|
@ -5,6 +5,7 @@
|
|||
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
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obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
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obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
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obj-$(CONFIG_SOC_EXYNOS4415) += clk-exynos4415.o
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obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
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obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
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obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
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|
@ -12,6 +13,7 @@ obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
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obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
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obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
|
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obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
|
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obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o
|
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obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
|
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obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
|
||||
obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
|
||||
|
|
1142
drivers/clk/samsung/clk-exynos4415.c
Normal file
1142
drivers/clk/samsung/clk-exynos4415.c
Normal file
File diff suppressed because it is too large
Load diff
|
@ -11,10 +11,8 @@
|
|||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
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#include <linux/of.h>
|
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#include <linux/of_address.h>
|
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#include <linux/syscore_ops.h>
|
||||
|
||||
#include "clk-exynos5260.h"
|
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#include "clk.h"
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|
@ -22,39 +20,6 @@
|
|||
|
||||
#include <dt-bindings/clock/exynos5260-clk.h>
|
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|
||||
static LIST_HEAD(clock_reg_cache_list);
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|
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struct exynos5260_clock_reg_cache {
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struct list_head node;
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void __iomem *reg_base;
|
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struct samsung_clk_reg_dump *rdump;
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unsigned int rd_num;
|
||||
};
|
||||
|
||||
struct exynos5260_cmu_info {
|
||||
/* list of pll clocks and respective count */
|
||||
struct samsung_pll_clock *pll_clks;
|
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unsigned int nr_pll_clks;
|
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/* list of mux clocks and respective count */
|
||||
struct samsung_mux_clock *mux_clks;
|
||||
unsigned int nr_mux_clks;
|
||||
/* list of div clocks and respective count */
|
||||
struct samsung_div_clock *div_clks;
|
||||
unsigned int nr_div_clks;
|
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/* list of gate clocks and respective count */
|
||||
struct samsung_gate_clock *gate_clks;
|
||||
unsigned int nr_gate_clks;
|
||||
/* list of fixed clocks and respective count */
|
||||
struct samsung_fixed_rate_clock *fixed_clks;
|
||||
unsigned int nr_fixed_clks;
|
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/* total number of clocks with IDs assigned*/
|
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unsigned int nr_clk_ids;
|
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|
||||
/* list and number of clocks registers */
|
||||
unsigned long *clk_regs;
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unsigned int nr_clk_regs;
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};
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|
||||
/*
|
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* Applicable for all 2550 Type PLLS for Exynos5260, listed below
|
||||
* DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
|
||||
|
@ -113,104 +78,6 @@ static struct samsung_pll_rate_table pll2650_24mhz_tbl[] __initdata = {
|
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PLL_36XX_RATE(66000000, 176, 2, 5, 0),
|
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};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
|
||||
static int exynos5260_clk_suspend(void)
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||||
{
|
||||
struct exynos5260_clock_reg_cache *cache;
|
||||
|
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list_for_each_entry(cache, &clock_reg_cache_list, node)
|
||||
samsung_clk_save(cache->reg_base, cache->rdump,
|
||||
cache->rd_num);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos5260_clk_resume(void)
|
||||
{
|
||||
struct exynos5260_clock_reg_cache *cache;
|
||||
|
||||
list_for_each_entry(cache, &clock_reg_cache_list, node)
|
||||
samsung_clk_restore(cache->reg_base, cache->rdump,
|
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cache->rd_num);
|
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}
|
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|
||||
static struct syscore_ops exynos5260_clk_syscore_ops = {
|
||||
.suspend = exynos5260_clk_suspend,
|
||||
.resume = exynos5260_clk_resume,
|
||||
};
|
||||
|
||||
static void exynos5260_clk_sleep_init(void __iomem *reg_base,
|
||||
unsigned long *rdump,
|
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unsigned long nr_rdump)
|
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{
|
||||
struct exynos5260_clock_reg_cache *reg_cache;
|
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|
||||
reg_cache = kzalloc(sizeof(struct exynos5260_clock_reg_cache),
|
||||
GFP_KERNEL);
|
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if (!reg_cache)
|
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panic("could not allocate register cache.\n");
|
||||
|
||||
reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
|
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|
||||
if (!reg_cache->rdump)
|
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panic("could not allocate register dump storage.\n");
|
||||
|
||||
if (list_empty(&clock_reg_cache_list))
|
||||
register_syscore_ops(&exynos5260_clk_syscore_ops);
|
||||
|
||||
reg_cache->rd_num = nr_rdump;
|
||||
reg_cache->reg_base = reg_base;
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list_add_tail(®_cache->node, &clock_reg_cache_list);
|
||||
}
|
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|
||||
#else
|
||||
static void exynos5260_clk_sleep_init(void __iomem *reg_base,
|
||||
unsigned long *rdump,
|
||||
unsigned long nr_rdump){}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Common function which registers plls, muxes, dividers and gates
|
||||
* for each CMU. It also add CMU register list to register cache.
|
||||
*/
|
||||
|
||||
void __init exynos5260_cmu_register_one(struct device_node *np,
|
||||
struct exynos5260_cmu_info *cmu)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
struct samsung_clk_provider *ctx;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base)
|
||||
panic("%s: failed to map registers\n", __func__);
|
||||
|
||||
ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
|
||||
if (!ctx)
|
||||
panic("%s: unable to alllocate ctx\n", __func__);
|
||||
|
||||
if (cmu->pll_clks)
|
||||
samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
|
||||
reg_base);
|
||||
if (cmu->mux_clks)
|
||||
samsung_clk_register_mux(ctx, cmu->mux_clks,
|
||||
cmu->nr_mux_clks);
|
||||
if (cmu->div_clks)
|
||||
samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
|
||||
if (cmu->gate_clks)
|
||||
samsung_clk_register_gate(ctx, cmu->gate_clks,
|
||||
cmu->nr_gate_clks);
|
||||
if (cmu->fixed_clks)
|
||||
samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
|
||||
cmu->nr_fixed_clks);
|
||||
if (cmu->clk_regs)
|
||||
exynos5260_clk_sleep_init(reg_base, cmu->clk_regs,
|
||||
cmu->nr_clk_regs);
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
|
||||
|
||||
/* CMU_AUD */
|
||||
|
||||
static unsigned long aud_clk_regs[] __initdata = {
|
||||
|
@ -268,7 +135,7 @@ struct samsung_gate_clock aud_gate_clks[] __initdata = {
|
|||
|
||||
static void __init exynos5260_clk_aud_init(struct device_node *np)
|
||||
{
|
||||
struct exynos5260_cmu_info cmu = {0};
|
||||
struct samsung_cmu_info cmu = {0};
|
||||
|
||||
cmu.mux_clks = aud_mux_clks;
|
||||
cmu.nr_mux_clks = ARRAY_SIZE(aud_mux_clks);
|
||||
|
@ -280,7 +147,7 @@ static void __init exynos5260_clk_aud_init(struct device_node *np)
|
|||
cmu.clk_regs = aud_clk_regs;
|
||||
cmu.nr_clk_regs = ARRAY_SIZE(aud_clk_regs);
|
||||
|
||||
exynos5260_cmu_register_one(np, &cmu);
|
||||
samsung_cmu_register_one(np, &cmu);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos5260_clk_aud, "samsung,exynos5260-clock-aud",
|
||||
|
@ -458,7 +325,7 @@ struct samsung_gate_clock disp_gate_clks[] __initdata = {
|
|||
|
||||
static void __init exynos5260_clk_disp_init(struct device_node *np)
|
||||
{
|
||||
struct exynos5260_cmu_info cmu = {0};
|
||||
struct samsung_cmu_info cmu = {0};
|
||||
|
||||
cmu.mux_clks = disp_mux_clks;
|
||||
cmu.nr_mux_clks = ARRAY_SIZE(disp_mux_clks);
|
||||
|
@ -470,7 +337,7 @@ static void __init exynos5260_clk_disp_init(struct device_node *np)
|
|||
cmu.clk_regs = disp_clk_regs;
|
||||
cmu.nr_clk_regs = ARRAY_SIZE(disp_clk_regs);
|
||||
|
||||
exynos5260_cmu_register_one(np, &cmu);
|
||||
samsung_cmu_register_one(np, &cmu);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos5260_clk_disp, "samsung,exynos5260-clock-disp",
|
||||
|
@ -522,7 +389,7 @@ static struct samsung_pll_clock egl_pll_clks[] __initdata = {
|
|||
|
||||
static void __init exynos5260_clk_egl_init(struct device_node *np)
|
||||
{
|
||||
struct exynos5260_cmu_info cmu = {0};
|
||||
struct samsung_cmu_info cmu = {0};
|
||||
|
||||
cmu.pll_clks = egl_pll_clks;
|
||||
cmu.nr_pll_clks = ARRAY_SIZE(egl_pll_clks);
|
||||
|
@ -534,7 +401,7 @@ static void __init exynos5260_clk_egl_init(struct device_node *np)
|
|||
cmu.clk_regs = egl_clk_regs;
|
||||
cmu.nr_clk_regs = ARRAY_SIZE(egl_clk_regs);
|
||||
|
||||
exynos5260_cmu_register_one(np, &cmu);
|
||||
samsung_cmu_register_one(np, &cmu);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos5260_clk_egl, "samsung,exynos5260-clock-egl",
|
||||
|
@ -624,7 +491,7 @@ struct samsung_gate_clock fsys_gate_clks[] __initdata = {
|
|||
|
||||
static void __init exynos5260_clk_fsys_init(struct device_node *np)
|
||||
{
|
||||
struct exynos5260_cmu_info cmu = {0};
|
||||
struct samsung_cmu_info cmu = {0};
|
||||
|
||||
cmu.mux_clks = fsys_mux_clks;
|
||||
cmu.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks);
|
||||
|
@ -634,7 +501,7 @@ static void __init exynos5260_clk_fsys_init(struct device_node *np)
|
|||
cmu.clk_regs = fsys_clk_regs;
|
||||
cmu.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs);
|
||||
|
||||
exynos5260_cmu_register_one(np, &cmu);
|
||||
samsung_cmu_register_one(np, &cmu);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos5260_clk_fsys, "samsung,exynos5260-clock-fsys",
|
||||
|
@ -713,7 +580,7 @@ struct samsung_gate_clock g2d_gate_clks[] __initdata = {
|
|||
|
||||
static void __init exynos5260_clk_g2d_init(struct device_node *np)
|
||||
{
|
||||
struct exynos5260_cmu_info cmu = {0};
|
||||
struct samsung_cmu_info cmu = {0};
|
||||
|
||||
cmu.mux_clks = g2d_mux_clks;
|
||||
cmu.nr_mux_clks = ARRAY_SIZE(g2d_mux_clks);
|
||||
|
@ -725,7 +592,7 @@ static void __init exynos5260_clk_g2d_init(struct device_node *np)
|
|||
cmu.clk_regs = g2d_clk_regs;
|
||||
cmu.nr_clk_regs = ARRAY_SIZE(g2d_clk_regs);
|
||||
|
||||
exynos5260_cmu_register_one(np, &cmu);
|
||||
samsung_cmu_register_one(np, &cmu);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos5260_clk_g2d, "samsung,exynos5260-clock-g2d",
|
||||
|
@ -774,7 +641,7 @@ static struct samsung_pll_clock g3d_pll_clks[] __initdata = {
|
|||
|
||||
static void __init exynos5260_clk_g3d_init(struct device_node *np)
|
||||
{
|
||||
struct exynos5260_cmu_info cmu = {0};
|
||||
struct samsung_cmu_info cmu = {0};
|
||||
|
||||
cmu.pll_clks = g3d_pll_clks;
|
||||
cmu.nr_pll_clks = ARRAY_SIZE(g3d_pll_clks);
|
||||
|
@ -788,7 +655,7 @@ static void __init exynos5260_clk_g3d_init(struct device_node *np)
|
|||
cmu.clk_regs = g3d_clk_regs;
|
||||
cmu.nr_clk_regs = ARRAY_SIZE(g3d_clk_regs);
|
||||
|
||||
exynos5260_cmu_register_one(np, &cmu);
|
||||
samsung_cmu_register_one(np, &cmu);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos5260_clk_g3d, "samsung,exynos5260-clock-g3d",
|
||||
|
@ -909,7 +776,7 @@ struct samsung_gate_clock gscl_gate_clks[] __initdata = {
|
|||
|
||||
static void __init exynos5260_clk_gscl_init(struct device_node *np)
|
||||
{
|
||||
struct exynos5260_cmu_info cmu = {0};
|
||||
struct samsung_cmu_info cmu = {0};
|
||||
|
||||
cmu.mux_clks = gscl_mux_clks;
|
||||
cmu.nr_mux_clks = ARRAY_SIZE(gscl_mux_clks);
|
||||
|
@ -921,7 +788,7 @@ static void __init exynos5260_clk_gscl_init(struct device_node *np)
|
|||
cmu.clk_regs = gscl_clk_regs;
|
||||
cmu.nr_clk_regs = ARRAY_SIZE(gscl_clk_regs);
|
||||
|
||||
exynos5260_cmu_register_one(np, &cmu);
|
||||
samsung_cmu_register_one(np, &cmu);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos5260_clk_gscl, "samsung,exynos5260-clock-gscl",
|
||||
|
@ -1028,7 +895,7 @@ struct samsung_gate_clock isp_gate_clks[] __initdata = {
|
|||
|
||||
static void __init exynos5260_clk_isp_init(struct device_node *np)
|
||||
{
|
||||
struct exynos5260_cmu_info cmu = {0};
|
||||
struct samsung_cmu_info cmu = {0};
|
||||
|
||||
cmu.mux_clks = isp_mux_clks;
|
||||
cmu.nr_mux_clks = ARRAY_SIZE(isp_mux_clks);
|
||||
|
@ -1040,7 +907,7 @@ static void __init exynos5260_clk_isp_init(struct device_node *np)
|
|||
cmu.clk_regs = isp_clk_regs;
|
||||
cmu.nr_clk_regs = ARRAY_SIZE(isp_clk_regs);
|
||||
|
||||
exynos5260_cmu_register_one(np, &cmu);
|
||||
samsung_cmu_register_one(np, &cmu);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos5260_clk_isp, "samsung,exynos5260-clock-isp",
|
||||
|
@ -1092,7 +959,7 @@ static struct samsung_pll_clock kfc_pll_clks[] __initdata = {
|
|||
|
||||
static void __init exynos5260_clk_kfc_init(struct device_node *np)
|
||||
{
|
||||
struct exynos5260_cmu_info cmu = {0};
|
||||
struct samsung_cmu_info cmu = {0};
|
||||
|
||||
cmu.pll_clks = kfc_pll_clks;
|
||||
cmu.nr_pll_clks = ARRAY_SIZE(kfc_pll_clks);
|
||||
|
@ -1104,7 +971,7 @@ static void __init exynos5260_clk_kfc_init(struct device_node *np)
|
|||
cmu.clk_regs = kfc_clk_regs;
|
||||
cmu.nr_clk_regs = ARRAY_SIZE(kfc_clk_regs);
|
||||
|
||||
exynos5260_cmu_register_one(np, &cmu);
|
||||
samsung_cmu_register_one(np, &cmu);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos5260_clk_kfc, "samsung,exynos5260-clock-kfc",
|
||||
|
@ -1148,7 +1015,7 @@ struct samsung_gate_clock mfc_gate_clks[] __initdata = {
|
|||
|
||||
static void __init exynos5260_clk_mfc_init(struct device_node *np)
|
||||
{
|
||||
struct exynos5260_cmu_info cmu = {0};
|
||||
struct samsung_cmu_info cmu = {0};
|
||||
|
||||
cmu.mux_clks = mfc_mux_clks;
|
||||
cmu.nr_mux_clks = ARRAY_SIZE(mfc_mux_clks);
|
||||
|
@ -1160,7 +1027,7 @@ static void __init exynos5260_clk_mfc_init(struct device_node *np)
|
|||
cmu.clk_regs = mfc_clk_regs;
|
||||
cmu.nr_clk_regs = ARRAY_SIZE(mfc_clk_regs);
|
||||
|
||||
exynos5260_cmu_register_one(np, &cmu);
|
||||
samsung_cmu_register_one(np, &cmu);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos5260_clk_mfc, "samsung,exynos5260-clock-mfc",
|
||||
|
@ -1295,7 +1162,7 @@ static struct samsung_pll_clock mif_pll_clks[] __initdata = {
|
|||
|
||||
static void __init exynos5260_clk_mif_init(struct device_node *np)
|
||||
{
|
||||
struct exynos5260_cmu_info cmu = {0};
|
||||
struct samsung_cmu_info cmu = {0};
|
||||
|
||||
cmu.pll_clks = mif_pll_clks;
|
||||
cmu.nr_pll_clks = ARRAY_SIZE(mif_pll_clks);
|
||||
|
@ -1309,7 +1176,7 @@ static void __init exynos5260_clk_mif_init(struct device_node *np)
|
|||
cmu.clk_regs = mif_clk_regs;
|
||||
cmu.nr_clk_regs = ARRAY_SIZE(mif_clk_regs);
|
||||
|
||||
exynos5260_cmu_register_one(np, &cmu);
|
||||
samsung_cmu_register_one(np, &cmu);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos5260_clk_mif, "samsung,exynos5260-clock-mif",
|
||||
|
@ -1503,7 +1370,7 @@ struct samsung_gate_clock peri_gate_clks[] __initdata = {
|
|||
|
||||
static void __init exynos5260_clk_peri_init(struct device_node *np)
|
||||
{
|
||||
struct exynos5260_cmu_info cmu = {0};
|
||||
struct samsung_cmu_info cmu = {0};
|
||||
|
||||
cmu.mux_clks = peri_mux_clks;
|
||||
cmu.nr_mux_clks = ARRAY_SIZE(peri_mux_clks);
|
||||
|
@ -1515,7 +1382,7 @@ static void __init exynos5260_clk_peri_init(struct device_node *np)
|
|||
cmu.clk_regs = peri_clk_regs;
|
||||
cmu.nr_clk_regs = ARRAY_SIZE(peri_clk_regs);
|
||||
|
||||
exynos5260_cmu_register_one(np, &cmu);
|
||||
samsung_cmu_register_one(np, &cmu);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos5260_clk_peri, "samsung,exynos5260-clock-peri",
|
||||
|
@ -1959,7 +1826,7 @@ static struct samsung_pll_clock top_pll_clks[] __initdata = {
|
|||
|
||||
static void __init exynos5260_clk_top_init(struct device_node *np)
|
||||
{
|
||||
struct exynos5260_cmu_info cmu = {0};
|
||||
struct samsung_cmu_info cmu = {0};
|
||||
|
||||
cmu.pll_clks = top_pll_clks;
|
||||
cmu.nr_pll_clks = ARRAY_SIZE(top_pll_clks);
|
||||
|
@ -1975,7 +1842,7 @@ static void __init exynos5260_clk_top_init(struct device_node *np)
|
|||
cmu.clk_regs = top_clk_regs;
|
||||
cmu.nr_clk_regs = ARRAY_SIZE(top_clk_regs);
|
||||
|
||||
exynos5260_cmu_register_one(np, &cmu);
|
||||
samsung_cmu_register_one(np, &cmu);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos5260_clk_top, "samsung,exynos5260-clock-top",
|
||||
|
|
743
drivers/clk/samsung/clk-exynos7.c
Normal file
743
drivers/clk/samsung/clk-exynos7.c
Normal file
|
@ -0,0 +1,743 @@
|
|||
/*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clkdev.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include <dt-bindings/clock/exynos7-clk.h>
|
||||
|
||||
/* Register Offset definitions for CMU_TOPC (0x10570000) */
|
||||
#define CC_PLL_LOCK 0x0000
|
||||
#define BUS0_PLL_LOCK 0x0004
|
||||
#define BUS1_DPLL_LOCK 0x0008
|
||||
#define MFC_PLL_LOCK 0x000C
|
||||
#define AUD_PLL_LOCK 0x0010
|
||||
#define CC_PLL_CON0 0x0100
|
||||
#define BUS0_PLL_CON0 0x0110
|
||||
#define BUS1_DPLL_CON0 0x0120
|
||||
#define MFC_PLL_CON0 0x0130
|
||||
#define AUD_PLL_CON0 0x0140
|
||||
#define MUX_SEL_TOPC0 0x0200
|
||||
#define MUX_SEL_TOPC1 0x0204
|
||||
#define MUX_SEL_TOPC2 0x0208
|
||||
#define MUX_SEL_TOPC3 0x020C
|
||||
#define DIV_TOPC0 0x0600
|
||||
#define DIV_TOPC1 0x0604
|
||||
#define DIV_TOPC3 0x060C
|
||||
|
||||
static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
|
||||
FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_topc_bus0_pll_div4",
|
||||
"ffac_topc_bus0_pll_div2", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_topc_bus1_pll_div2", "mout_bus1_pll_ctrl", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_topc_cc_pll_div2", "mout_cc_pll_ctrl", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_topc_mfc_pll_div2", "mout_mfc_pll_ctrl", 1, 2, 0),
|
||||
};
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_TOPC */
|
||||
PNAME(mout_bus0_pll_ctrl_p) = { "fin_pll", "fout_bus0_pll" };
|
||||
PNAME(mout_bus1_pll_ctrl_p) = { "fin_pll", "fout_bus1_pll" };
|
||||
PNAME(mout_cc_pll_ctrl_p) = { "fin_pll", "fout_cc_pll" };
|
||||
PNAME(mout_mfc_pll_ctrl_p) = { "fin_pll", "fout_mfc_pll" };
|
||||
|
||||
PNAME(mout_topc_group2) = { "mout_sclk_bus0_pll_cmuc",
|
||||
"mout_sclk_bus1_pll_cmuc", "mout_sclk_cc_pll_cmuc",
|
||||
"mout_sclk_mfc_pll_cmuc" };
|
||||
|
||||
PNAME(mout_sclk_bus0_pll_cmuc_p) = { "mout_bus0_pll_ctrl",
|
||||
"ffac_topc_bus0_pll_div2", "ffac_topc_bus0_pll_div4"};
|
||||
PNAME(mout_sclk_bus1_pll_cmuc_p) = { "mout_bus1_pll_ctrl",
|
||||
"ffac_topc_bus1_pll_div2"};
|
||||
PNAME(mout_sclk_cc_pll_cmuc_p) = { "mout_cc_pll_ctrl",
|
||||
"ffac_topc_cc_pll_div2"};
|
||||
PNAME(mout_sclk_mfc_pll_cmuc_p) = { "mout_mfc_pll_ctrl",
|
||||
"ffac_topc_mfc_pll_div2"};
|
||||
|
||||
|
||||
PNAME(mout_sclk_bus0_pll_out_p) = {"mout_bus0_pll_ctrl",
|
||||
"ffac_topc_bus0_pll_div2"};
|
||||
|
||||
static unsigned long topc_clk_regs[] __initdata = {
|
||||
CC_PLL_LOCK,
|
||||
BUS0_PLL_LOCK,
|
||||
BUS1_DPLL_LOCK,
|
||||
MFC_PLL_LOCK,
|
||||
AUD_PLL_LOCK,
|
||||
CC_PLL_CON0,
|
||||
BUS0_PLL_CON0,
|
||||
BUS1_DPLL_CON0,
|
||||
MFC_PLL_CON0,
|
||||
AUD_PLL_CON0,
|
||||
MUX_SEL_TOPC0,
|
||||
MUX_SEL_TOPC1,
|
||||
MUX_SEL_TOPC2,
|
||||
MUX_SEL_TOPC3,
|
||||
DIV_TOPC0,
|
||||
DIV_TOPC1,
|
||||
DIV_TOPC3,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock topc_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_bus0_pll_ctrl", mout_bus0_pll_ctrl_p, MUX_SEL_TOPC0, 0, 1),
|
||||
MUX(0, "mout_bus1_pll_ctrl", mout_bus1_pll_ctrl_p, MUX_SEL_TOPC0, 4, 1),
|
||||
MUX(0, "mout_cc_pll_ctrl", mout_cc_pll_ctrl_p, MUX_SEL_TOPC0, 8, 1),
|
||||
MUX(0, "mout_mfc_pll_ctrl", mout_mfc_pll_ctrl_p, MUX_SEL_TOPC0, 12, 1),
|
||||
|
||||
MUX(0, "mout_sclk_bus0_pll_cmuc", mout_sclk_bus0_pll_cmuc_p,
|
||||
MUX_SEL_TOPC0, 16, 2),
|
||||
MUX(0, "mout_sclk_bus1_pll_cmuc", mout_sclk_bus1_pll_cmuc_p,
|
||||
MUX_SEL_TOPC0, 20, 1),
|
||||
MUX(0, "mout_sclk_cc_pll_cmuc", mout_sclk_cc_pll_cmuc_p,
|
||||
MUX_SEL_TOPC0, 24, 1),
|
||||
MUX(0, "mout_sclk_mfc_pll_cmuc", mout_sclk_mfc_pll_cmuc_p,
|
||||
MUX_SEL_TOPC0, 28, 1),
|
||||
|
||||
MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
|
||||
MUX_SEL_TOPC1, 16, 1),
|
||||
|
||||
MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
|
||||
|
||||
MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
|
||||
};
|
||||
|
||||
static struct samsung_div_clock topc_div_clks[] __initdata = {
|
||||
DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
|
||||
DIV_TOPC0, 4, 4),
|
||||
|
||||
DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
|
||||
DIV_TOPC1, 24, 4),
|
||||
|
||||
DIV(DOUT_SCLK_BUS0_PLL, "dout_sclk_bus0_pll", "mout_sclk_bus0_pll_out",
|
||||
DIV_TOPC3, 0, 3),
|
||||
DIV(DOUT_SCLK_BUS1_PLL, "dout_sclk_bus1_pll", "mout_bus1_pll_ctrl",
|
||||
DIV_TOPC3, 8, 3),
|
||||
DIV(DOUT_SCLK_CC_PLL, "dout_sclk_cc_pll", "mout_cc_pll_ctrl",
|
||||
DIV_TOPC3, 12, 3),
|
||||
DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
|
||||
DIV_TOPC3, 16, 3),
|
||||
};
|
||||
|
||||
static struct samsung_pll_clock topc_pll_clks[] __initdata = {
|
||||
PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
|
||||
BUS0_PLL_CON0, NULL),
|
||||
PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
|
||||
CC_PLL_CON0, NULL),
|
||||
PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
|
||||
BUS1_DPLL_CON0, NULL),
|
||||
PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
|
||||
MFC_PLL_CON0, NULL),
|
||||
PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
|
||||
AUD_PLL_CON0, NULL),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info topc_cmu_info __initdata = {
|
||||
.pll_clks = topc_pll_clks,
|
||||
.nr_pll_clks = ARRAY_SIZE(topc_pll_clks),
|
||||
.mux_clks = topc_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(topc_mux_clks),
|
||||
.div_clks = topc_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(topc_div_clks),
|
||||
.fixed_factor_clks = topc_fixed_factor_clks,
|
||||
.nr_fixed_factor_clks = ARRAY_SIZE(topc_fixed_factor_clks),
|
||||
.nr_clk_ids = TOPC_NR_CLK,
|
||||
.clk_regs = topc_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(topc_clk_regs),
|
||||
};
|
||||
|
||||
static void __init exynos7_clk_topc_init(struct device_node *np)
|
||||
{
|
||||
samsung_cmu_register_one(np, &topc_cmu_info);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
|
||||
exynos7_clk_topc_init);
|
||||
|
||||
/* Register Offset definitions for CMU_TOP0 (0x105D0000) */
|
||||
#define MUX_SEL_TOP00 0x0200
|
||||
#define MUX_SEL_TOP01 0x0204
|
||||
#define MUX_SEL_TOP03 0x020C
|
||||
#define MUX_SEL_TOP0_PERIC3 0x023C
|
||||
#define DIV_TOP03 0x060C
|
||||
#define DIV_TOP0_PERIC3 0x063C
|
||||
#define ENABLE_SCLK_TOP0_PERIC3 0x0A3C
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_TOP0 */
|
||||
PNAME(mout_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
|
||||
PNAME(mout_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll" };
|
||||
PNAME(mout_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll" };
|
||||
PNAME(mout_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll" };
|
||||
|
||||
PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
|
||||
"ffac_top0_bus0_pll_div2"};
|
||||
PNAME(mout_top0_half_bus1_pll_p) = {"mout_top0_bus1_pll",
|
||||
"ffac_top0_bus1_pll_div2"};
|
||||
PNAME(mout_top0_half_cc_pll_p) = {"mout_top0_cc_pll",
|
||||
"ffac_top0_cc_pll_div2"};
|
||||
PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
|
||||
"ffac_top0_mfc_pll_div2"};
|
||||
|
||||
PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
|
||||
"mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
|
||||
"mout_top0_half_mfc_pll"};
|
||||
|
||||
static unsigned long top0_clk_regs[] __initdata = {
|
||||
MUX_SEL_TOP00,
|
||||
MUX_SEL_TOP01,
|
||||
MUX_SEL_TOP03,
|
||||
MUX_SEL_TOP0_PERIC3,
|
||||
DIV_TOP03,
|
||||
DIV_TOP0_PERIC3,
|
||||
ENABLE_SCLK_TOP0_PERIC3,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock top0_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
|
||||
MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
|
||||
MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
|
||||
MUX(0, "mout_top0_bus0_pll", mout_bus0_pll_p, MUX_SEL_TOP00, 16, 1),
|
||||
|
||||
MUX(0, "mout_top0_half_mfc_pll", mout_top0_half_mfc_pll_p,
|
||||
MUX_SEL_TOP01, 4, 1),
|
||||
MUX(0, "mout_top0_half_cc_pll", mout_top0_half_cc_pll_p,
|
||||
MUX_SEL_TOP01, 8, 1),
|
||||
MUX(0, "mout_top0_half_bus1_pll", mout_top0_half_bus1_pll_p,
|
||||
MUX_SEL_TOP01, 12, 1),
|
||||
MUX(0, "mout_top0_half_bus0_pll", mout_top0_half_bus0_pll_p,
|
||||
MUX_SEL_TOP01, 16, 1),
|
||||
|
||||
MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
|
||||
MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
|
||||
|
||||
MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
|
||||
MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
|
||||
MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
|
||||
MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
|
||||
};
|
||||
|
||||
static struct samsung_div_clock top0_div_clks[] __initdata = {
|
||||
DIV(DOUT_ACLK_PERIC1, "dout_aclk_peric1_66", "mout_aclk_peric1_66",
|
||||
DIV_TOP03, 12, 6),
|
||||
DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
|
||||
DIV_TOP03, 20, 6),
|
||||
|
||||
DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
|
||||
DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
|
||||
DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
|
||||
DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock top0_gate_clks[] __initdata = {
|
||||
GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
|
||||
ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
|
||||
GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
|
||||
ENABLE_SCLK_TOP0_PERIC3, 8, 0, 0),
|
||||
GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_sclk_uart1",
|
||||
ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
|
||||
GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
|
||||
ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
|
||||
FFACTOR(0, "ffac_top0_bus0_pll_div2", "mout_top0_bus0_pll", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top0_bus1_pll_div2", "mout_top0_bus1_pll", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top0_cc_pll_div2", "mout_top0_cc_pll", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top0_mfc_pll_div2", "mout_top0_mfc_pll", 1, 2, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info top0_cmu_info __initdata = {
|
||||
.mux_clks = top0_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(top0_mux_clks),
|
||||
.div_clks = top0_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(top0_div_clks),
|
||||
.gate_clks = top0_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(top0_gate_clks),
|
||||
.fixed_factor_clks = top0_fixed_factor_clks,
|
||||
.nr_fixed_factor_clks = ARRAY_SIZE(top0_fixed_factor_clks),
|
||||
.nr_clk_ids = TOP0_NR_CLK,
|
||||
.clk_regs = top0_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(top0_clk_regs),
|
||||
};
|
||||
|
||||
static void __init exynos7_clk_top0_init(struct device_node *np)
|
||||
{
|
||||
samsung_cmu_register_one(np, &top0_cmu_info);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos7_clk_top0, "samsung,exynos7-clock-top0",
|
||||
exynos7_clk_top0_init);
|
||||
|
||||
/* Register Offset definitions for CMU_TOP1 (0x105E0000) */
|
||||
#define MUX_SEL_TOP10 0x0200
|
||||
#define MUX_SEL_TOP11 0x0204
|
||||
#define MUX_SEL_TOP13 0x020C
|
||||
#define MUX_SEL_TOP1_FSYS0 0x0224
|
||||
#define MUX_SEL_TOP1_FSYS1 0x0228
|
||||
#define DIV_TOP13 0x060C
|
||||
#define DIV_TOP1_FSYS0 0x0624
|
||||
#define DIV_TOP1_FSYS1 0x0628
|
||||
#define ENABLE_ACLK_TOP13 0x080C
|
||||
#define ENABLE_SCLK_TOP1_FSYS0 0x0A24
|
||||
#define ENABLE_SCLK_TOP1_FSYS1 0x0A28
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_TOP1 */
|
||||
PNAME(mout_top1_bus0_pll_p) = { "fin_pll", "dout_sclk_bus0_pll" };
|
||||
PNAME(mout_top1_bus1_pll_p) = { "fin_pll", "dout_sclk_bus1_pll_b" };
|
||||
PNAME(mout_top1_cc_pll_p) = { "fin_pll", "dout_sclk_cc_pll_b" };
|
||||
PNAME(mout_top1_mfc_pll_p) = { "fin_pll", "dout_sclk_mfc_pll_b" };
|
||||
|
||||
PNAME(mout_top1_half_bus0_pll_p) = {"mout_top1_bus0_pll",
|
||||
"ffac_top1_bus0_pll_div2"};
|
||||
PNAME(mout_top1_half_bus1_pll_p) = {"mout_top1_bus1_pll",
|
||||
"ffac_top1_bus1_pll_div2"};
|
||||
PNAME(mout_top1_half_cc_pll_p) = {"mout_top1_cc_pll",
|
||||
"ffac_top1_cc_pll_div2"};
|
||||
PNAME(mout_top1_half_mfc_pll_p) = {"mout_top1_mfc_pll",
|
||||
"ffac_top1_mfc_pll_div2"};
|
||||
|
||||
PNAME(mout_top1_group1) = {"mout_top1_half_bus0_pll",
|
||||
"mout_top1_half_bus1_pll", "mout_top1_half_cc_pll",
|
||||
"mout_top1_half_mfc_pll"};
|
||||
|
||||
static unsigned long top1_clk_regs[] __initdata = {
|
||||
MUX_SEL_TOP10,
|
||||
MUX_SEL_TOP11,
|
||||
MUX_SEL_TOP13,
|
||||
MUX_SEL_TOP1_FSYS0,
|
||||
MUX_SEL_TOP1_FSYS1,
|
||||
DIV_TOP13,
|
||||
DIV_TOP1_FSYS0,
|
||||
DIV_TOP1_FSYS1,
|
||||
ENABLE_ACLK_TOP13,
|
||||
ENABLE_SCLK_TOP1_FSYS0,
|
||||
ENABLE_SCLK_TOP1_FSYS1,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock top1_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_top1_mfc_pll", mout_top1_mfc_pll_p, MUX_SEL_TOP10, 4, 1),
|
||||
MUX(0, "mout_top1_cc_pll", mout_top1_cc_pll_p, MUX_SEL_TOP10, 8, 1),
|
||||
MUX(0, "mout_top1_bus1_pll", mout_top1_bus1_pll_p,
|
||||
MUX_SEL_TOP10, 12, 1),
|
||||
MUX(0, "mout_top1_bus0_pll", mout_top1_bus0_pll_p,
|
||||
MUX_SEL_TOP10, 16, 1),
|
||||
|
||||
MUX(0, "mout_top1_half_mfc_pll", mout_top1_half_mfc_pll_p,
|
||||
MUX_SEL_TOP11, 4, 1),
|
||||
MUX(0, "mout_top1_half_cc_pll", mout_top1_half_cc_pll_p,
|
||||
MUX_SEL_TOP11, 8, 1),
|
||||
MUX(0, "mout_top1_half_bus1_pll", mout_top1_half_bus1_pll_p,
|
||||
MUX_SEL_TOP11, 12, 1),
|
||||
MUX(0, "mout_top1_half_bus0_pll", mout_top1_half_bus0_pll_p,
|
||||
MUX_SEL_TOP11, 16, 1),
|
||||
|
||||
MUX(0, "mout_aclk_fsys1_200", mout_top1_group1, MUX_SEL_TOP13, 24, 2),
|
||||
MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
|
||||
|
||||
MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
|
||||
|
||||
MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
|
||||
MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
|
||||
};
|
||||
|
||||
static struct samsung_div_clock top1_div_clks[] __initdata = {
|
||||
DIV(DOUT_ACLK_FSYS1_200, "dout_aclk_fsys1_200", "mout_aclk_fsys1_200",
|
||||
DIV_TOP13, 24, 4),
|
||||
DIV(DOUT_ACLK_FSYS0_200, "dout_aclk_fsys0_200", "mout_aclk_fsys0_200",
|
||||
DIV_TOP13, 28, 4),
|
||||
|
||||
DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
|
||||
DIV_TOP1_FSYS0, 24, 4),
|
||||
|
||||
DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
|
||||
DIV_TOP1_FSYS1, 24, 4),
|
||||
DIV(DOUT_SCLK_MMC0, "dout_sclk_mmc0", "mout_sclk_mmc0",
|
||||
DIV_TOP1_FSYS1, 28, 4),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock top1_gate_clks[] __initdata = {
|
||||
GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
|
||||
ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
|
||||
|
||||
GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
|
||||
ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
|
||||
GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_sclk_mmc0",
|
||||
ENABLE_SCLK_TOP1_FSYS1, 28, CLK_SET_RATE_PARENT, 0),
|
||||
};
|
||||
|
||||
static struct samsung_fixed_factor_clock top1_fixed_factor_clks[] __initdata = {
|
||||
FFACTOR(0, "ffac_top1_bus0_pll_div2", "mout_top1_bus0_pll", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top1_bus1_pll_div2", "mout_top1_bus1_pll", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top1_cc_pll_div2", "mout_top1_cc_pll", 1, 2, 0),
|
||||
FFACTOR(0, "ffac_top1_mfc_pll_div2", "mout_top1_mfc_pll", 1, 2, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info top1_cmu_info __initdata = {
|
||||
.mux_clks = top1_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(top1_mux_clks),
|
||||
.div_clks = top1_div_clks,
|
||||
.nr_div_clks = ARRAY_SIZE(top1_div_clks),
|
||||
.gate_clks = top1_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(top1_gate_clks),
|
||||
.fixed_factor_clks = top1_fixed_factor_clks,
|
||||
.nr_fixed_factor_clks = ARRAY_SIZE(top1_fixed_factor_clks),
|
||||
.nr_clk_ids = TOP1_NR_CLK,
|
||||
.clk_regs = top1_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(top1_clk_regs),
|
||||
};
|
||||
|
||||
static void __init exynos7_clk_top1_init(struct device_node *np)
|
||||
{
|
||||
samsung_cmu_register_one(np, &top1_cmu_info);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos7_clk_top1, "samsung,exynos7-clock-top1",
|
||||
exynos7_clk_top1_init);
|
||||
|
||||
/* Register Offset definitions for CMU_CCORE (0x105B0000) */
|
||||
#define MUX_SEL_CCORE 0x0200
|
||||
#define DIV_CCORE 0x0600
|
||||
#define ENABLE_ACLK_CCORE0 0x0800
|
||||
#define ENABLE_ACLK_CCORE1 0x0804
|
||||
#define ENABLE_PCLK_CCORE 0x0900
|
||||
|
||||
/*
|
||||
* List of parent clocks for Muxes in CMU_CCORE
|
||||
*/
|
||||
PNAME(mout_aclk_ccore_133_p) = { "fin_pll", "dout_aclk_ccore_133" };
|
||||
|
||||
static unsigned long ccore_clk_regs[] __initdata = {
|
||||
MUX_SEL_CCORE,
|
||||
ENABLE_PCLK_CCORE,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock ccore_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_aclk_ccore_133_user", mout_aclk_ccore_133_p,
|
||||
MUX_SEL_CCORE, 1, 1),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock ccore_gate_clks[] __initdata = {
|
||||
GATE(PCLK_RTC, "pclk_rtc", "mout_aclk_ccore_133_user",
|
||||
ENABLE_PCLK_CCORE, 8, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info ccore_cmu_info __initdata = {
|
||||
.mux_clks = ccore_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(ccore_mux_clks),
|
||||
.gate_clks = ccore_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(ccore_gate_clks),
|
||||
.nr_clk_ids = CCORE_NR_CLK,
|
||||
.clk_regs = ccore_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(ccore_clk_regs),
|
||||
};
|
||||
|
||||
static void __init exynos7_clk_ccore_init(struct device_node *np)
|
||||
{
|
||||
samsung_cmu_register_one(np, &ccore_cmu_info);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos7_clk_ccore, "samsung,exynos7-clock-ccore",
|
||||
exynos7_clk_ccore_init);
|
||||
|
||||
/* Register Offset definitions for CMU_PERIC0 (0x13610000) */
|
||||
#define MUX_SEL_PERIC0 0x0200
|
||||
#define ENABLE_PCLK_PERIC0 0x0900
|
||||
#define ENABLE_SCLK_PERIC0 0x0A00
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_PERIC0 */
|
||||
PNAME(mout_aclk_peric0_66_p) = { "fin_pll", "dout_aclk_peric0_66" };
|
||||
PNAME(mout_sclk_uart0_p) = { "fin_pll", "sclk_uart0" };
|
||||
|
||||
static unsigned long peric0_clk_regs[] __initdata = {
|
||||
MUX_SEL_PERIC0,
|
||||
ENABLE_PCLK_PERIC0,
|
||||
ENABLE_SCLK_PERIC0,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock peric0_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_aclk_peric0_66_user", mout_aclk_peric0_66_p,
|
||||
MUX_SEL_PERIC0, 0, 1),
|
||||
MUX(0, "mout_sclk_uart0_user", mout_sclk_uart0_p,
|
||||
MUX_SEL_PERIC0, 16, 1),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock peric0_gate_clks[] __initdata = {
|
||||
GATE(PCLK_HSI2C0, "pclk_hsi2c0", "mout_aclk_peric0_66_user",
|
||||
ENABLE_PCLK_PERIC0, 8, 0, 0),
|
||||
GATE(PCLK_HSI2C1, "pclk_hsi2c1", "mout_aclk_peric0_66_user",
|
||||
ENABLE_PCLK_PERIC0, 9, 0, 0),
|
||||
GATE(PCLK_HSI2C4, "pclk_hsi2c4", "mout_aclk_peric0_66_user",
|
||||
ENABLE_PCLK_PERIC0, 10, 0, 0),
|
||||
GATE(PCLK_HSI2C5, "pclk_hsi2c5", "mout_aclk_peric0_66_user",
|
||||
ENABLE_PCLK_PERIC0, 11, 0, 0),
|
||||
GATE(PCLK_HSI2C9, "pclk_hsi2c9", "mout_aclk_peric0_66_user",
|
||||
ENABLE_PCLK_PERIC0, 12, 0, 0),
|
||||
GATE(PCLK_HSI2C10, "pclk_hsi2c10", "mout_aclk_peric0_66_user",
|
||||
ENABLE_PCLK_PERIC0, 13, 0, 0),
|
||||
GATE(PCLK_HSI2C11, "pclk_hsi2c11", "mout_aclk_peric0_66_user",
|
||||
ENABLE_PCLK_PERIC0, 14, 0, 0),
|
||||
GATE(PCLK_UART0, "pclk_uart0", "mout_aclk_peric0_66_user",
|
||||
ENABLE_PCLK_PERIC0, 16, 0, 0),
|
||||
GATE(PCLK_ADCIF, "pclk_adcif", "mout_aclk_peric0_66_user",
|
||||
ENABLE_PCLK_PERIC0, 20, 0, 0),
|
||||
GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
|
||||
ENABLE_PCLK_PERIC0, 21, 0, 0),
|
||||
|
||||
GATE(SCLK_UART0, "sclk_uart0_user", "mout_sclk_uart0_user",
|
||||
ENABLE_SCLK_PERIC0, 16, 0, 0),
|
||||
GATE(SCLK_PWM, "sclk_pwm", "fin_pll", ENABLE_SCLK_PERIC0, 21, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info peric0_cmu_info __initdata = {
|
||||
.mux_clks = peric0_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
|
||||
.gate_clks = peric0_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
|
||||
.nr_clk_ids = PERIC0_NR_CLK,
|
||||
.clk_regs = peric0_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
|
||||
};
|
||||
|
||||
static void __init exynos7_clk_peric0_init(struct device_node *np)
|
||||
{
|
||||
samsung_cmu_register_one(np, &peric0_cmu_info);
|
||||
}
|
||||
|
||||
/* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
|
||||
#define MUX_SEL_PERIC10 0x0200
|
||||
#define MUX_SEL_PERIC11 0x0204
|
||||
#define ENABLE_PCLK_PERIC1 0x0900
|
||||
#define ENABLE_SCLK_PERIC10 0x0A00
|
||||
|
||||
CLK_OF_DECLARE(exynos7_clk_peric0, "samsung,exynos7-clock-peric0",
|
||||
exynos7_clk_peric0_init);
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_PERIC1 */
|
||||
PNAME(mout_aclk_peric1_66_p) = { "fin_pll", "dout_aclk_peric1_66" };
|
||||
PNAME(mout_sclk_uart1_p) = { "fin_pll", "sclk_uart1" };
|
||||
PNAME(mout_sclk_uart2_p) = { "fin_pll", "sclk_uart2" };
|
||||
PNAME(mout_sclk_uart3_p) = { "fin_pll", "sclk_uart3" };
|
||||
|
||||
static unsigned long peric1_clk_regs[] __initdata = {
|
||||
MUX_SEL_PERIC10,
|
||||
MUX_SEL_PERIC11,
|
||||
ENABLE_PCLK_PERIC1,
|
||||
ENABLE_SCLK_PERIC10,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
|
||||
MUX_SEL_PERIC10, 0, 1),
|
||||
|
||||
MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
|
||||
MUX_SEL_PERIC11, 20, 1),
|
||||
MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
|
||||
MUX_SEL_PERIC11, 24, 1),
|
||||
MUX(0, "mout_sclk_uart3_user", mout_sclk_uart3_p,
|
||||
MUX_SEL_PERIC11, 28, 1),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
|
||||
GATE(PCLK_HSI2C2, "pclk_hsi2c2", "mout_aclk_peric1_66_user",
|
||||
ENABLE_PCLK_PERIC1, 4, 0, 0),
|
||||
GATE(PCLK_HSI2C3, "pclk_hsi2c3", "mout_aclk_peric1_66_user",
|
||||
ENABLE_PCLK_PERIC1, 5, 0, 0),
|
||||
GATE(PCLK_HSI2C6, "pclk_hsi2c6", "mout_aclk_peric1_66_user",
|
||||
ENABLE_PCLK_PERIC1, 6, 0, 0),
|
||||
GATE(PCLK_HSI2C7, "pclk_hsi2c7", "mout_aclk_peric1_66_user",
|
||||
ENABLE_PCLK_PERIC1, 7, 0, 0),
|
||||
GATE(PCLK_HSI2C8, "pclk_hsi2c8", "mout_aclk_peric1_66_user",
|
||||
ENABLE_PCLK_PERIC1, 8, 0, 0),
|
||||
GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
|
||||
ENABLE_PCLK_PERIC1, 9, 0, 0),
|
||||
GATE(PCLK_UART2, "pclk_uart2", "mout_aclk_peric1_66_user",
|
||||
ENABLE_PCLK_PERIC1, 10, 0, 0),
|
||||
GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
|
||||
ENABLE_PCLK_PERIC1, 11, 0, 0),
|
||||
|
||||
GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
|
||||
ENABLE_SCLK_PERIC10, 9, 0, 0),
|
||||
GATE(SCLK_UART2, "sclk_uart2_user", "mout_sclk_uart2_user",
|
||||
ENABLE_SCLK_PERIC10, 10, 0, 0),
|
||||
GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
|
||||
ENABLE_SCLK_PERIC10, 11, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info peric1_cmu_info __initdata = {
|
||||
.mux_clks = peric1_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
|
||||
.gate_clks = peric1_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
|
||||
.nr_clk_ids = PERIC1_NR_CLK,
|
||||
.clk_regs = peric1_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
|
||||
};
|
||||
|
||||
static void __init exynos7_clk_peric1_init(struct device_node *np)
|
||||
{
|
||||
samsung_cmu_register_one(np, &peric1_cmu_info);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos7_clk_peric1, "samsung,exynos7-clock-peric1",
|
||||
exynos7_clk_peric1_init);
|
||||
|
||||
/* Register Offset definitions for CMU_PERIS (0x10040000) */
|
||||
#define MUX_SEL_PERIS 0x0200
|
||||
#define ENABLE_PCLK_PERIS 0x0900
|
||||
#define ENABLE_PCLK_PERIS_SECURE_CHIPID 0x0910
|
||||
#define ENABLE_SCLK_PERIS 0x0A00
|
||||
#define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0A10
|
||||
|
||||
/* List of parent clocks for Muxes in CMU_PERIS */
|
||||
PNAME(mout_aclk_peris_66_p) = { "fin_pll", "dout_aclk_peris_66" };
|
||||
|
||||
static unsigned long peris_clk_regs[] __initdata = {
|
||||
MUX_SEL_PERIS,
|
||||
ENABLE_PCLK_PERIS,
|
||||
ENABLE_PCLK_PERIS_SECURE_CHIPID,
|
||||
ENABLE_SCLK_PERIS,
|
||||
ENABLE_SCLK_PERIS_SECURE_CHIPID,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock peris_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_aclk_peris_66_user",
|
||||
mout_aclk_peris_66_p, MUX_SEL_PERIS, 0, 1),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock peris_gate_clks[] __initdata = {
|
||||
GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
|
||||
ENABLE_PCLK_PERIS, 6, 0, 0),
|
||||
GATE(PCLK_TMU, "pclk_tmu_apbif", "mout_aclk_peris_66_user",
|
||||
ENABLE_PCLK_PERIS, 10, 0, 0),
|
||||
|
||||
GATE(PCLK_CHIPID, "pclk_chipid", "mout_aclk_peris_66_user",
|
||||
ENABLE_PCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
|
||||
GATE(SCLK_CHIPID, "sclk_chipid", "fin_pll",
|
||||
ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, 0, 0),
|
||||
|
||||
GATE(SCLK_TMU, "sclk_tmu", "fin_pll", ENABLE_SCLK_PERIS, 10, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info peris_cmu_info __initdata = {
|
||||
.mux_clks = peris_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(peris_mux_clks),
|
||||
.gate_clks = peris_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
|
||||
.nr_clk_ids = PERIS_NR_CLK,
|
||||
.clk_regs = peris_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
|
||||
};
|
||||
|
||||
static void __init exynos7_clk_peris_init(struct device_node *np)
|
||||
{
|
||||
samsung_cmu_register_one(np, &peris_cmu_info);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
|
||||
exynos7_clk_peris_init);
|
||||
|
||||
/* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
|
||||
#define MUX_SEL_FSYS00 0x0200
|
||||
#define MUX_SEL_FSYS01 0x0204
|
||||
#define ENABLE_ACLK_FSYS01 0x0804
|
||||
|
||||
/*
|
||||
* List of parent clocks for Muxes in CMU_FSYS0
|
||||
*/
|
||||
PNAME(mout_aclk_fsys0_200_p) = { "fin_pll", "dout_aclk_fsys0_200" };
|
||||
PNAME(mout_sclk_mmc2_p) = { "fin_pll", "sclk_mmc2" };
|
||||
|
||||
static unsigned long fsys0_clk_regs[] __initdata = {
|
||||
MUX_SEL_FSYS00,
|
||||
MUX_SEL_FSYS01,
|
||||
ENABLE_ACLK_FSYS01,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_aclk_fsys0_200_user", mout_aclk_fsys0_200_p,
|
||||
MUX_SEL_FSYS00, 24, 1),
|
||||
|
||||
MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
|
||||
GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
|
||||
ENABLE_ACLK_FSYS01, 31, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info fsys0_cmu_info __initdata = {
|
||||
.mux_clks = fsys0_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(fsys0_mux_clks),
|
||||
.gate_clks = fsys0_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(fsys0_gate_clks),
|
||||
.nr_clk_ids = TOP1_NR_CLK,
|
||||
.clk_regs = fsys0_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(fsys0_clk_regs),
|
||||
};
|
||||
|
||||
static void __init exynos7_clk_fsys0_init(struct device_node *np)
|
||||
{
|
||||
samsung_cmu_register_one(np, &fsys0_cmu_info);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos7_clk_fsys0, "samsung,exynos7-clock-fsys0",
|
||||
exynos7_clk_fsys0_init);
|
||||
|
||||
/* Register Offset definitions for CMU_FSYS1 (0x156E0000) */
|
||||
#define MUX_SEL_FSYS10 0x0200
|
||||
#define MUX_SEL_FSYS11 0x0204
|
||||
#define ENABLE_ACLK_FSYS1 0x0800
|
||||
|
||||
/*
|
||||
* List of parent clocks for Muxes in CMU_FSYS1
|
||||
*/
|
||||
PNAME(mout_aclk_fsys1_200_p) = { "fin_pll", "dout_aclk_fsys1_200" };
|
||||
PNAME(mout_sclk_mmc0_p) = { "fin_pll", "sclk_mmc0" };
|
||||
PNAME(mout_sclk_mmc1_p) = { "fin_pll", "sclk_mmc1" };
|
||||
|
||||
static unsigned long fsys1_clk_regs[] __initdata = {
|
||||
MUX_SEL_FSYS10,
|
||||
MUX_SEL_FSYS11,
|
||||
ENABLE_ACLK_FSYS1,
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock fsys1_mux_clks[] __initdata = {
|
||||
MUX(0, "mout_aclk_fsys1_200_user", mout_aclk_fsys1_200_p,
|
||||
MUX_SEL_FSYS10, 28, 1),
|
||||
|
||||
MUX(0, "mout_sclk_mmc1_user", mout_sclk_mmc1_p, MUX_SEL_FSYS11, 24, 1),
|
||||
MUX(0, "mout_sclk_mmc0_user", mout_sclk_mmc0_p, MUX_SEL_FSYS11, 28, 1),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock fsys1_gate_clks[] __initdata = {
|
||||
GATE(ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys1_200_user",
|
||||
ENABLE_ACLK_FSYS1, 29, 0, 0),
|
||||
GATE(ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys1_200_user",
|
||||
ENABLE_ACLK_FSYS1, 30, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_cmu_info fsys1_cmu_info __initdata = {
|
||||
.mux_clks = fsys1_mux_clks,
|
||||
.nr_mux_clks = ARRAY_SIZE(fsys1_mux_clks),
|
||||
.gate_clks = fsys1_gate_clks,
|
||||
.nr_gate_clks = ARRAY_SIZE(fsys1_gate_clks),
|
||||
.nr_clk_ids = TOP1_NR_CLK,
|
||||
.clk_regs = fsys1_clk_regs,
|
||||
.nr_clk_regs = ARRAY_SIZE(fsys1_clk_regs),
|
||||
};
|
||||
|
||||
static void __init exynos7_clk_fsys1_init(struct device_node *np)
|
||||
{
|
||||
samsung_cmu_register_one(np, &fsys1_cmu_info);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
|
||||
exynos7_clk_fsys1_init);
|
|
@ -482,6 +482,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = {
|
|||
|
||||
#define PLL46XX_VSEL_MASK (1)
|
||||
#define PLL46XX_MDIV_MASK (0x1FF)
|
||||
#define PLL1460X_MDIV_MASK (0x3FF)
|
||||
|
||||
#define PLL46XX_PDIV_MASK (0x3F)
|
||||
#define PLL46XX_SDIV_MASK (0x7)
|
||||
#define PLL46XX_VSEL_SHIFT (27)
|
||||
|
@ -511,13 +513,15 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw,
|
|||
|
||||
pll_con0 = __raw_readl(pll->con_reg);
|
||||
pll_con1 = __raw_readl(pll->con_reg + 4);
|
||||
mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
|
||||
mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ?
|
||||
PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK);
|
||||
pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
|
||||
kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK :
|
||||
pll_con1 & PLL46XX_KDIV_MASK;
|
||||
|
||||
shift = pll->type == pll_4600 ? 16 : 10;
|
||||
shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10;
|
||||
|
||||
fvco *= (mdiv << shift) + kdiv;
|
||||
do_div(fvco, (pdiv << sdiv));
|
||||
fvco >>= shift;
|
||||
|
@ -573,14 +577,21 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate,
|
|||
lock = 0xffff;
|
||||
|
||||
/* Set PLL PMS and VSEL values. */
|
||||
con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
|
||||
if (pll->type == pll_1460x) {
|
||||
con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
|
||||
(PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
|
||||
(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT));
|
||||
} else {
|
||||
con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) |
|
||||
(PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) |
|
||||
(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) |
|
||||
(PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT));
|
||||
con0 |= rate->vsel << PLL46XX_VSEL_SHIFT;
|
||||
}
|
||||
|
||||
con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) |
|
||||
(rate->pdiv << PLL46XX_PDIV_SHIFT) |
|
||||
(rate->sdiv << PLL46XX_SDIV_SHIFT) |
|
||||
(rate->vsel << PLL46XX_VSEL_SHIFT);
|
||||
(rate->sdiv << PLL46XX_SDIV_SHIFT);
|
||||
|
||||
/* Set PLL K, MFR and MRR values. */
|
||||
con1 = __raw_readl(pll->con_reg + 0x4);
|
||||
|
@ -1190,6 +1201,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
|||
/* clk_ops for 35xx and 2550 are similar */
|
||||
case pll_35xx:
|
||||
case pll_2550:
|
||||
case pll_1450x:
|
||||
case pll_1451x:
|
||||
case pll_1452x:
|
||||
if (!pll->rate_table)
|
||||
init.ops = &samsung_pll35xx_clk_min_ops;
|
||||
else
|
||||
|
@ -1223,6 +1237,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
|||
case pll_4600:
|
||||
case pll_4650:
|
||||
case pll_4650c:
|
||||
case pll_1460x:
|
||||
if (!pll->rate_table)
|
||||
init.ops = &samsung_pll46xx_clk_min_ops;
|
||||
else
|
||||
|
|
|
@ -33,6 +33,10 @@ enum samsung_pll_type {
|
|||
pll_s3c2440_mpll,
|
||||
pll_2550xx,
|
||||
pll_2650xx,
|
||||
pll_1450x,
|
||||
pll_1451x,
|
||||
pll_1452x,
|
||||
pll_1460x,
|
||||
};
|
||||
|
||||
#define PLL_35XX_RATE(_rate, _m, _p, _s) \
|
||||
|
|
|
@ -14,6 +14,8 @@
|
|||
#include <linux/syscore_ops.h>
|
||||
#include "clk.h"
|
||||
|
||||
static LIST_HEAD(clock_reg_cache_list);
|
||||
|
||||
void samsung_clk_save(void __iomem *base,
|
||||
struct samsung_clk_reg_dump *rd,
|
||||
unsigned int num_regs)
|
||||
|
@ -313,3 +315,99 @@ unsigned long _get_rate(const char *clk_name)
|
|||
|
||||
return clk_get_rate(clk);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int samsung_clk_suspend(void)
|
||||
{
|
||||
struct samsung_clock_reg_cache *reg_cache;
|
||||
|
||||
list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
|
||||
samsung_clk_save(reg_cache->reg_base, reg_cache->rdump,
|
||||
reg_cache->rd_num);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void samsung_clk_resume(void)
|
||||
{
|
||||
struct samsung_clock_reg_cache *reg_cache;
|
||||
|
||||
list_for_each_entry(reg_cache, &clock_reg_cache_list, node)
|
||||
samsung_clk_restore(reg_cache->reg_base, reg_cache->rdump,
|
||||
reg_cache->rd_num);
|
||||
}
|
||||
|
||||
static struct syscore_ops samsung_clk_syscore_ops = {
|
||||
.suspend = samsung_clk_suspend,
|
||||
.resume = samsung_clk_resume,
|
||||
};
|
||||
|
||||
static void samsung_clk_sleep_init(void __iomem *reg_base,
|
||||
const unsigned long *rdump,
|
||||
unsigned long nr_rdump)
|
||||
{
|
||||
struct samsung_clock_reg_cache *reg_cache;
|
||||
|
||||
reg_cache = kzalloc(sizeof(struct samsung_clock_reg_cache),
|
||||
GFP_KERNEL);
|
||||
if (!reg_cache)
|
||||
panic("could not allocate register reg_cache.\n");
|
||||
reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump);
|
||||
|
||||
if (!reg_cache->rdump)
|
||||
panic("could not allocate register dump storage.\n");
|
||||
|
||||
if (list_empty(&clock_reg_cache_list))
|
||||
register_syscore_ops(&samsung_clk_syscore_ops);
|
||||
|
||||
reg_cache->reg_base = reg_base;
|
||||
reg_cache->rd_num = nr_rdump;
|
||||
list_add_tail(®_cache->node, &clock_reg_cache_list);
|
||||
}
|
||||
|
||||
#else
|
||||
static void samsung_clk_sleep_init(void __iomem *reg_base,
|
||||
const unsigned long *rdump,
|
||||
unsigned long nr_rdump) {}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Common function which registers plls, muxes, dividers and gates
|
||||
* for each CMU. It also add CMU register list to register cache.
|
||||
*/
|
||||
void __init samsung_cmu_register_one(struct device_node *np,
|
||||
struct samsung_cmu_info *cmu)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
struct samsung_clk_provider *ctx;
|
||||
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base)
|
||||
panic("%s: failed to map registers\n", __func__);
|
||||
|
||||
ctx = samsung_clk_init(np, reg_base, cmu->nr_clk_ids);
|
||||
if (!ctx)
|
||||
panic("%s: unable to alllocate ctx\n", __func__);
|
||||
|
||||
if (cmu->pll_clks)
|
||||
samsung_clk_register_pll(ctx, cmu->pll_clks, cmu->nr_pll_clks,
|
||||
reg_base);
|
||||
if (cmu->mux_clks)
|
||||
samsung_clk_register_mux(ctx, cmu->mux_clks,
|
||||
cmu->nr_mux_clks);
|
||||
if (cmu->div_clks)
|
||||
samsung_clk_register_div(ctx, cmu->div_clks, cmu->nr_div_clks);
|
||||
if (cmu->gate_clks)
|
||||
samsung_clk_register_gate(ctx, cmu->gate_clks,
|
||||
cmu->nr_gate_clks);
|
||||
if (cmu->fixed_clks)
|
||||
samsung_clk_register_fixed_rate(ctx, cmu->fixed_clks,
|
||||
cmu->nr_fixed_clks);
|
||||
if (cmu->fixed_factor_clks)
|
||||
samsung_clk_register_fixed_factor(ctx, cmu->fixed_factor_clks,
|
||||
cmu->nr_fixed_factor_clks);
|
||||
if (cmu->clk_regs)
|
||||
samsung_clk_sleep_init(reg_base, cmu->clk_regs,
|
||||
cmu->nr_clk_regs);
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
|
|
|
@ -324,6 +324,40 @@ struct samsung_pll_clock {
|
|||
__PLL(_typ, _id, NULL, _name, _pname, CLK_GET_RATE_NOCACHE, \
|
||||
_lock, _con, _rtable, _alias)
|
||||
|
||||
struct samsung_clock_reg_cache {
|
||||
struct list_head node;
|
||||
void __iomem *reg_base;
|
||||
struct samsung_clk_reg_dump *rdump;
|
||||
unsigned int rd_num;
|
||||
};
|
||||
|
||||
struct samsung_cmu_info {
|
||||
/* list of pll clocks and respective count */
|
||||
struct samsung_pll_clock *pll_clks;
|
||||
unsigned int nr_pll_clks;
|
||||
/* list of mux clocks and respective count */
|
||||
struct samsung_mux_clock *mux_clks;
|
||||
unsigned int nr_mux_clks;
|
||||
/* list of div clocks and respective count */
|
||||
struct samsung_div_clock *div_clks;
|
||||
unsigned int nr_div_clks;
|
||||
/* list of gate clocks and respective count */
|
||||
struct samsung_gate_clock *gate_clks;
|
||||
unsigned int nr_gate_clks;
|
||||
/* list of fixed clocks and respective count */
|
||||
struct samsung_fixed_rate_clock *fixed_clks;
|
||||
unsigned int nr_fixed_clks;
|
||||
/* list of fixed factor clocks and respective count */
|
||||
struct samsung_fixed_factor_clock *fixed_factor_clks;
|
||||
unsigned int nr_fixed_factor_clks;
|
||||
/* total number of clocks with IDs assigned*/
|
||||
unsigned int nr_clk_ids;
|
||||
|
||||
/* list and number of clocks registers */
|
||||
unsigned long *clk_regs;
|
||||
unsigned int nr_clk_regs;
|
||||
};
|
||||
|
||||
extern struct samsung_clk_provider *__init samsung_clk_init(
|
||||
struct device_node *np, void __iomem *base,
|
||||
unsigned long nr_clks);
|
||||
|
@ -362,6 +396,9 @@ extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
|||
struct samsung_pll_clock *pll_list,
|
||||
unsigned int nr_clk, void __iomem *base);
|
||||
|
||||
extern void __init samsung_cmu_register_one(struct device_node *,
|
||||
struct samsung_cmu_info *);
|
||||
|
||||
extern unsigned long _get_rate(const char *clk_name);
|
||||
|
||||
extern void samsung_clk_save(void __iomem *base,
|
||||
|
|
360
include/dt-bindings/clock/exynos4415.h
Normal file
360
include/dt-bindings/clock/exynos4415.h
Normal file
|
@ -0,0 +1,360 @@
|
|||
/*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* Author: Chanwoo Choi <cw00.choi@samsung.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Device Tree binding constants for Samsung Exynos4415 clock controllers.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
|
||||
#define _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H
|
||||
|
||||
/*
|
||||
* Let each exported clock get a unique index, which is used on DT-enabled
|
||||
* platforms to lookup the clock from a clock specifier. These indices are
|
||||
* therefore considered an ABI and so must not be changed. This implies
|
||||
* that new clocks should be added either in free spaces between clock groups
|
||||
* or at the end.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Main CMU
|
||||
*/
|
||||
|
||||
#define CLK_OSCSEL 1
|
||||
#define CLK_FIN_PLL 2
|
||||
#define CLK_FOUT_APLL 3
|
||||
#define CLK_FOUT_MPLL 4
|
||||
#define CLK_FOUT_EPLL 5
|
||||
#define CLK_FOUT_G3D_PLL 6
|
||||
#define CLK_FOUT_ISP_PLL 7
|
||||
#define CLK_FOUT_DISP_PLL 8
|
||||
|
||||
/* Muxes */
|
||||
#define CLK_MOUT_MPLL_USER_L 16
|
||||
#define CLK_MOUT_GDL 17
|
||||
#define CLK_MOUT_MPLL_USER_R 18
|
||||
#define CLK_MOUT_GDR 19
|
||||
#define CLK_MOUT_EBI 20
|
||||
#define CLK_MOUT_ACLK_200 21
|
||||
#define CLK_MOUT_ACLK_160 22
|
||||
#define CLK_MOUT_ACLK_100 23
|
||||
#define CLK_MOUT_ACLK_266 24
|
||||
#define CLK_MOUT_G3D_PLL 25
|
||||
#define CLK_MOUT_EPLL 26
|
||||
#define CLK_MOUT_EBI_1 27
|
||||
#define CLK_MOUT_ISP_PLL 28
|
||||
#define CLK_MOUT_DISP_PLL 29
|
||||
#define CLK_MOUT_MPLL_USER_T 30
|
||||
#define CLK_MOUT_ACLK_400_MCUISP 31
|
||||
#define CLK_MOUT_G3D_PLLSRC 32
|
||||
#define CLK_MOUT_CSIS1 33
|
||||
#define CLK_MOUT_CSIS0 34
|
||||
#define CLK_MOUT_CAM1 35
|
||||
#define CLK_MOUT_FIMC3_LCLK 36
|
||||
#define CLK_MOUT_FIMC2_LCLK 37
|
||||
#define CLK_MOUT_FIMC1_LCLK 38
|
||||
#define CLK_MOUT_FIMC0_LCLK 39
|
||||
#define CLK_MOUT_MFC 40
|
||||
#define CLK_MOUT_MFC_1 41
|
||||
#define CLK_MOUT_MFC_0 42
|
||||
#define CLK_MOUT_G3D 43
|
||||
#define CLK_MOUT_G3D_1 44
|
||||
#define CLK_MOUT_G3D_0 45
|
||||
#define CLK_MOUT_MIPI0 46
|
||||
#define CLK_MOUT_FIMD0 47
|
||||
#define CLK_MOUT_TSADC_ISP 48
|
||||
#define CLK_MOUT_UART_ISP 49
|
||||
#define CLK_MOUT_SPI1_ISP 50
|
||||
#define CLK_MOUT_SPI0_ISP 51
|
||||
#define CLK_MOUT_PWM_ISP 52
|
||||
#define CLK_MOUT_AUDIO0 53
|
||||
#define CLK_MOUT_TSADC 54
|
||||
#define CLK_MOUT_MMC2 55
|
||||
#define CLK_MOUT_MMC1 56
|
||||
#define CLK_MOUT_MMC0 57
|
||||
#define CLK_MOUT_UART3 58
|
||||
#define CLK_MOUT_UART2 59
|
||||
#define CLK_MOUT_UART1 60
|
||||
#define CLK_MOUT_UART0 61
|
||||
#define CLK_MOUT_SPI2 62
|
||||
#define CLK_MOUT_SPI1 63
|
||||
#define CLK_MOUT_SPI0 64
|
||||
#define CLK_MOUT_SPDIF 65
|
||||
#define CLK_MOUT_AUDIO2 66
|
||||
#define CLK_MOUT_AUDIO1 67
|
||||
#define CLK_MOUT_MPLL_USER_C 68
|
||||
#define CLK_MOUT_HPM 69
|
||||
#define CLK_MOUT_CORE 70
|
||||
#define CLK_MOUT_APLL 71
|
||||
#define CLK_MOUT_PXLASYNC_CSIS1_FIMC 72
|
||||
#define CLK_MOUT_PXLASYNC_CSIS0_FIMC 73
|
||||
#define CLK_MOUT_JPEG 74
|
||||
#define CLK_MOUT_JPEG1 75
|
||||
#define CLK_MOUT_JPEG0 76
|
||||
#define CLK_MOUT_ACLK_ISP0_300 77
|
||||
#define CLK_MOUT_ACLK_ISP0_400 78
|
||||
#define CLK_MOUT_ACLK_ISP0_300_USER 79
|
||||
#define CLK_MOUT_ACLK_ISP1_300 80
|
||||
#define CLK_MOUT_ACLK_ISP1_300_USER 81
|
||||
#define CLK_MOUT_HDMI 82
|
||||
|
||||
/* Dividers */
|
||||
#define CLK_DIV_GPL 90
|
||||
#define CLK_DIV_GDL 91
|
||||
#define CLK_DIV_GPR 92
|
||||
#define CLK_DIV_GDR 93
|
||||
#define CLK_DIV_ACLK_400_MCUISP 94
|
||||
#define CLK_DIV_EBI 95
|
||||
#define CLK_DIV_ACLK_200 96
|
||||
#define CLK_DIV_ACLK_160 97
|
||||
#define CLK_DIV_ACLK_100 98
|
||||
#define CLK_DIV_ACLK_266 99
|
||||
#define CLK_DIV_CSIS1 100
|
||||
#define CLK_DIV_CSIS0 101
|
||||
#define CLK_DIV_CAM1 102
|
||||
#define CLK_DIV_FIMC3_LCLK 103
|
||||
#define CLK_DIV_FIMC2_LCLK 104
|
||||
#define CLK_DIV_FIMC1_LCLK 105
|
||||
#define CLK_DIV_FIMC0_LCLK 106
|
||||
#define CLK_DIV_TV_BLK 107
|
||||
#define CLK_DIV_MFC 108
|
||||
#define CLK_DIV_G3D 109
|
||||
#define CLK_DIV_MIPI0_PRE 110
|
||||
#define CLK_DIV_MIPI0 111
|
||||
#define CLK_DIV_FIMD0 112
|
||||
#define CLK_DIV_UART_ISP 113
|
||||
#define CLK_DIV_SPI1_ISP_PRE 114
|
||||
#define CLK_DIV_SPI1_ISP 115
|
||||
#define CLK_DIV_SPI0_ISP_PRE 116
|
||||
#define CLK_DIV_SPI0_ISP 117
|
||||
#define CLK_DIV_PWM_ISP 118
|
||||
#define CLK_DIV_PCM0 119
|
||||
#define CLK_DIV_AUDIO0 120
|
||||
#define CLK_DIV_TSADC_PRE 121
|
||||
#define CLK_DIV_TSADC 122
|
||||
#define CLK_DIV_MMC1_PRE 123
|
||||
#define CLK_DIV_MMC1 124
|
||||
#define CLK_DIV_MMC0_PRE 125
|
||||
#define CLK_DIV_MMC0 126
|
||||
#define CLK_DIV_MMC2_PRE 127
|
||||
#define CLK_DIV_MMC2 128
|
||||
#define CLK_DIV_UART3 129
|
||||
#define CLK_DIV_UART2 130
|
||||
#define CLK_DIV_UART1 131
|
||||
#define CLK_DIV_UART0 132
|
||||
#define CLK_DIV_SPI1_PRE 133
|
||||
#define CLK_DIV_SPI1 134
|
||||
#define CLK_DIV_SPI0_PRE 135
|
||||
#define CLK_DIV_SPI0 136
|
||||
#define CLK_DIV_SPI2_PRE 137
|
||||
#define CLK_DIV_SPI2 138
|
||||
#define CLK_DIV_PCM2 139
|
||||
#define CLK_DIV_AUDIO2 140
|
||||
#define CLK_DIV_PCM1 141
|
||||
#define CLK_DIV_AUDIO1 142
|
||||
#define CLK_DIV_I2S1 143
|
||||
#define CLK_DIV_PXLASYNC_CSIS1_FIMC 144
|
||||
#define CLK_DIV_PXLASYNC_CSIS0_FIMC 145
|
||||
#define CLK_DIV_JPEG 146
|
||||
#define CLK_DIV_CORE2 147
|
||||
#define CLK_DIV_APLL 148
|
||||
#define CLK_DIV_PCLK_DBG 149
|
||||
#define CLK_DIV_ATB 150
|
||||
#define CLK_DIV_PERIPH 151
|
||||
#define CLK_DIV_COREM1 152
|
||||
#define CLK_DIV_COREM0 153
|
||||
#define CLK_DIV_CORE 154
|
||||
#define CLK_DIV_HPM 155
|
||||
#define CLK_DIV_COPY 156
|
||||
|
||||
/* Gates */
|
||||
#define CLK_ASYNC_G3D 180
|
||||
#define CLK_ASYNC_MFCL 181
|
||||
#define CLK_ASYNC_TVX 182
|
||||
#define CLK_PPMULEFT 183
|
||||
#define CLK_GPIO_LEFT 184
|
||||
#define CLK_PPMUIMAGE 185
|
||||
#define CLK_QEMDMA2 186
|
||||
#define CLK_QEROTATOR 187
|
||||
#define CLK_SMMUMDMA2 188
|
||||
#define CLK_SMMUROTATOR 189
|
||||
#define CLK_MDMA2 190
|
||||
#define CLK_ROTATOR 191
|
||||
#define CLK_ASYNC_ISPMX 192
|
||||
#define CLK_ASYNC_MAUDIOX 193
|
||||
#define CLK_ASYNC_MFCR 194
|
||||
#define CLK_ASYNC_FSYSD 195
|
||||
#define CLK_ASYNC_LCD0X 196
|
||||
#define CLK_ASYNC_CAMX 197
|
||||
#define CLK_PPMURIGHT 198
|
||||
#define CLK_GPIO_RIGHT 199
|
||||
#define CLK_ANTIRBK_APBIF 200
|
||||
#define CLK_EFUSE_WRITER_APBIF 201
|
||||
#define CLK_MONOCNT 202
|
||||
#define CLK_TZPC6 203
|
||||
#define CLK_PROVISIONKEY1 204
|
||||
#define CLK_PROVISIONKEY0 205
|
||||
#define CLK_CMU_ISPPART 206
|
||||
#define CLK_TMU_APBIF 207
|
||||
#define CLK_KEYIF 208
|
||||
#define CLK_RTC 209
|
||||
#define CLK_WDT 210
|
||||
#define CLK_MCT 211
|
||||
#define CLK_SECKEY 212
|
||||
#define CLK_HDMI_CEC 213
|
||||
#define CLK_TZPC5 214
|
||||
#define CLK_TZPC4 215
|
||||
#define CLK_TZPC3 216
|
||||
#define CLK_TZPC2 217
|
||||
#define CLK_TZPC1 218
|
||||
#define CLK_TZPC0 219
|
||||
#define CLK_CMU_COREPART 220
|
||||
#define CLK_CMU_TOPPART 221
|
||||
#define CLK_PMU_APBIF 222
|
||||
#define CLK_SYSREG 223
|
||||
#define CLK_CHIP_ID 224
|
||||
#define CLK_SMMUFIMC_LITE2 225
|
||||
#define CLK_FIMC_LITE2 226
|
||||
#define CLK_PIXELASYNCM1 227
|
||||
#define CLK_PIXELASYNCM0 228
|
||||
#define CLK_PPMUCAMIF 229
|
||||
#define CLK_SMMUJPEG 230
|
||||
#define CLK_SMMUFIMC3 231
|
||||
#define CLK_SMMUFIMC2 232
|
||||
#define CLK_SMMUFIMC1 233
|
||||
#define CLK_SMMUFIMC0 234
|
||||
#define CLK_JPEG 235
|
||||
#define CLK_CSIS1 236
|
||||
#define CLK_CSIS0 237
|
||||
#define CLK_FIMC3 238
|
||||
#define CLK_FIMC2 239
|
||||
#define CLK_FIMC1 240
|
||||
#define CLK_FIMC0 241
|
||||
#define CLK_PPMUTV 242
|
||||
#define CLK_SMMUTV 243
|
||||
#define CLK_HDMI 244
|
||||
#define CLK_MIXER 245
|
||||
#define CLK_VP 246
|
||||
#define CLK_PPMUMFC_R 247
|
||||
#define CLK_PPMUMFC_L 248
|
||||
#define CLK_SMMUMFC_R 249
|
||||
#define CLK_SMMUMFC_L 250
|
||||
#define CLK_MFC 251
|
||||
#define CLK_PPMUG3D 252
|
||||
#define CLK_G3D 253
|
||||
#define CLK_PPMULCD0 254
|
||||
#define CLK_SMMUFIMD0 255
|
||||
#define CLK_DSIM0 256
|
||||
#define CLK_SMIES 257
|
||||
#define CLK_MIE0 258
|
||||
#define CLK_FIMD0 259
|
||||
#define CLK_TSADC 260
|
||||
#define CLK_PPMUFILE 261
|
||||
#define CLK_NFCON 262
|
||||
#define CLK_USBDEVICE 263
|
||||
#define CLK_USBHOST 264
|
||||
#define CLK_SROMC 265
|
||||
#define CLK_SDMMC2 266
|
||||
#define CLK_SDMMC1 267
|
||||
#define CLK_SDMMC0 268
|
||||
#define CLK_PDMA1 269
|
||||
#define CLK_PDMA0 270
|
||||
#define CLK_SPDIF 271
|
||||
#define CLK_PWM 272
|
||||
#define CLK_PCM2 273
|
||||
#define CLK_PCM1 274
|
||||
#define CLK_I2S1 275
|
||||
#define CLK_SPI2 276
|
||||
#define CLK_SPI1 277
|
||||
#define CLK_SPI0 278
|
||||
#define CLK_I2CHDMI 279
|
||||
#define CLK_I2C7 280
|
||||
#define CLK_I2C6 281
|
||||
#define CLK_I2C5 282
|
||||
#define CLK_I2C4 283
|
||||
#define CLK_I2C3 284
|
||||
#define CLK_I2C2 285
|
||||
#define CLK_I2C1 286
|
||||
#define CLK_I2C0 287
|
||||
#define CLK_UART3 288
|
||||
#define CLK_UART2 289
|
||||
#define CLK_UART1 290
|
||||
#define CLK_UART0 291
|
||||
|
||||
/* Special clocks */
|
||||
#define CLK_SCLK_PXLAYSNC_CSIS1_FIMC 330
|
||||
#define CLK_SCLK_PXLAYSNC_CSIS0_FIMC 331
|
||||
#define CLK_SCLK_JPEG 332
|
||||
#define CLK_SCLK_CSIS1 333
|
||||
#define CLK_SCLK_CSIS0 334
|
||||
#define CLK_SCLK_CAM1 335
|
||||
#define CLK_SCLK_FIMC3_LCLK 336
|
||||
#define CLK_SCLK_FIMC2_LCLK 337
|
||||
#define CLK_SCLK_FIMC1_LCLK 338
|
||||
#define CLK_SCLK_FIMC0_LCLK 339
|
||||
#define CLK_SCLK_PIXEL 340
|
||||
#define CLK_SCLK_HDMI 341
|
||||
#define CLK_SCLK_MIXER 342
|
||||
#define CLK_SCLK_MFC 343
|
||||
#define CLK_SCLK_G3D 344
|
||||
#define CLK_SCLK_MIPIDPHY4L 345
|
||||
#define CLK_SCLK_MIPI0 346
|
||||
#define CLK_SCLK_MDNIE0 347
|
||||
#define CLK_SCLK_FIMD0 348
|
||||
#define CLK_SCLK_PCM0 349
|
||||
#define CLK_SCLK_AUDIO0 350
|
||||
#define CLK_SCLK_TSADC 351
|
||||
#define CLK_SCLK_EBI 352
|
||||
#define CLK_SCLK_MMC2 353
|
||||
#define CLK_SCLK_MMC1 354
|
||||
#define CLK_SCLK_MMC0 355
|
||||
#define CLK_SCLK_I2S 356
|
||||
#define CLK_SCLK_PCM2 357
|
||||
#define CLK_SCLK_PCM1 358
|
||||
#define CLK_SCLK_AUDIO2 359
|
||||
#define CLK_SCLK_AUDIO1 360
|
||||
#define CLK_SCLK_SPDIF 361
|
||||
#define CLK_SCLK_SPI2 362
|
||||
#define CLK_SCLK_SPI1 363
|
||||
#define CLK_SCLK_SPI0 364
|
||||
#define CLK_SCLK_UART3 365
|
||||
#define CLK_SCLK_UART2 366
|
||||
#define CLK_SCLK_UART1 367
|
||||
#define CLK_SCLK_UART0 368
|
||||
#define CLK_SCLK_HDMIPHY 369
|
||||
|
||||
/*
|
||||
* Total number of clocks of main CMU.
|
||||
* NOTE: Must be equal to last clock ID increased by one.
|
||||
*/
|
||||
#define CLK_NR_CLKS 370
|
||||
|
||||
/*
|
||||
* CMU DMC
|
||||
*/
|
||||
#define CLK_DMC_FOUT_MPLL 1
|
||||
#define CLK_DMC_FOUT_BPLL 2
|
||||
|
||||
#define CLK_DMC_MOUT_MPLL 3
|
||||
#define CLK_DMC_MOUT_BPLL 4
|
||||
#define CLK_DMC_MOUT_DPHY 5
|
||||
#define CLK_DMC_MOUT_DMC_BUS 6
|
||||
|
||||
#define CLK_DMC_DIV_DMC 7
|
||||
#define CLK_DMC_DIV_DPHY 8
|
||||
#define CLK_DMC_DIV_DMC_PRE 9
|
||||
#define CLK_DMC_DIV_DMCP 10
|
||||
#define CLK_DMC_DIV_DMCD 11
|
||||
#define CLK_DMC_DIV_MPLL_PRE 12
|
||||
|
||||
/*
|
||||
* Total number of clocks of CMU_DMC.
|
||||
* NOTE: Must be equal to highest clock ID increased by one.
|
||||
*/
|
||||
#define NR_CLKS_DMC 13
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS4415_CLOCK_H */
|
92
include/dt-bindings/clock/exynos7-clk.h
Normal file
92
include/dt-bindings/clock/exynos7-clk.h
Normal file
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* Author: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS7_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS7_H
|
||||
|
||||
/* TOPC */
|
||||
#define DOUT_ACLK_PERIS 1
|
||||
#define DOUT_SCLK_BUS0_PLL 2
|
||||
#define DOUT_SCLK_BUS1_PLL 3
|
||||
#define DOUT_SCLK_CC_PLL 4
|
||||
#define DOUT_SCLK_MFC_PLL 5
|
||||
#define DOUT_ACLK_CCORE_133 6
|
||||
#define TOPC_NR_CLK 7
|
||||
|
||||
/* TOP0 */
|
||||
#define DOUT_ACLK_PERIC1 1
|
||||
#define DOUT_ACLK_PERIC0 2
|
||||
#define CLK_SCLK_UART0 3
|
||||
#define CLK_SCLK_UART1 4
|
||||
#define CLK_SCLK_UART2 5
|
||||
#define CLK_SCLK_UART3 6
|
||||
#define TOP0_NR_CLK 7
|
||||
|
||||
/* TOP1 */
|
||||
#define DOUT_ACLK_FSYS1_200 1
|
||||
#define DOUT_ACLK_FSYS0_200 2
|
||||
#define DOUT_SCLK_MMC2 3
|
||||
#define DOUT_SCLK_MMC1 4
|
||||
#define DOUT_SCLK_MMC0 5
|
||||
#define CLK_SCLK_MMC2 6
|
||||
#define CLK_SCLK_MMC1 7
|
||||
#define CLK_SCLK_MMC0 8
|
||||
#define TOP1_NR_CLK 9
|
||||
|
||||
/* CCORE */
|
||||
#define PCLK_RTC 1
|
||||
#define CCORE_NR_CLK 2
|
||||
|
||||
/* PERIC0 */
|
||||
#define PCLK_UART0 1
|
||||
#define SCLK_UART0 2
|
||||
#define PCLK_HSI2C0 3
|
||||
#define PCLK_HSI2C1 4
|
||||
#define PCLK_HSI2C4 5
|
||||
#define PCLK_HSI2C5 6
|
||||
#define PCLK_HSI2C9 7
|
||||
#define PCLK_HSI2C10 8
|
||||
#define PCLK_HSI2C11 9
|
||||
#define PCLK_PWM 10
|
||||
#define SCLK_PWM 11
|
||||
#define PCLK_ADCIF 12
|
||||
#define PERIC0_NR_CLK 13
|
||||
|
||||
/* PERIC1 */
|
||||
#define PCLK_UART1 1
|
||||
#define PCLK_UART2 2
|
||||
#define PCLK_UART3 3
|
||||
#define SCLK_UART1 4
|
||||
#define SCLK_UART2 5
|
||||
#define SCLK_UART3 6
|
||||
#define PCLK_HSI2C2 7
|
||||
#define PCLK_HSI2C3 8
|
||||
#define PCLK_HSI2C6 9
|
||||
#define PCLK_HSI2C7 10
|
||||
#define PCLK_HSI2C8 11
|
||||
#define PERIC1_NR_CLK 12
|
||||
|
||||
/* PERIS */
|
||||
#define PCLK_CHIPID 1
|
||||
#define SCLK_CHIPID 2
|
||||
#define PCLK_WDT 3
|
||||
#define PCLK_TMU 4
|
||||
#define SCLK_TMU 5
|
||||
#define PERIS_NR_CLK 6
|
||||
|
||||
/* FSYS0 */
|
||||
#define ACLK_MMC2 1
|
||||
#define FSYS0_NR_CLK 2
|
||||
|
||||
/* FSYS1 */
|
||||
#define ACLK_MMC1 1
|
||||
#define ACLK_MMC0 2
|
||||
#define FSYS1_NR_CLK 3
|
||||
|
||||
#endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */
|
Loading…
Reference in a new issue