mtd: rawnand: brcmnand: exec_op implementation
exec_op implementation for Broadcom STB, Broadband and iProc SoC This adds exec_op and removes the legacy interface. Based on changes proposed by Boris Brezillon. Link:4ec6f8d8d8Link:11b4acffd7Signed-off-by: David Regan <dregan@broadcom.com> [Miquel Raynal: Misc style fixes] Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20231125012438.15191-4-dregan@broadcom.com
This commit is contained in:
David Regan
Miquel Raynal
parent
c86b63b82f
commit
3c8260ce76
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@ -625,6 +625,8 @@ enum {
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/* Only for v7.2 */
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#define ACC_CONTROL_ECC_EXT_SHIFT 13
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static u8 brcmnand_status(struct brcmnand_host *host);
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static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl)
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{
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#if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA)
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@ -1022,19 +1024,6 @@ static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
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return -1;
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}
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static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
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{
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struct brcmnand_controller *ctrl = host->ctrl;
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int shift = brcmnand_sector_1k_shift(ctrl);
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u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
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BRCMNAND_CS_ACC_CONTROL);
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if (shift < 0)
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return 0;
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return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
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}
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static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
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{
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struct brcmnand_controller *ctrl = host->ctrl;
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@ -1074,6 +1063,9 @@ static int bcmnand_ctrl_poll_status(struct brcmnand_host *host,
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limit = jiffies + msecs_to_jiffies(timeout_ms);
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do {
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if (mask & INTFC_FLASH_STATUS)
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brcmnand_status(host);
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val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
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if ((val & mask) == expected_val)
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return 0;
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@ -1085,6 +1077,9 @@ static int bcmnand_ctrl_poll_status(struct brcmnand_host *host,
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* do a final check after time out in case the CPU was busy and the driver
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* did not get enough time to perform the polling to avoid false alarms
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*/
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if (mask & INTFC_FLASH_STATUS)
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brcmnand_status(host);
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val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
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if ((val & mask) == expected_val)
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return 0;
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@ -1388,7 +1383,8 @@ static void brcmnand_wp(struct mtd_info *mtd, int wp)
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return;
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brcmnand_set_wp(ctrl, wp);
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nand_status_op(chip, NULL);
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/* force controller operation to update internal copy of NAND chip status */
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brcmnand_status(host);
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/* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */
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ret = bcmnand_ctrl_poll_status(host,
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NAND_CTRL_RDY |
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@ -1644,16 +1640,6 @@ static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
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cmd << brcmnand_cmd_shift(ctrl));
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}
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/***********************************************************************
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* NAND MTD API: read/program/erase
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***********************************************************************/
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static void brcmnand_cmd_ctrl(struct nand_chip *chip, int dat,
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unsigned int ctrl)
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{
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/* intentionally left blank */
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}
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static bool brcmstb_nand_wait_for_completion(struct nand_chip *chip)
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{
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struct brcmnand_host *host = nand_get_controller_data(chip);
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@ -1704,6 +1690,26 @@ static int brcmnand_waitfunc(struct nand_chip *chip)
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INTFC_FLASH_STATUS;
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}
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static u8 brcmnand_status(struct brcmnand_host *host)
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{
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struct nand_chip *chip = &host->chip;
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struct mtd_info *mtd = nand_to_mtd(chip);
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brcmnand_set_cmd_addr(mtd, 0);
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brcmnand_send_cmd(host, CMD_STATUS_READ);
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return brcmnand_waitfunc(chip);
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}
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static u8 brcmnand_reset(struct brcmnand_host *host)
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{
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struct nand_chip *chip = &host->chip;
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brcmnand_send_cmd(host, CMD_FLASH_RESET);
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return brcmnand_waitfunc(chip);
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}
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enum {
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LLOP_RE = BIT(16),
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LLOP_WE = BIT(17),
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@ -1753,190 +1759,6 @@ static int brcmnand_low_level_op(struct brcmnand_host *host,
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return brcmnand_waitfunc(chip);
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}
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static void brcmnand_cmdfunc(struct nand_chip *chip, unsigned command,
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int column, int page_addr)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct brcmnand_host *host = nand_get_controller_data(chip);
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struct brcmnand_controller *ctrl = host->ctrl;
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u64 addr = (u64)page_addr << chip->page_shift;
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int native_cmd = 0;
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if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
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command == NAND_CMD_RNDOUT)
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addr = (u64)column;
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/* Avoid propagating a negative, don't-care address */
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else if (page_addr < 0)
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addr = 0;
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dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
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(unsigned long long)addr);
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host->last_cmd = command;
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host->last_byte = 0;
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host->last_addr = addr;
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switch (command) {
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case NAND_CMD_RESET:
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native_cmd = CMD_FLASH_RESET;
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break;
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case NAND_CMD_STATUS:
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native_cmd = CMD_STATUS_READ;
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break;
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case NAND_CMD_READID:
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native_cmd = CMD_DEVICE_ID_READ;
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break;
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case NAND_CMD_READOOB:
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native_cmd = CMD_SPARE_AREA_READ;
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break;
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case NAND_CMD_ERASE1:
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native_cmd = CMD_BLOCK_ERASE;
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brcmnand_wp(mtd, 0);
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break;
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case NAND_CMD_PARAM:
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native_cmd = CMD_PARAMETER_READ;
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break;
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case NAND_CMD_SET_FEATURES:
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case NAND_CMD_GET_FEATURES:
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brcmnand_low_level_op(host, LL_OP_CMD, command, false);
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brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
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break;
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case NAND_CMD_RNDOUT:
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native_cmd = CMD_PARAMETER_CHANGE_COL;
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addr &= ~((u64)(FC_BYTES - 1));
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/*
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* HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
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* NB: hwcfg.sector_size_1k may not be initialized yet
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*/
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if (brcmnand_get_sector_size_1k(host)) {
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host->hwcfg.sector_size_1k =
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brcmnand_get_sector_size_1k(host);
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brcmnand_set_sector_size_1k(host, 0);
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}
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break;
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}
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if (!native_cmd)
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return;
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brcmnand_set_cmd_addr(mtd, addr);
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brcmnand_send_cmd(host, native_cmd);
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brcmnand_waitfunc(chip);
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if (native_cmd == CMD_PARAMETER_READ ||
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native_cmd == CMD_PARAMETER_CHANGE_COL) {
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/* Copy flash cache word-wise */
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u32 *flash_cache = (u32 *)ctrl->flash_cache;
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int i;
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brcmnand_soc_data_bus_prepare(ctrl->soc, true);
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/*
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* Must cache the FLASH_CACHE now, since changes in
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* SECTOR_SIZE_1K may invalidate it
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*/
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for (i = 0; i < FC_WORDS; i++)
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/*
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* Flash cache is big endian for parameter pages, at
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* least on STB SoCs
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*/
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flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i));
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brcmnand_soc_data_bus_unprepare(ctrl->soc, true);
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/* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
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if (host->hwcfg.sector_size_1k)
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brcmnand_set_sector_size_1k(host,
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host->hwcfg.sector_size_1k);
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}
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/* Re-enable protection is necessary only after erase */
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if (command == NAND_CMD_ERASE1)
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brcmnand_wp(mtd, 1);
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}
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static uint8_t brcmnand_read_byte(struct nand_chip *chip)
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{
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struct brcmnand_host *host = nand_get_controller_data(chip);
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struct brcmnand_controller *ctrl = host->ctrl;
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uint8_t ret = 0;
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int addr, offs;
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switch (host->last_cmd) {
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case NAND_CMD_READID:
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if (host->last_byte < 4)
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ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
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(24 - (host->last_byte << 3));
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else if (host->last_byte < 8)
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ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
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(56 - (host->last_byte << 3));
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break;
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case NAND_CMD_READOOB:
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ret = oob_reg_read(ctrl, host->last_byte);
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break;
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case NAND_CMD_STATUS:
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ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
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INTFC_FLASH_STATUS;
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if (wp_on) /* hide WP status */
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ret |= NAND_STATUS_WP;
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break;
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case NAND_CMD_PARAM:
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case NAND_CMD_RNDOUT:
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addr = host->last_addr + host->last_byte;
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offs = addr & (FC_BYTES - 1);
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/* At FC_BYTES boundary, switch to next column */
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if (host->last_byte > 0 && offs == 0)
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nand_change_read_column_op(chip, addr, NULL, 0, false);
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ret = ctrl->flash_cache[offs];
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break;
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case NAND_CMD_GET_FEATURES:
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if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
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ret = 0;
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} else {
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bool last = host->last_byte ==
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ONFI_SUBFEATURE_PARAM_LEN - 1;
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brcmnand_low_level_op(host, LL_OP_RD, 0, last);
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ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
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}
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}
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dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
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host->last_byte++;
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return ret;
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}
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static void brcmnand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++, buf++)
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*buf = brcmnand_read_byte(chip);
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}
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static void brcmnand_write_buf(struct nand_chip *chip, const uint8_t *buf,
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int len)
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{
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int i;
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struct brcmnand_host *host = nand_get_controller_data(chip);
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switch (host->last_cmd) {
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case NAND_CMD_SET_FEATURES:
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for (i = 0; i < len; i++)
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brcmnand_low_level_op(host, LL_OP_WR, buf[i],
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(i + 1) == len);
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break;
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default:
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BUG();
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break;
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}
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}
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/*
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* Kick EDU engine
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*/
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@ -2346,8 +2168,9 @@ static int brcmnand_read_page(struct nand_chip *chip, uint8_t *buf,
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct brcmnand_host *host = nand_get_controller_data(chip);
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u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
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u64 addr = (u64)page << chip->page_shift;
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nand_read_page_op(chip, page, 0, NULL, 0);
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host->last_addr = addr;
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return brcmnand_read(mtd, chip, host->last_addr,
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mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
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@ -2360,8 +2183,9 @@ static int brcmnand_read_page_raw(struct nand_chip *chip, uint8_t *buf,
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struct mtd_info *mtd = nand_to_mtd(chip);
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u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
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int ret;
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u64 addr = (u64)page << chip->page_shift;
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nand_read_page_op(chip, page, 0, NULL, 0);
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host->last_addr = addr;
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brcmnand_set_ecc_enabled(host, 0);
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ret = brcmnand_read(mtd, chip, host->last_addr,
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@ -2469,11 +2293,11 @@ static int brcmnand_write_page(struct nand_chip *chip, const uint8_t *buf,
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct brcmnand_host *host = nand_get_controller_data(chip);
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void *oob = oob_required ? chip->oob_poi : NULL;
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u64 addr = (u64)page << chip->page_shift;
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nand_prog_page_begin_op(chip, page, 0, NULL, 0);
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brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
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host->last_addr = addr;
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return nand_prog_page_end_op(chip);
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return brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
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}
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static int brcmnand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
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@ -2482,13 +2306,15 @@ static int brcmnand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct brcmnand_host *host = nand_get_controller_data(chip);
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void *oob = oob_required ? chip->oob_poi : NULL;
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u64 addr = (u64)page << chip->page_shift;
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int ret = 0;
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nand_prog_page_begin_op(chip, page, 0, NULL, 0);
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host->last_addr = addr;
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brcmnand_set_ecc_enabled(host, 0);
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brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
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ret = brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
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brcmnand_set_ecc_enabled(host, 1);
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return nand_prog_page_end_op(chip);
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return ret;
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}
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static int brcmnand_write_oob(struct nand_chip *chip, int page)
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@ -2512,6 +2338,130 @@ static int brcmnand_write_oob_raw(struct nand_chip *chip, int page)
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return ret;
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}
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static int brcmnand_exec_instr(struct brcmnand_host *host, int i,
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const struct nand_operation *op)
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{
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const struct nand_op_instr *instr = &op->instrs[i];
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struct brcmnand_controller *ctrl = host->ctrl;
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const u8 *out;
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bool last_op;
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int ret = 0;
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u8 *in;
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/*
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* The controller needs to be aware of the last command in the operation
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* (WAITRDY excepted).
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*/
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last_op = ((i == (op->ninstrs - 1)) && (instr->type != NAND_OP_WAITRDY_INSTR)) ||
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((i == (op->ninstrs - 2)) && (op->instrs[i+1].type == NAND_OP_WAITRDY_INSTR));
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switch (instr->type) {
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case NAND_OP_CMD_INSTR:
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brcmnand_low_level_op(host, LL_OP_CMD, instr->ctx.cmd.opcode, last_op);
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break;
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case NAND_OP_ADDR_INSTR:
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for (i = 0; i < instr->ctx.addr.naddrs; i++)
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brcmnand_low_level_op(host, LL_OP_ADDR, instr->ctx.addr.addrs[i],
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last_op && (i == (instr->ctx.addr.naddrs - 1)));
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break;
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case NAND_OP_DATA_IN_INSTR:
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in = instr->ctx.data.buf.in;
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for (i = 0; i < instr->ctx.data.len; i++) {
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brcmnand_low_level_op(host, LL_OP_RD, 0,
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last_op && (i == (instr->ctx.data.len - 1)));
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in[i] = brcmnand_read_reg(host->ctrl, BRCMNAND_LL_RDATA);
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}
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break;
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case NAND_OP_DATA_OUT_INSTR:
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out = instr->ctx.data.buf.out;
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for (i = 0; i < instr->ctx.data.len; i++)
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brcmnand_low_level_op(host, LL_OP_WR, out[i],
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last_op && (i == (instr->ctx.data.len - 1)));
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break;
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case NAND_OP_WAITRDY_INSTR:
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ret = bcmnand_ctrl_poll_status(host, NAND_CTRL_RDY, NAND_CTRL_RDY, 0);
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break;
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default:
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dev_err(ctrl->dev, "unsupported instruction type: %d\n",
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instr->type);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int brcmnand_op_is_status(const struct nand_operation *op)
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{
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if ((op->ninstrs == 2) &&
|
||||
(op->instrs[0].type == NAND_OP_CMD_INSTR) &&
|
||||
(op->instrs[0].ctx.cmd.opcode == NAND_CMD_STATUS) &&
|
||||
(op->instrs[1].type == NAND_OP_DATA_IN_INSTR))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int brcmnand_op_is_reset(const struct nand_operation *op)
|
||||
{
|
||||
if ((op->ninstrs == 2) &&
|
||||
(op->instrs[0].type == NAND_OP_CMD_INSTR) &&
|
||||
(op->instrs[0].ctx.cmd.opcode == NAND_CMD_RESET) &&
|
||||
(op->instrs[1].type == NAND_OP_WAITRDY_INSTR))
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int brcmnand_exec_op(struct nand_chip *chip,
|
||||
const struct nand_operation *op,
|
||||
bool check_only)
|
||||
{
|
||||
struct brcmnand_host *host = nand_get_controller_data(chip);
|
||||
struct mtd_info *mtd = nand_to_mtd(chip);
|
||||
u8 *status;
|
||||
unsigned int i;
|
||||
int ret = 0;
|
||||
|
||||
if (check_only)
|
||||
return 0;
|
||||
|
||||
if (brcmnand_op_is_status(op)) {
|
||||
status = op->instrs[1].ctx.data.buf.in;
|
||||
*status = brcmnand_status(host);
|
||||
|
||||
return 0;
|
||||
}
|
||||
else if (brcmnand_op_is_reset(op)) {
|
||||
ret = brcmnand_reset(host);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
brcmnand_wp(mtd, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (op->deassert_wp)
|
||||
brcmnand_wp(mtd, 0);
|
||||
|
||||
for (i = 0; i < op->ninstrs; i++) {
|
||||
ret = brcmnand_exec_instr(host, i, op);
|
||||
if (ret)
|
||||
break;
|
||||
}
|
||||
|
||||
if (op->deassert_wp)
|
||||
brcmnand_wp(mtd, 1);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
* Per-CS setup (1 NAND device)
|
||||
***********************************************************************/
|
||||
|
|
@ -2822,6 +2772,7 @@ static int brcmnand_attach_chip(struct nand_chip *chip)
|
|||
|
||||
static const struct nand_controller_ops brcmnand_controller_ops = {
|
||||
.attach_chip = brcmnand_attach_chip,
|
||||
.exec_op = brcmnand_exec_op,
|
||||
};
|
||||
|
||||
static int brcmnand_init_cs(struct brcmnand_host *host,
|
||||
|
|
@ -2846,13 +2797,6 @@ static int brcmnand_init_cs(struct brcmnand_host *host,
|
|||
mtd->owner = THIS_MODULE;
|
||||
mtd->dev.parent = dev;
|
||||
|
||||
chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl;
|
||||
chip->legacy.cmdfunc = brcmnand_cmdfunc;
|
||||
chip->legacy.waitfunc = brcmnand_waitfunc;
|
||||
chip->legacy.read_byte = brcmnand_read_byte;
|
||||
chip->legacy.read_buf = brcmnand_read_buf;
|
||||
chip->legacy.write_buf = brcmnand_write_buf;
|
||||
|
||||
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
|
||||
chip->ecc.read_page = brcmnand_read_page;
|
||||
chip->ecc.write_page = brcmnand_write_page;
|
||||
|
|
@ -2864,6 +2808,7 @@ static int brcmnand_init_cs(struct brcmnand_host *host,
|
|||
chip->ecc.write_oob = brcmnand_write_oob;
|
||||
|
||||
chip->controller = &ctrl->controller;
|
||||
ctrl->controller.controller_wp = 1;
|
||||
|
||||
/*
|
||||
* The bootloader might have configured 16bit mode but
|
||||
|
|
|
|||
Loading…
Reference in New Issue