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drm/amd/pp: Add update_avfs call when set_power_state
when Overdrive voltage, need to disable AVFS. when OverDriv engine clock, need to recalculate AVFS voltage by disable/enable avfs feature. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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49fd66e5d5
commit
3c9d1fde7f
1 changed files with 57 additions and 28 deletions
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@ -91,7 +91,6 @@ enum DPM_EVENT_SRC {
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DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4
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};
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static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable);
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static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic);
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static int smu7_force_clock_level(struct pp_hwmgr *hwmgr,
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enum pp_clock_type type, uint32_t mask);
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@ -1351,6 +1350,58 @@ static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
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return 0;
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}
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static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
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{
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struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
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if (smu_data == NULL)
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return -EINVAL;
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if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
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return 0;
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if (enable) {
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if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
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CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
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hwmgr, PPSMC_MSG_EnableAvfs),
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"Failed to enable AVFS!",
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return -EINVAL);
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}
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} else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
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CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) {
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
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hwmgr, PPSMC_MSG_DisableAvfs),
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"Failed to disable AVFS!",
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return -EINVAL);
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}
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return 0;
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}
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static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
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{
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struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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if (smu_data == NULL)
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return -EINVAL;
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if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
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return 0;
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if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) {
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smu7_avfs_control(hwmgr, false);
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} else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) {
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smu7_avfs_control(hwmgr, false);
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smu7_avfs_control(hwmgr, true);
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} else {
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smu7_avfs_control(hwmgr, true);
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}
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return 0;
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}
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int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
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{
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int tmp_result, result = 0;
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@ -3842,6 +3893,11 @@ static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
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"Failed to populate and upload SCLK MCLK DPM levels!",
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result = tmp_result);
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tmp_result = smu7_update_avfs(hwmgr);
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PP_ASSERT_WITH_CODE((0 == tmp_result),
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"Failed to update avfs voltages!",
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result = tmp_result);
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tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input);
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PP_ASSERT_WITH_CODE((0 == tmp_result),
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"Failed to generate DPM level enabled mask!",
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@ -4626,33 +4682,6 @@ static int smu7_set_power_profile_state(struct pp_hwmgr *hwmgr,
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return result;
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}
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static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable)
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{
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struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
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if (smu_data == NULL)
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return -EINVAL;
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if (smu_data->avfs.avfs_btc_status == AVFS_BTC_NOTSUPPORTED)
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return 0;
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if (enable) {
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if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
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CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
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hwmgr, PPSMC_MSG_EnableAvfs),
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"Failed to enable AVFS!",
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return -EINVAL);
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} else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
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CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON))
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PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(
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hwmgr, PPSMC_MSG_DisableAvfs),
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"Failed to disable AVFS!",
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return -EINVAL);
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return 0;
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}
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static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
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uint32_t virtual_addr_low,
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uint32_t virtual_addr_hi,
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