mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-05 16:37:50 +00:00
Merge remote-tracking branches 'asoc/topic/sam9x5_wm8731', 'asoc/topic/sgtl5000' and 'asoc/topic/sun8i-codec' into asoc-next
This commit is contained in:
commit
3d0a352a55
3 changed files with 90 additions and 11 deletions
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@ -49,13 +49,13 @@ static int sam9x5_wm8731_init(struct snd_soc_pcm_runtime *rtd)
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struct device *dev = rtd->dev;
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struct device *dev = rtd->dev;
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int ret;
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int ret;
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dev_dbg(dev, "ASoC: %s called\n", __func__);
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dev_dbg(dev, "%s called\n", __func__);
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/* set the codec system clock for DAC and ADC */
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/* set the codec system clock for DAC and ADC */
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ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL,
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ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL,
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MCLK_RATE, SND_SOC_CLOCK_IN);
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MCLK_RATE, SND_SOC_CLOCK_IN);
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if (ret < 0) {
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if (ret < 0) {
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dev_err(dev, "ASoC: Failed to set WM8731 SYSCLK: %d\n", ret);
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dev_err(dev, "Failed to set WM8731 SYSCLK: %d\n", ret);
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return ret;
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return ret;
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}
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}
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@ -146,8 +146,7 @@ static int sam9x5_wm8731_driver_probe(struct platform_device *pdev)
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ret = atmel_ssc_set_audio(priv->ssc_id);
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ret = atmel_ssc_set_audio(priv->ssc_id);
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if (ret != 0) {
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if (ret != 0) {
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dev_err(&pdev->dev,
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dev_err(&pdev->dev, "Failed to set SSC %d for audio: %d\n",
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"ASoC: Failed to set SSC %d for audio: %d\n",
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ret, priv->ssc_id);
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ret, priv->ssc_id);
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goto out;
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goto out;
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}
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}
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@ -157,12 +156,11 @@ static int sam9x5_wm8731_driver_probe(struct platform_device *pdev)
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ret = snd_soc_register_card(card);
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ret = snd_soc_register_card(card);
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if (ret) {
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if (ret) {
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dev_err(&pdev->dev,
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dev_err(&pdev->dev, "Platform device allocation failed\n");
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"ASoC: Platform device allocation failed\n");
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goto out_put_audio;
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goto out_put_audio;
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}
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}
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dev_dbg(&pdev->dev, "ASoC: %s ok\n", __func__);
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dev_dbg(&pdev->dev, "%s ok\n", __func__);
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return ret;
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return ret;
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@ -1332,10 +1332,13 @@ static int sgtl5000_i2c_probe(struct i2c_client *client,
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sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
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sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
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if (IS_ERR(sgtl5000->mclk)) {
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if (IS_ERR(sgtl5000->mclk)) {
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ret = PTR_ERR(sgtl5000->mclk);
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ret = PTR_ERR(sgtl5000->mclk);
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dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
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/* Defer the probe to see if the clk will be provided later */
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/* Defer the probe to see if the clk will be provided later */
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if (ret == -ENOENT)
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if (ret == -ENOENT)
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ret = -EPROBE_DEFER;
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ret = -EPROBE_DEFER;
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if (ret != -EPROBE_DEFER)
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dev_err(&client->dev, "Failed to get mclock: %d\n",
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ret);
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goto disable_regs;
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goto disable_regs;
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}
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}
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@ -1389,7 +1392,7 @@ static int sgtl5000_i2c_probe(struct i2c_client *client,
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ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
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ana_pwr |= SGTL5000_LINEREG_D_POWERUP;
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dev_info(&client->dev,
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dev_info(&client->dev,
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"Using internal LDO instead of VDDD: check ER1\n");
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"Using internal LDO instead of VDDD: check ER1 erratum\n");
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} else {
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} else {
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/* using external LDO for VDDD
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/* using external LDO for VDDD
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* Clear startup powerup and simple powerup
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* Clear startup powerup and simple powerup
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@ -37,9 +37,11 @@
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#define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0
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#define SUN8I_SYSCLK_CTL_SYSCLK_SRC 0
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#define SUN8I_MOD_CLK_ENA 0x010
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#define SUN8I_MOD_CLK_ENA 0x010
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#define SUN8I_MOD_CLK_ENA_AIF1 15
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#define SUN8I_MOD_CLK_ENA_AIF1 15
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#define SUN8I_MOD_CLK_ENA_ADC 3
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#define SUN8I_MOD_CLK_ENA_DAC 2
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#define SUN8I_MOD_CLK_ENA_DAC 2
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#define SUN8I_MOD_RST_CTL 0x014
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#define SUN8I_MOD_RST_CTL 0x014
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#define SUN8I_MOD_RST_CTL_AIF1 15
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#define SUN8I_MOD_RST_CTL_AIF1 15
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#define SUN8I_MOD_RST_CTL_ADC 3
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#define SUN8I_MOD_RST_CTL_DAC 2
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#define SUN8I_MOD_RST_CTL_DAC 2
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#define SUN8I_SYS_SR_CTRL 0x018
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#define SUN8I_SYS_SR_CTRL 0x018
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#define SUN8I_SYS_SR_CTRL_AIF1_FS 12
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#define SUN8I_SYS_SR_CTRL_AIF1_FS 12
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@ -54,9 +56,25 @@
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#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4
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#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ 4
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#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4)
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#define SUN8I_AIF1CLK_CTRL_AIF1_WORD_SIZ_16 (1 << 4)
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#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2
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#define SUN8I_AIF1CLK_CTRL_AIF1_DATA_FMT 2
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#define SUN8I_AIF1_ADCDAT_CTRL 0x044
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#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA 15
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#define SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA 14
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#define SUN8I_AIF1_DACDAT_CTRL 0x048
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#define SUN8I_AIF1_DACDAT_CTRL 0x048
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#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15
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#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0L_ENA 15
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#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14
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#define SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA 14
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#define SUN8I_AIF1_MXR_SRC 0x04c
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#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L 15
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#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL 14
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#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL 13
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#define SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR 12
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#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R 11
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#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR 10
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#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR 9
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#define SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL 8
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#define SUN8I_ADC_DIG_CTRL 0x100
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#define SUN8I_ADC_DIG_CTRL_ENDA 15
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#define SUN8I_ADC_DIG_CTRL_ADOUT_DTS 2
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#define SUN8I_ADC_DIG_CTRL_ADOUT_DLY 1
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#define SUN8I_DAC_DIG_CTRL 0x120
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#define SUN8I_DAC_DIG_CTRL 0x120
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#define SUN8I_DAC_DIG_CTRL_ENDA 15
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#define SUN8I_DAC_DIG_CTRL_ENDA 15
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#define SUN8I_DAC_MXR_SRC 0x130
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#define SUN8I_DAC_MXR_SRC 0x130
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@ -338,10 +356,30 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
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SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0),
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SUN8I_DAC_MXR_SRC_DACR_MXR_SRC_ADCR, 1, 0),
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};
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};
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static const struct snd_kcontrol_new sun8i_input_mixer_controls[] = {
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SOC_DAPM_DOUBLE("AIF1 Slot 0 Digital ADC Capture Switch",
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SUN8I_AIF1_MXR_SRC,
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SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF1DA0L,
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SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF1DA0R, 1, 0),
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SOC_DAPM_DOUBLE("AIF2 Digital ADC Capture Switch", SUN8I_AIF1_MXR_SRC,
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SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACL,
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SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACR, 1, 0),
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SOC_DAPM_DOUBLE("AIF1 Data Digital ADC Capture Switch",
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SUN8I_AIF1_MXR_SRC,
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SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_ADCL,
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SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_ADCR, 1, 0),
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SOC_DAPM_DOUBLE("AIF2 Inv Digital ADC Capture Switch",
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SUN8I_AIF1_MXR_SRC,
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SUN8I_AIF1_MXR_SRC_AD0L_MXL_SRC_AIF2DACR,
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SUN8I_AIF1_MXR_SRC_AD0R_MXR_SRC_AIF2DACL, 1, 0),
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};
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static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
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static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
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/* Digital parts of the DACs */
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/* Digital parts of the DACs and ADC */
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SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA,
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SND_SOC_DAPM_SUPPLY("DAC", SUN8I_DAC_DIG_CTRL, SUN8I_DAC_DIG_CTRL_ENDA,
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0, NULL, 0),
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0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("ADC", SUN8I_ADC_DIG_CTRL, SUN8I_ADC_DIG_CTRL_ENDA,
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0, NULL, 0),
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/* Analog DAC AIF */
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/* Analog DAC AIF */
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SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0,
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SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left", "Playback", 0,
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@ -351,17 +389,31 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
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SUN8I_AIF1_DACDAT_CTRL,
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SUN8I_AIF1_DACDAT_CTRL,
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SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
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SUN8I_AIF1_DACDAT_CTRL_AIF1_DA0R_ENA, 0),
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/* DAC Mixers */
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/* Analog ADC AIF */
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SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Left ADC", "Capture", 0,
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SUN8I_AIF1_ADCDAT_CTRL,
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SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0L_ENA, 0),
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SND_SOC_DAPM_AIF_IN("AIF1 Slot 0 Right ADC", "Capture", 0,
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SUN8I_AIF1_ADCDAT_CTRL,
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SUN8I_AIF1_ADCDAT_CTRL_AIF1_DA0R_ENA, 0),
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/* DAC and ADC Mixers */
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SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
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SOC_MIXER_ARRAY("Left Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
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sun8i_dac_mixer_controls),
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sun8i_dac_mixer_controls),
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SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
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SOC_MIXER_ARRAY("Right Digital DAC Mixer", SND_SOC_NOPM, 0, 0,
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sun8i_dac_mixer_controls),
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sun8i_dac_mixer_controls),
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SOC_MIXER_ARRAY("Left Digital ADC Mixer", SND_SOC_NOPM, 0, 0,
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sun8i_input_mixer_controls),
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SOC_MIXER_ARRAY("Right Digital ADC Mixer", SND_SOC_NOPM, 0, 0,
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sun8i_input_mixer_controls),
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/* Clocks */
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/* Clocks */
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SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA,
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SND_SOC_DAPM_SUPPLY("MODCLK AFI1", SUN8I_MOD_CLK_ENA,
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SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
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SUN8I_MOD_CLK_ENA_AIF1, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA,
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SND_SOC_DAPM_SUPPLY("MODCLK DAC", SUN8I_MOD_CLK_ENA,
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SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
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SUN8I_MOD_CLK_ENA_DAC, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("MODCLK ADC", SUN8I_MOD_CLK_ENA,
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SUN8I_MOD_CLK_ENA_ADC, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL,
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SND_SOC_DAPM_SUPPLY("AIF1", SUN8I_SYSCLK_CTL,
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SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
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SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL,
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SND_SOC_DAPM_SUPPLY("SYSCLK", SUN8I_SYSCLK_CTL,
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@ -378,6 +430,12 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
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SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0),
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SUN8I_MOD_RST_CTL_AIF1, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL,
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SND_SOC_DAPM_SUPPLY("RST DAC", SUN8I_MOD_RST_CTL,
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SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),
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SUN8I_MOD_RST_CTL_DAC, 0, NULL, 0),
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SND_SOC_DAPM_SUPPLY("RST ADC", SUN8I_MOD_RST_CTL,
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SUN8I_MOD_RST_CTL_ADC, 0, NULL, 0),
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SND_SOC_DAPM_MIC("Headset Mic", NULL),
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SND_SOC_DAPM_MIC("Mic", NULL),
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};
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};
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static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
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static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
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@ -387,11 +445,16 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
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{ "RST AIF1", NULL, "AIF1 PLL" },
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{ "RST AIF1", NULL, "AIF1 PLL" },
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{ "MODCLK AFI1", NULL, "RST AIF1" },
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{ "MODCLK AFI1", NULL, "RST AIF1" },
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{ "DAC", NULL, "MODCLK AFI1" },
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{ "DAC", NULL, "MODCLK AFI1" },
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{ "ADC", NULL, "MODCLK AFI1" },
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{ "RST DAC", NULL, "SYSCLK" },
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{ "RST DAC", NULL, "SYSCLK" },
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{ "MODCLK DAC", NULL, "RST DAC" },
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{ "MODCLK DAC", NULL, "RST DAC" },
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{ "DAC", NULL, "MODCLK DAC" },
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{ "DAC", NULL, "MODCLK DAC" },
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{ "RST ADC", NULL, "SYSCLK" },
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{ "MODCLK ADC", NULL, "RST ADC" },
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{ "ADC", NULL, "MODCLK ADC" },
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/* DAC Routes */
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/* DAC Routes */
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{ "AIF1 Slot 0 Right", NULL, "DAC" },
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{ "AIF1 Slot 0 Right", NULL, "DAC" },
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{ "AIF1 Slot 0 Left", NULL, "DAC" },
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{ "AIF1 Slot 0 Left", NULL, "DAC" },
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@ -401,6 +464,12 @@ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
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"AIF1 Slot 0 Left"},
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"AIF1 Slot 0 Left"},
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{ "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
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{ "Right Digital DAC Mixer", "AIF1 Slot 0 Digital DAC Playback Switch",
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"AIF1 Slot 0 Right"},
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"AIF1 Slot 0 Right"},
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/* ADC routes */
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{ "Left Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch",
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"AIF1 Slot 0 Left ADC" },
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{ "Right Digital ADC Mixer", "AIF1 Data Digital ADC Capture Switch",
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"AIF1 Slot 0 Right ADC" },
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};
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};
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static const struct snd_soc_dai_ops sun8i_codec_dai_ops = {
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static const struct snd_soc_dai_ops sun8i_codec_dai_ops = {
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@ -418,6 +487,15 @@ static struct snd_soc_dai_driver sun8i_codec_dai = {
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.rates = SNDRV_PCM_RATE_8000_192000,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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},
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/* capture capabilities */
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.capture = {
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.stream_name = "Capture",
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.channels_min = 1,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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.sig_bits = 24,
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},
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/* pcm operations */
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/* pcm operations */
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.ops = &sun8i_codec_dai_ops,
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.ops = &sun8i_codec_dai_ops,
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};
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};
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