drm/amd/display: Use optc32 instead of optc30 in DC
Change DC to use optc32, which uses REG_UPDATE instead of REG_SET. REG_SET clears OTG_H_TIMING_DIV_MODE_MANUAL which must be set to 1 in some specific HDMI configurations. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Charlene Liu <charlene.liu@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -207,7 +207,7 @@ void optc3_set_odm_bypass(struct timing_generator *optc,
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);
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h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
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REG_SET(OTG_H_TIMING_CNTL, 0,
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REG_UPDATE(OTG_H_TIMING_CNTL,
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OTG_H_TIMING_DIV_MODE, h_div);
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REG_SET(OPTC_MEMORY_CONFIG, 0,
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@ -201,7 +201,7 @@ static void optc32_disable_phantom_otg(struct timing_generator *optc)
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REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
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}
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static void optc32_set_odm_bypass(struct timing_generator *optc,
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void optc32_set_odm_bypass(struct timing_generator *optc,
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const struct dc_crtc_timing *dc_crtc_timing)
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{
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struct optc *optc1 = DCN10TG_FROM_TG(optc);
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@ -181,5 +181,7 @@
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void dcn32_timing_generator_init(struct optc *optc1);
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void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode);
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void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combine_segments);
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void optc32_set_odm_bypass(struct timing_generator *optc,
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const struct dc_crtc_timing *dc_crtc_timing);
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#endif /* __DC_OPTC_DCN32_H__ */
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@ -249,7 +249,7 @@ static struct timing_generator_funcs dcn35_tg_funcs = {
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.set_dsc_config = optc3_set_dsc_config,
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.get_dsc_status = optc2_get_dsc_status,
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.set_dwb_source = NULL,
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.set_odm_bypass = optc3_set_odm_bypass,
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.set_odm_bypass = optc32_set_odm_bypass,
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.set_odm_combine = optc35_set_odm_combine,
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.get_optc_source = optc2_get_optc_source,
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.set_h_timing_div_manual_mode = optc32_set_h_timing_div_manual_mode,
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