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ARM: dts: Split omap3 pinmux core device
The omap3_pmx_core pinmux device in the device tree handles the system controller module (SCM) PADCONFS fonction. Its control registers are split in two distinct areas, with other SCM registers in-between. Those other registers can't thus be requested by other drivers as the memory region gets reserved by the pinmux driver. Split the omap3_pmx_core device tree node in two for the two memory regions. The second region address and size depends on the SoC model. The change in omap3.dtsi fixes an "external abort on non-linefetch" when doing cat /sys/kernel/debug/pinctrl/.../pins on a Nokia N900. Note that the core2 padconf region is different for 3430 vs 3630, and does not exist on 3517 as noted by Nishanth Menon <nm@ti.com>. Reported-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-By: Sebastian Reichel <sre@debian.org> Signed-off-by: Nishanth Menon <nm@ti.com> [tony@atomide.com: updated for 3430 vs 3630 core2 based on Nishant's patch] Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
parent
43a348ea53
commit
3d49538364
9 changed files with 127 additions and 66 deletions
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@ -99,7 +99,7 @@ gpio1_pins: pinmux_gpio1_pins {
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&omap3_pmx_core {
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pinctrl-names = "default";
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pinctrl-0 = <
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&hsusbb2_pins
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&hsusb2_pins
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>;
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uart3_pins: pinmux_uart3_pins {
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@ -109,20 +109,32 @@ uart3_pins: pinmux_uart3_pins {
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>;
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};
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hsusbb2_pins: pinmux_hsusbb2_pins {
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hsusb2_pins: pinmux_hsusb2_pins {
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pinctrl-single,pins = <
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0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
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0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
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0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
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0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
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0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
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0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
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0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
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0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
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0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
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0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
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0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
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0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
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OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
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OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
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OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
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OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
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OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
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OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
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>;
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};
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};
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&omap3_pmx_core2 {
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pinctrl-names = "default";
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pinctrl-0 = <
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&hsusb2_2_pins
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>;
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hsusb2_2_pins: pinmux_hsusb2_2_pins {
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pinctrl-single,pins = <
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OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
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OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
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OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
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OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
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OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
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OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
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>;
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};
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};
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@ -93,23 +93,17 @@ gpio1_pins: pinmux_gpio1_pins {
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&omap3_pmx_core {
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pinctrl-names = "default";
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pinctrl-0 = <
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&hsusbb2_pins
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&hsusb2_pins
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>;
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hsusbb2_pins: pinmux_hsusbb2_pins {
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hsusb2_pins: pinmux_hsusb2_pins {
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pinctrl-single,pins = <
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0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
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0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
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0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
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0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
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0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
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0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
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0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
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0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
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0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
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0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
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0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
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0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
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OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
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OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
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OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
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OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
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OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
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OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
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>;
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};
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@ -121,6 +115,24 @@ uart3_pins: pinmux_uart3_pins {
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};
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};
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&omap3_pmx_core2 {
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pinctrl-names = "default";
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pinctrl-0 = <
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&hsusb2_2_pins
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>;
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hsusb2_2_pins: pinmux_hsusb2_2_pins {
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pinctrl-single,pins = <
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OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
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OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
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OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
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OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
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OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
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OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
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>;
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};
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};
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&i2c1 {
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clock-frequency = <2600000>;
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@ -133,8 +133,6 @@ i2c3_pins: pinmux_i2c3_pins {
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0x194 (PIN_INPUT | MUX_MODE0) /* i2c3_sda.i2c3_sda */
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>;
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};
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leds_pins: pinmux_leds_pins { };
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};
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&i2c1 {
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@ -66,28 +66,10 @@ hsusb1_phy: hsusb1_phy {
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&omap3_pmx_core {
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pinctrl-names = "default";
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pinctrl-0 = <
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&hsusbb1_pins
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&tfp410_pins
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&dss_pins
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>;
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hsusbb1_pins: pinmux_hsusbb1_pins {
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pinctrl-single,pins = <
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0x5aa (PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
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0x5a8 (PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
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0x5bc (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
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0x5be (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
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0x5ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
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0x5ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
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0x5b0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
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0x5b2 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
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0x5b4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
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0x5b6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
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0x5b8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
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0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
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>;
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};
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tfp410_pins: tfp410_dvi_pins {
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pinctrl-single,pins = <
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0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */
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@ -128,12 +110,36 @@ dss_pins: pinmux_dss_dvi_pins {
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};
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};
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&leds_pins {
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pinctrl-single,pins = <
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0x5c4 (PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
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0x5c6 (PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
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0x5c8 (PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
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&omap3_pmx_core2 {
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pinctrl-names = "default";
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pinctrl-0 = <
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&hsusbb1_pins
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>;
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hsusbb1_pins: pinmux_hsusbb1_pins {
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pinctrl-single,pins = <
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OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
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OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
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OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
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OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
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OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
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OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
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OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
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OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
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OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
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OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
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OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
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OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
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>;
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};
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leds_pins: pinmux_leds_pins {
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pinctrl-single,pins = <
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OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
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OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
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OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
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>;
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};
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};
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&i2c3 {
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@ -46,10 +46,12 @@ user2 {
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};
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};
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&leds_pins {
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pinctrl-single,pins = <
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0x5b0 (PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
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>;
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&omap3_pmx_core2 {
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leds_pins: pinmux_leds_pins {
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pinctrl-single,pins = <
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OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
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>;
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};
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};
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&gpmc {
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@ -80,13 +80,8 @@ mmc2_pins: pinmux_mmc2_pins {
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mmc3_pins: pinmux_mmc3_pins {
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pinctrl-single,pins = <
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0x168 (PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */
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0x1a0 (PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
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0x5a8 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */
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0x5b4 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */
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0x5b6 (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
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0x5b8 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */
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0x5b2 (PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */
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OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE4) /* mcbsp1_clkx.gpio_162 WLAN IRQ */
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OMAP3_CORE1_IOPAD(0x21d0, PIN_INPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.sdmmc3_cmd */
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>;
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};
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};
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};
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&omap3_pmx_core2 {
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mmc3_2_pins: pinmux_mmc3_2_pins {
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pinctrl-single,pins = <
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OMAP3630_CORE2_IOPAD(0x25d8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_clk.sdmmc3_clk */
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OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d4.sdmmc3_dat0 */
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OMAP3630_CORE2_IOPAD(0x25e6, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d5.sdmmc3_dat1 */
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OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d6.sdmmc3_dat2 */
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OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLUP | MUX_MODE2) /* etk_d3.sdmmc3_dat3 */
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>;
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};
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};
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&omap3_pmx_wkup {
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wlan_host_wkup: pinmux_wlan_host_wkup_pins {
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pinctrl-single,pins = <
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@ -187,7 +194,7 @@ &mmc3 {
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bus-width = <4>;
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cap-power-off-card;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc3_pins>;
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pinctrl-0 = <&mmc3_pins &mmc3_2_pins>;
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};
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&uart1 {
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@ -117,7 +117,7 @@ sdma: dma-controller@48056000 {
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omap3_pmx_core: pinmux@48002030 {
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compatible = "ti,omap3-padconf", "pinctrl-single";
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reg = <0x48002030 0x05cc>;
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reg = <0x48002030 0x0238>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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@ -25,4 +25,17 @@ cpu@0 {
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clock-latency = <300000>; /* From legacy driver */
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};
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};
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ocp {
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omap3_pmx_core2: pinmux@480025d8 {
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compatible = "ti,omap3-padconf", "pinctrl-single";
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reg = <0x480025d8 0x24>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0xff1f>;
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};
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};
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};
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@ -38,5 +38,16 @@ uart4: serial@49042000 {
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ti,hwmods = "uart4";
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clock-frequency = <48000000>;
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};
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omap3_pmx_core2: pinmux@480025a0 {
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compatible = "ti,omap3-padconf", "pinctrl-single";
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reg = <0x480025a0 0x5c>;
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#address-cells = <1>;
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#size-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
|
||||
pinctrl-single,register-width = <16>;
|
||||
pinctrl-single,function-mask = <0xff1f>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
Loading…
Reference in a new issue