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ARM: gic-v3: Work around definition of gic_write_bpr1
A new accessor for gic_write_bpr1 is added to arch_gicv3.h in 4.9, whilst the CP15 accessors are redifined in a separate branch. This leads to a horrible clash, where the new accessor ends up with a crap "asm volatile" definition. Work around this by carrying our own definition of gic_write_bpr1, creating a small conflict which will be obvious to resolve. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -216,6 +216,15 @@ static inline void gic_write_sre(u32 val)
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isb();
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}
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static inline void gic_write_bpr1(u32 val)
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{
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#if defined(__write_sysreg) && defined(ICC_BPR1)
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write_sysreg(val, ICC_BPR1);
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#else
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asm volatile("mcr " __stringify(ICC_BPR1) : : "r" (val));
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#endif
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}
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/*
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* Even in 32bit systems that use LPAE, there is no guarantee that the I/O
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* interface provides true 64bit atomic accesses, so using strd/ldrd doesn't
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