net: phy: Add 10BASE-T1L support in phy-c45
This patch is needed because the BASE-T1 uses different registers for status, control and advertisement to those already employed in the existing phy-c45 functions. Where required, genphy_c45 functions will now check whether the device supports BASE-T1 and use the specific registers instead: 45.2.7.19 BASE-T1 AN control register, 45.2.7.20 BASE-T1 AN status, 45.2.7.21 BASE-T1 AN advertisement register, 45.2.7.22 BASE-T1 AN LP Base Page ability register, 45.2.1.185 BASE-T1 PMA/PMD control register. Tested-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Alexandru Tachici
David S. Miller
parent
1b020e448e
commit
3da8ffd854
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@ -8,6 +8,25 @@
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#include <linux/mii.h>
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#include <linux/phy.h>
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/**
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* genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
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* @phydev: target phy_device struct
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*/
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static bool genphy_c45_baset1_able(struct phy_device *phydev)
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{
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int val;
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if (phydev->pma_extable == -ENODATA) {
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE);
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if (val < 0)
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return false;
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phydev->pma_extable = val;
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}
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return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1);
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}
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/**
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* genphy_c45_pma_can_sleep - checks if the PMA have sleep support
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* @phydev: target phy_device struct
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@ -80,7 +99,10 @@ int genphy_c45_pma_setup_forced(struct phy_device *phydev)
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switch (phydev->speed) {
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case SPEED_10:
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ctrl2 |= MDIO_PMA_CTRL2_10BT;
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if (genphy_c45_baset1_able(phydev))
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ctrl2 |= MDIO_PMA_CTRL2_BASET1;
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else
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ctrl2 |= MDIO_PMA_CTRL2_10BT;
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break;
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case SPEED_100:
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ctrl1 |= MDIO_PMA_CTRL1_SPEED100;
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@ -118,10 +140,95 @@ int genphy_c45_pma_setup_forced(struct phy_device *phydev)
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if (ret < 0)
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return ret;
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if (genphy_c45_baset1_able(phydev)) {
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int ctl = 0;
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switch (phydev->master_slave_set) {
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case MASTER_SLAVE_CFG_MASTER_PREFERRED:
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case MASTER_SLAVE_CFG_MASTER_FORCE:
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ctl = MDIO_PMA_PMD_BT1_CTRL_CFG_MST;
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break;
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case MASTER_SLAVE_CFG_SLAVE_FORCE:
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case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
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case MASTER_SLAVE_CFG_UNKNOWN:
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case MASTER_SLAVE_CFG_UNSUPPORTED:
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break;
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default:
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phydev_warn(phydev, "Unsupported Master/Slave mode\n");
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return -EOPNOTSUPP;
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}
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ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
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MDIO_PMA_PMD_BT1_CTRL_CFG_MST, ctl);
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if (ret < 0)
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return ret;
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}
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return genphy_c45_an_disable_aneg(phydev);
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}
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EXPORT_SYMBOL_GPL(genphy_c45_pma_setup_forced);
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/* Sets master/slave preference and supported technologies.
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* The preference is set in the BIT(4) of BASE-T1 AN
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* advertisement register 7.515 and whether the status
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* is forced or not, it is set in the BIT(12) of BASE-T1
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* AN advertisement register 7.514.
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* Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation
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* advertisement register [31:16] if supported.
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*/
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static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev)
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{
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int changed = 0;
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u16 adv_l = 0;
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u16 adv_m = 0;
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int ret;
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switch (phydev->master_slave_set) {
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case MASTER_SLAVE_CFG_MASTER_FORCE:
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case MASTER_SLAVE_CFG_SLAVE_FORCE:
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adv_l |= MDIO_AN_T1_ADV_L_FORCE_MS;
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break;
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case MASTER_SLAVE_CFG_MASTER_PREFERRED:
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case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
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break;
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default:
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break;
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}
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switch (phydev->master_slave_set) {
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case MASTER_SLAVE_CFG_MASTER_FORCE:
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case MASTER_SLAVE_CFG_MASTER_PREFERRED:
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adv_m |= MDIO_AN_T1_ADV_M_MST;
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break;
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case MASTER_SLAVE_CFG_SLAVE_FORCE:
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case MASTER_SLAVE_CFG_SLAVE_PREFERRED:
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break;
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default:
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break;
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}
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adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising);
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ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L,
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(MDIO_AN_T1_ADV_L_FORCE_MS | MDIO_AN_T1_ADV_L_PAUSE_CAP
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| MDIO_AN_T1_ADV_L_PAUSE_ASYM), adv_l);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = 1;
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adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising);
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ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M,
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MDIO_AN_T1_ADV_M_MST | MDIO_AN_T1_ADV_M_B10L, adv_m);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = 1;
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return changed;
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}
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/**
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* genphy_c45_an_config_aneg - configure advertisement registers
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* @phydev: target phy_device struct
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@ -141,6 +248,9 @@ int genphy_c45_an_config_aneg(struct phy_device *phydev)
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changed = genphy_config_eee_advert(phydev);
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if (genphy_c45_baset1_able(phydev))
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return genphy_c45_baset1_an_config_aneg(phydev);
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adv = linkmode_adv_to_mii_adv_t(phydev->advertising);
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ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE,
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@ -178,8 +288,12 @@ EXPORT_SYMBOL_GPL(genphy_c45_an_config_aneg);
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*/
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int genphy_c45_an_disable_aneg(struct phy_device *phydev)
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{
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u16 reg = MDIO_CTRL1;
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return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
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if (genphy_c45_baset1_able(phydev))
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reg = MDIO_AN_T1_CTRL;
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return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
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MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
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}
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EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
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@ -194,7 +308,12 @@ EXPORT_SYMBOL_GPL(genphy_c45_an_disable_aneg);
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*/
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int genphy_c45_restart_aneg(struct phy_device *phydev)
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{
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return phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1,
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u16 reg = MDIO_CTRL1;
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if (genphy_c45_baset1_able(phydev))
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reg = MDIO_AN_T1_CTRL;
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return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg,
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MDIO_AN_CTRL1_ENABLE | MDIO_AN_CTRL1_RESTART);
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}
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EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
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@ -210,11 +329,15 @@ EXPORT_SYMBOL_GPL(genphy_c45_restart_aneg);
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*/
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int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart)
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{
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u16 reg = MDIO_CTRL1;
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int ret;
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if (genphy_c45_baset1_able(phydev))
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reg = MDIO_AN_T1_CTRL;
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if (!restart) {
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/* Configure and restart aneg if it wasn't set before */
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ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
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ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
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if (ret < 0)
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return ret;
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@ -242,7 +365,13 @@ EXPORT_SYMBOL_GPL(genphy_c45_check_and_restart_aneg);
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*/
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int genphy_c45_aneg_done(struct phy_device *phydev)
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{
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int val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
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int reg = MDIO_STAT1;
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int val;
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if (genphy_c45_baset1_able(phydev))
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reg = MDIO_AN_T1_STAT;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
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return val < 0 ? val : val & MDIO_AN_STAT1_COMPLETE ? 1 : 0;
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}
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@ -307,6 +436,49 @@ int genphy_c45_read_link(struct phy_device *phydev)
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}
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EXPORT_SYMBOL_GPL(genphy_c45_read_link);
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/* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check
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* if autoneg is complete. If so read the BASE-T1 Autonegotiation
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* Advertisement registers filling in the link partner advertisement,
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* pause and asym_pause members in phydev.
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*/
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static int genphy_c45_baset1_read_lpa(struct phy_device *phydev)
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{
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int val;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
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if (val < 0)
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return val;
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if (!(val & MDIO_AN_STAT1_COMPLETE)) {
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linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising);
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mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0);
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mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0);
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phydev->pause = 0;
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phydev->asym_pause = 0;
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return 0;
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}
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linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1);
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L);
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if (val < 0)
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return val;
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mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val);
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phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0;
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phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M);
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if (val < 0)
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return val;
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mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val);
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return 0;
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}
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/**
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* genphy_c45_read_lpa - read the link partner advertisement and pause
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* @phydev: target phy_device struct
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@ -321,6 +493,9 @@ int genphy_c45_read_lpa(struct phy_device *phydev)
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{
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int val;
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if (genphy_c45_baset1_able(phydev))
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return genphy_c45_baset1_read_lpa(phydev);
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1);
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if (val < 0)
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return val;
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@ -399,6 +574,17 @@ int genphy_c45_read_pma(struct phy_device *phydev)
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phydev->duplex = DUPLEX_FULL;
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if (genphy_c45_baset1_able(phydev)) {
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL);
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if (val < 0)
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return val;
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if (MDIO_PMA_PMD_BT1_CTRL_CFG_MST)
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phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
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else
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phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(genphy_c45_read_pma);
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@ -530,12 +716,67 @@ int genphy_c45_pma_read_abilities(struct phy_device *phydev)
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phydev->supported,
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val & MDIO_PMA_NG_EXTABLE_5GBT);
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}
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if (val & MDIO_PMA_EXTABLE_BT1) {
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val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1);
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if (val < 0)
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return val;
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linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
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phydev->supported,
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val & MDIO_PMA_PMD_BT1_B10L_ABLE);
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT);
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if (val < 0)
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return val;
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linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
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phydev->supported,
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val & MDIO_AN_STAT1_ABLE);
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}
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(genphy_c45_pma_read_abilities);
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/* Read master/slave preference from registers.
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* The preference is read from the BIT(4) of BASE-T1 AN
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* advertisement register 7.515 and whether the preference
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* is forced or not, it is read from BASE-T1 AN advertisement
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* register 7.514.
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*/
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static int genphy_c45_baset1_read_status(struct phy_device *phydev)
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{
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int ret;
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int cfg;
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phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
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phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
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ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L);
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if (ret < 0)
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return ret;
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cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M);
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if (cfg < 0)
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return cfg;
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if (ret & MDIO_AN_T1_ADV_L_FORCE_MS) {
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if (cfg & MDIO_AN_T1_ADV_M_MST)
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phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
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else
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phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
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} else {
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if (cfg & MDIO_AN_T1_ADV_M_MST)
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phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED;
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else
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phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED;
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}
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return 0;
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}
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/**
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* genphy_c45_read_status - read PHY status
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* @phydev: target phy_device struct
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@ -560,6 +801,12 @@ int genphy_c45_read_status(struct phy_device *phydev)
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if (ret)
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return ret;
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if (genphy_c45_baset1_able(phydev)) {
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ret = genphy_c45_baset1_read_status(phydev);
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if (ret < 0)
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return ret;
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}
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phy_resolve_aneg_linkmode(phydev);
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} else {
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ret = genphy_c45_read_pma(phydev);
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@ -600,6 +600,7 @@ struct phy_device *phy_device_create(struct mii_bus *bus, int addr, u32 phy_id,
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dev->autoneg = AUTONEG_ENABLE;
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dev->pma_extable = -ENODATA;
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dev->is_c45 = is_c45;
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dev->phy_id = phy_id;
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if (c45_ids)
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@ -340,6 +340,76 @@ static inline void mii_10gbt_stat_mod_linkmode_lpa_t(unsigned long *advertising,
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advertising, lpa & MDIO_AN_10GBT_STAT_LP10G);
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}
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/**
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* mii_t1_adv_l_mod_linkmode_t
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* @advertising: target the linkmode advertisement settings
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* @lpa: value of the BASE-T1 Autonegotiation Advertisement [15:0] Register
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*
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* A small helper function that translates BASE-T1 Autonegotiation
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* Advertisement [15:0] Register bits to linkmode advertisement settings.
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* Other bits in advertising aren't changed.
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*/
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static inline void mii_t1_adv_l_mod_linkmode_t(unsigned long *advertising, u32 lpa)
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{
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linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertising,
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lpa & MDIO_AN_T1_ADV_L_PAUSE_CAP);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertising,
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lpa & MDIO_AN_T1_ADV_L_PAUSE_ASYM);
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}
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/**
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* mii_t1_adv_m_mod_linkmode_t
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* @advertising: target the linkmode advertisement settings
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* @lpa: value of the BASE-T1 Autonegotiation Advertisement [31:16] Register
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*
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* A small helper function that translates BASE-T1 Autonegotiation
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* Advertisement [31:16] Register bits to linkmode advertisement settings.
|
||||
* Other bits in advertising aren't changed.
|
||||
*/
|
||||
static inline void mii_t1_adv_m_mod_linkmode_t(unsigned long *advertising, u32 lpa)
|
||||
{
|
||||
linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT,
|
||||
advertising, lpa & MDIO_AN_T1_ADV_M_B10L);
|
||||
}
|
||||
|
||||
/**
|
||||
* linkmode_adv_to_mii_t1_adv_l_t
|
||||
* @advertising: the linkmode advertisement settings
|
||||
*
|
||||
* A small helper function that translates linkmode advertisement
|
||||
* settings to phy autonegotiation advertisements for the
|
||||
* BASE-T1 Autonegotiation Advertisement [15:0] Register.
|
||||
*/
|
||||
static inline u32 linkmode_adv_to_mii_t1_adv_l_t(unsigned long *advertising)
|
||||
{
|
||||
u32 result = 0;
|
||||
|
||||
if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT, advertising))
|
||||
result |= MDIO_AN_T1_ADV_L_PAUSE_CAP;
|
||||
if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, advertising))
|
||||
result |= MDIO_AN_T1_ADV_L_PAUSE_ASYM;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* linkmode_adv_to_mii_t1_adv_m_t
|
||||
* @advertising: the linkmode advertisement settings
|
||||
*
|
||||
* A small helper function that translates linkmode advertisement
|
||||
* settings to phy autonegotiation advertisements for the
|
||||
* BASE-T1 Autonegotiation Advertisement [31:16] Register.
|
||||
*/
|
||||
static inline u32 linkmode_adv_to_mii_t1_adv_m_t(unsigned long *advertising)
|
||||
{
|
||||
u32 result = 0;
|
||||
|
||||
if (linkmode_test_bit(ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, advertising))
|
||||
result |= MDIO_AN_T1_ADV_M_B10L;
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
int __mdiobus_read(struct mii_bus *bus, int addr, u32 regnum);
|
||||
int __mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val);
|
||||
int __mdiobus_modify_changed(struct mii_bus *bus, int addr, u32 regnum,
|
||||
|
|
|
|||
|
|
@ -570,6 +570,7 @@ struct macsec_ops;
|
|||
* @autoneg_complete: Flag auto negotiation of the link has completed
|
||||
* @mdix: Current crossover
|
||||
* @mdix_ctrl: User setting of crossover
|
||||
* @pma_extable: Cached value of PMA/PMD Extended Abilities Register
|
||||
* @interrupts: Flag interrupts have been enabled
|
||||
* @interface: enum phy_interface_t value
|
||||
* @skb: Netlink message for cable diagnostics
|
||||
|
|
@ -698,6 +699,8 @@ struct phy_device {
|
|||
u8 mdix;
|
||||
u8 mdix_ctrl;
|
||||
|
||||
int pma_extable;
|
||||
|
||||
void (*phy_link_change)(struct phy_device *phydev, bool up);
|
||||
void (*adjust_link)(struct net_device *dev);
|
||||
|
||||
|
|
|
|||
|
|
@ -70,6 +70,7 @@
|
|||
#define MDIO_B10L_PMA_CTRL 2294 /* 10BASE-T1L PMA control */
|
||||
#define MDIO_PMA_10T1L_STAT 2295 /* 10BASE-T1L PMA status */
|
||||
#define MDIO_PCS_10T1L_CTRL 2278 /* 10BASE-T1L PCS control */
|
||||
#define MDIO_PMA_PMD_BT1 18 /* BASE-T1 PMA/PMD extended ability */
|
||||
#define MDIO_AN_T1_CTRL 512 /* BASE-T1 AN control */
|
||||
#define MDIO_AN_T1_STAT 513 /* BASE-T1 AN status */
|
||||
#define MDIO_AN_T1_ADV_L 514 /* BASE-T1 AN advertisement register [15:0] */
|
||||
|
|
@ -78,6 +79,7 @@
|
|||
#define MDIO_AN_T1_LP_L 517 /* BASE-T1 AN LP Base Page ability register [15:0] */
|
||||
#define MDIO_AN_T1_LP_M 518 /* BASE-T1 AN LP Base Page ability register [31:16] */
|
||||
#define MDIO_AN_T1_LP_H 519 /* BASE-T1 AN LP Base Page ability register [47:32] */
|
||||
#define MDIO_PMA_PMD_BT1_CTRL 2100 /* BASE-T1 PMA/PMD control register */
|
||||
|
||||
/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
|
||||
#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
|
||||
|
|
@ -170,6 +172,7 @@
|
|||
#define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */
|
||||
#define MDIO_PMA_CTRL2_2_5GBT 0x0030 /* 2.5GBaseT type */
|
||||
#define MDIO_PMA_CTRL2_5GBT 0x0031 /* 5GBaseT type */
|
||||
#define MDIO_PMA_CTRL2_BASET1 0x003D /* BASE-T1 type */
|
||||
#define MDIO_PCS_CTRL2_TYPE 0x0003 /* PCS type selection */
|
||||
#define MDIO_PCS_CTRL2_10GBR 0x0000 /* 10GBASE-R type */
|
||||
#define MDIO_PCS_CTRL2_10GBX 0x0001 /* 10GBASE-X type */
|
||||
|
|
@ -223,6 +226,7 @@
|
|||
#define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */
|
||||
#define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */
|
||||
#define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */
|
||||
#define MDIO_PMA_EXTABLE_BT1 0x0800 /* BASE-T1 ability */
|
||||
#define MDIO_PMA_EXTABLE_NBT 0x4000 /* 2.5/5GBASE-T ability */
|
||||
|
||||
/* PHY XGXS lane state register. */
|
||||
|
|
@ -301,6 +305,9 @@
|
|||
#define MDIO_PCS_10T1L_CTRL_LB 0x4000 /* Enable PCS level loopback mode */
|
||||
#define MDIO_PCS_10T1L_CTRL_RESET 0x8000 /* PCS reset */
|
||||
|
||||
/* BASE-T1 PMA/PMD extended ability register. */
|
||||
#define MDIO_PMA_PMD_BT1_B10L_ABLE 0x0004 /* 10BASE-T1L Ability */
|
||||
|
||||
/* BASE-T1 auto-negotiation advertisement register [15:0] */
|
||||
#define MDIO_AN_T1_ADV_L_PAUSE_CAP ADVERTISE_PAUSE_CAP
|
||||
#define MDIO_AN_T1_ADV_L_PAUSE_ASYM ADVERTISE_PAUSE_ASYM
|
||||
|
|
@ -333,6 +340,9 @@
|
|||
#define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000 /* 10BASE-T1L High Level LP Transmit Request */
|
||||
#define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000 /* 10BASE-T1L High Level LP Transmit Ability */
|
||||
|
||||
/* BASE-T1 PMA/PMD control register */
|
||||
#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000 /* MASTER-SLAVE config value */
|
||||
|
||||
/* EEE Supported/Advertisement/LP Advertisement registers.
|
||||
*
|
||||
* EEE capability Register (3.20), Advertisement (7.60) and
|
||||
|
|
|
|||
Loading…
Reference in New Issue