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Blackfin: Split PLL code from mach-specific cdef headers
Split the PLL control code from the Blackfin machine-specific cdef headers so that the irqflags functions can be renamed without incurring a header loop. Signed-off-by: David Howells <dhowells@redhat.com>
This commit is contained in:
parent
cb655d0f3d
commit
3dcc1e7f9f
15 changed files with 436 additions and 344 deletions
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@ -1058,54 +1058,4 @@
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/* These need to be last due to the cdef/linux inter-dependencies */
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#include <asm/irq.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_PLL_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR0, iwr0);
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bfin_write32(SIC_IWR1, iwr1);
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local_irq_restore_hw(flags);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_VR_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR0, iwr0);
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bfin_write32(SIC_IWR1, iwr1);
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local_irq_restore_hw(flags);
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}
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#endif /* _CDEF_BF52X_H */
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63
arch/blackfin/mach-bf518/include/mach/pll.h
Normal file
63
arch/blackfin/mach-bf518/include/mach/pll.h
Normal file
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@ -0,0 +1,63 @@
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/*
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* Copyright 2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later
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*/
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#ifndef _MACH_PLL_H
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#define _MACH_PLL_H
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#include <asm/blackfin.h>
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#include <asm/irqflags.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_PLL_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR0, iwr0);
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bfin_write32(SIC_IWR1, iwr1);
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local_irq_restore_hw(flags);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_VR_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR0, iwr0);
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bfin_write32(SIC_IWR1, iwr1);
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local_irq_restore_hw(flags);
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}
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#endif /* _MACH_PLL_H */
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@ -1110,54 +1110,4 @@
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/* These need to be last due to the cdef/linux inter-dependencies */
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#include <asm/irq.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_PLL_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR0, iwr0);
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bfin_write32(SIC_IWR1, iwr1);
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local_irq_restore_hw(flags);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_VR_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR0, iwr0);
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bfin_write32(SIC_IWR1, iwr1);
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local_irq_restore_hw(flags);
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}
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#endif /* _CDEF_BF52X_H */
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63
arch/blackfin/mach-bf527/include/mach/pll.h
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63
arch/blackfin/mach-bf527/include/mach/pll.h
Normal file
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/*
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* Copyright 2007-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later
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*/
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#ifndef _MACH_PLL_H
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#define _MACH_PLL_H
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#include <asm/blackfin.h>
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#include <asm/irqflags.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_PLL_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR0, iwr0);
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bfin_write32(SIC_IWR1, iwr1);
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local_irq_restore_hw(flags);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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if (val == bfin_read_VR_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr0 = bfin_read32(SIC_IWR0);
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iwr1 = bfin_read32(SIC_IWR1);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR0, IWR_ENABLE(0));
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bfin_write32(SIC_IWR1, 0);
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR0, iwr0);
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bfin_write32(SIC_IWR1, iwr1);
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local_irq_restore_hw(flags);
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}
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#endif /* _MACH_PLL_H */
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@ -697,48 +697,4 @@ BFIN_READ_FIO_FLAG(T)
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#define bfin_read_FIO_FLAG_D() bfin_read16(FIO_FLAG_D)
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#endif
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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if (val == bfin_read_PLL_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SIC_IWR);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR, IWR_ENABLE(0));
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR, iwr);
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local_irq_restore_hw(flags);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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if (val == bfin_read_VR_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SIC_IWR);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR, IWR_ENABLE(0));
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR, iwr);
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local_irq_restore_hw(flags);
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}
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#endif /* _CDEF_BF532_H */
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57
arch/blackfin/mach-bf533/include/mach/pll.h
Normal file
57
arch/blackfin/mach-bf533/include/mach/pll.h
Normal file
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/*
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* Copyright 2005-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later
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*/
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#ifndef _MACH_PLL_H
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#define _MACH_PLL_H
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#include <asm/blackfin.h>
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#include <asm/irqflags.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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if (val == bfin_read_PLL_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SIC_IWR);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR, IWR_ENABLE(0));
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR, iwr);
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local_irq_restore_hw(flags);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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if (val == bfin_read_VR_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SIC_IWR);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR, IWR_ENABLE(0));
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR, iwr);
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local_irq_restore_hw(flags);
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}
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#endif /* _MACH_PLL_H */
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@ -1750,48 +1750,4 @@
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/* These need to be last due to the cdef/linux inter-dependencies */
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#include <asm/irq.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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if (val == bfin_read_PLL_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SIC_IWR);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR, IWR_ENABLE(0));
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR, iwr);
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local_irq_restore_hw(flags);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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if (val == bfin_read_VR_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SIC_IWR);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR, IWR_ENABLE(0));
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR, iwr);
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local_irq_restore_hw(flags);
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}
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#endif /* _CDEF_BF534_H */
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57
arch/blackfin/mach-bf537/include/mach/pll.h
Normal file
57
arch/blackfin/mach-bf537/include/mach/pll.h
Normal file
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/*
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* Copyright 2005-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later
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*/
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#ifndef _MACH_PLL_H
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#define _MACH_PLL_H
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#include <asm/blackfin.h>
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#include <asm/irqflags.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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if (val == bfin_read_PLL_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SIC_IWR);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR, IWR_ENABLE(0));
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bfin_write16(PLL_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR, iwr);
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local_irq_restore_hw(flags);
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}
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/* Writing to VR_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_VR_CTL(unsigned int val)
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{
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unsigned long flags, iwr;
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if (val == bfin_read_VR_CTL())
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return;
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local_irq_save_hw(flags);
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/* Enable the PLL Wakeup bit in SIC IWR */
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iwr = bfin_read32(SIC_IWR);
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/* Only allow PPL Wakeup) */
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bfin_write32(SIC_IWR, IWR_ENABLE(0));
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bfin_write16(VR_CTL, val);
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SSYNC();
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asm("IDLE;");
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bfin_write32(SIC_IWR, iwr);
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local_irq_restore_hw(flags);
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}
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#endif /* _MACH_PLL_H */
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@ -2027,54 +2027,4 @@
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/* These need to be last due to the cdef/linux inter-dependencies */
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#include <asm/irq.h>
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/* Writing to PLL_CTL initiates a PLL relock sequence. */
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static __inline__ void bfin_write_PLL_CTL(unsigned int val)
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{
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unsigned long flags, iwr0, iwr1;
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|
||||
if (val == bfin_read_PLL_CTL())
|
||||
return;
|
||||
|
||||
local_irq_save_hw(flags);
|
||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
||||
iwr0 = bfin_read32(SIC_IWR0);
|
||||
iwr1 = bfin_read32(SIC_IWR1);
|
||||
/* Only allow PPL Wakeup) */
|
||||
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
|
||||
bfin_write32(SIC_IWR1, 0);
|
||||
|
||||
bfin_write16(PLL_CTL, val);
|
||||
SSYNC();
|
||||
asm("IDLE;");
|
||||
|
||||
bfin_write32(SIC_IWR0, iwr0);
|
||||
bfin_write32(SIC_IWR1, iwr1);
|
||||
local_irq_restore_hw(flags);
|
||||
}
|
||||
|
||||
/* Writing to VR_CTL initiates a PLL relock sequence. */
|
||||
static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
{
|
||||
unsigned long flags, iwr0, iwr1;
|
||||
|
||||
if (val == bfin_read_VR_CTL())
|
||||
return;
|
||||
|
||||
local_irq_save_hw(flags);
|
||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
||||
iwr0 = bfin_read32(SIC_IWR0);
|
||||
iwr1 = bfin_read32(SIC_IWR1);
|
||||
/* Only allow PPL Wakeup) */
|
||||
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
|
||||
bfin_write32(SIC_IWR1, 0);
|
||||
|
||||
bfin_write16(VR_CTL, val);
|
||||
SSYNC();
|
||||
asm("IDLE;");
|
||||
|
||||
bfin_write32(SIC_IWR0, iwr0);
|
||||
bfin_write32(SIC_IWR1, iwr1);
|
||||
local_irq_restore_hw(flags);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
63
arch/blackfin/mach-bf538/include/mach/pll.h
Normal file
63
arch/blackfin/mach-bf538/include/mach/pll.h
Normal file
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Copyright 2008-2009 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_PLL_H
|
||||
#define _MACH_PLL_H
|
||||
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/irqflags.h>
|
||||
|
||||
/* Writing to PLL_CTL initiates a PLL relock sequence. */
|
||||
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
|
||||
{
|
||||
unsigned long flags, iwr0, iwr1;
|
||||
|
||||
if (val == bfin_read_PLL_CTL())
|
||||
return;
|
||||
|
||||
local_irq_save_hw(flags);
|
||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
||||
iwr0 = bfin_read32(SIC_IWR0);
|
||||
iwr1 = bfin_read32(SIC_IWR1);
|
||||
/* Only allow PPL Wakeup) */
|
||||
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
|
||||
bfin_write32(SIC_IWR1, 0);
|
||||
|
||||
bfin_write16(PLL_CTL, val);
|
||||
SSYNC();
|
||||
asm("IDLE;");
|
||||
|
||||
bfin_write32(SIC_IWR0, iwr0);
|
||||
bfin_write32(SIC_IWR1, iwr1);
|
||||
local_irq_restore_hw(flags);
|
||||
}
|
||||
|
||||
/* Writing to VR_CTL initiates a PLL relock sequence. */
|
||||
static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
{
|
||||
unsigned long flags, iwr0, iwr1;
|
||||
|
||||
if (val == bfin_read_VR_CTL())
|
||||
return;
|
||||
|
||||
local_irq_save_hw(flags);
|
||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
||||
iwr0 = bfin_read32(SIC_IWR0);
|
||||
iwr1 = bfin_read32(SIC_IWR1);
|
||||
/* Only allow PPL Wakeup) */
|
||||
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
|
||||
bfin_write32(SIC_IWR1, 0);
|
||||
|
||||
bfin_write16(VR_CTL, val);
|
||||
SSYNC();
|
||||
asm("IDLE;");
|
||||
|
||||
bfin_write32(SIC_IWR0, iwr0);
|
||||
bfin_write32(SIC_IWR1, iwr1);
|
||||
local_irq_restore_hw(flags);
|
||||
}
|
||||
|
||||
#endif /* _MACH_PLL_H */
|
|
@ -2648,61 +2648,5 @@
|
|||
/* These need to be last due to the cdef/linux inter-dependencies */
|
||||
#include <asm/irq.h>
|
||||
|
||||
/* Writing to PLL_CTL initiates a PLL relock sequence. */
|
||||
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
|
||||
{
|
||||
unsigned long flags, iwr0, iwr1, iwr2;
|
||||
|
||||
if (val == bfin_read_PLL_CTL())
|
||||
return;
|
||||
|
||||
local_irq_save_hw(flags);
|
||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
||||
iwr0 = bfin_read32(SIC_IWR0);
|
||||
iwr1 = bfin_read32(SIC_IWR1);
|
||||
iwr2 = bfin_read32(SIC_IWR2);
|
||||
/* Only allow PPL Wakeup) */
|
||||
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
|
||||
bfin_write32(SIC_IWR1, 0);
|
||||
bfin_write32(SIC_IWR2, 0);
|
||||
|
||||
bfin_write16(PLL_CTL, val);
|
||||
SSYNC();
|
||||
asm("IDLE;");
|
||||
|
||||
bfin_write32(SIC_IWR0, iwr0);
|
||||
bfin_write32(SIC_IWR1, iwr1);
|
||||
bfin_write32(SIC_IWR2, iwr2);
|
||||
local_irq_restore_hw(flags);
|
||||
}
|
||||
|
||||
/* Writing to VR_CTL initiates a PLL relock sequence. */
|
||||
static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
{
|
||||
unsigned long flags, iwr0, iwr1, iwr2;
|
||||
|
||||
if (val == bfin_read_VR_CTL())
|
||||
return;
|
||||
|
||||
local_irq_save_hw(flags);
|
||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
||||
iwr0 = bfin_read32(SIC_IWR0);
|
||||
iwr1 = bfin_read32(SIC_IWR1);
|
||||
iwr2 = bfin_read32(SIC_IWR2);
|
||||
/* Only allow PPL Wakeup) */
|
||||
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
|
||||
bfin_write32(SIC_IWR1, 0);
|
||||
bfin_write32(SIC_IWR2, 0);
|
||||
|
||||
bfin_write16(VR_CTL, val);
|
||||
SSYNC();
|
||||
asm("IDLE;");
|
||||
|
||||
bfin_write32(SIC_IWR0, iwr0);
|
||||
bfin_write32(SIC_IWR1, iwr1);
|
||||
bfin_write32(SIC_IWR2, iwr2);
|
||||
local_irq_restore_hw(flags);
|
||||
}
|
||||
|
||||
#endif /* _CDEF_BF54X_H */
|
||||
|
||||
|
|
69
arch/blackfin/mach-bf548/include/mach/pll.h
Normal file
69
arch/blackfin/mach-bf548/include/mach/pll.h
Normal file
|
@ -0,0 +1,69 @@
|
|||
/*
|
||||
* Copyright 2007-2008 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_PLL_H
|
||||
#define _MACH_PLL_H
|
||||
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/irqflags.h>
|
||||
|
||||
/* Writing to PLL_CTL initiates a PLL relock sequence. */
|
||||
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
|
||||
{
|
||||
unsigned long flags, iwr0, iwr1, iwr2;
|
||||
|
||||
if (val == bfin_read_PLL_CTL())
|
||||
return;
|
||||
|
||||
local_irq_save_hw(flags);
|
||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
||||
iwr0 = bfin_read32(SIC_IWR0);
|
||||
iwr1 = bfin_read32(SIC_IWR1);
|
||||
iwr2 = bfin_read32(SIC_IWR2);
|
||||
/* Only allow PPL Wakeup) */
|
||||
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
|
||||
bfin_write32(SIC_IWR1, 0);
|
||||
bfin_write32(SIC_IWR2, 0);
|
||||
|
||||
bfin_write16(PLL_CTL, val);
|
||||
SSYNC();
|
||||
asm("IDLE;");
|
||||
|
||||
bfin_write32(SIC_IWR0, iwr0);
|
||||
bfin_write32(SIC_IWR1, iwr1);
|
||||
bfin_write32(SIC_IWR2, iwr2);
|
||||
local_irq_restore_hw(flags);
|
||||
}
|
||||
|
||||
/* Writing to VR_CTL initiates a PLL relock sequence. */
|
||||
static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
{
|
||||
unsigned long flags, iwr0, iwr1, iwr2;
|
||||
|
||||
if (val == bfin_read_VR_CTL())
|
||||
return;
|
||||
|
||||
local_irq_save_hw(flags);
|
||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
||||
iwr0 = bfin_read32(SIC_IWR0);
|
||||
iwr1 = bfin_read32(SIC_IWR1);
|
||||
iwr2 = bfin_read32(SIC_IWR2);
|
||||
/* Only allow PPL Wakeup) */
|
||||
bfin_write32(SIC_IWR0, IWR_ENABLE(0));
|
||||
bfin_write32(SIC_IWR1, 0);
|
||||
bfin_write32(SIC_IWR2, 0);
|
||||
|
||||
bfin_write16(VR_CTL, val);
|
||||
SSYNC();
|
||||
asm("IDLE;");
|
||||
|
||||
bfin_write32(SIC_IWR0, iwr0);
|
||||
bfin_write32(SIC_IWR1, iwr1);
|
||||
bfin_write32(SIC_IWR2, iwr2);
|
||||
local_irq_restore_hw(flags);
|
||||
}
|
||||
|
||||
#endif /* _MACH_PLL_H */
|
|
@ -1534,54 +1534,4 @@
|
|||
/* These need to be last due to the cdef/linux inter-dependencies */
|
||||
#include <asm/irq.h>
|
||||
|
||||
/* Writing to PLL_CTL initiates a PLL relock sequence. */
|
||||
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
|
||||
{
|
||||
unsigned long flags, iwr0, iwr1;
|
||||
|
||||
if (val == bfin_read_PLL_CTL())
|
||||
return;
|
||||
|
||||
local_irq_save_hw(flags);
|
||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
||||
iwr0 = bfin_read32(SICA_IWR0);
|
||||
iwr1 = bfin_read32(SICA_IWR1);
|
||||
/* Only allow PPL Wakeup) */
|
||||
bfin_write32(SICA_IWR0, IWR_ENABLE(0));
|
||||
bfin_write32(SICA_IWR1, 0);
|
||||
|
||||
bfin_write16(PLL_CTL, val);
|
||||
SSYNC();
|
||||
asm("IDLE;");
|
||||
|
||||
bfin_write32(SICA_IWR0, iwr0);
|
||||
bfin_write32(SICA_IWR1, iwr1);
|
||||
local_irq_restore_hw(flags);
|
||||
}
|
||||
|
||||
/* Writing to VR_CTL initiates a PLL relock sequence. */
|
||||
static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
{
|
||||
unsigned long flags, iwr0, iwr1;
|
||||
|
||||
if (val == bfin_read_VR_CTL())
|
||||
return;
|
||||
|
||||
local_irq_save_hw(flags);
|
||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
||||
iwr0 = bfin_read32(SICA_IWR0);
|
||||
iwr1 = bfin_read32(SICA_IWR1);
|
||||
/* Only allow PPL Wakeup) */
|
||||
bfin_write32(SICA_IWR0, IWR_ENABLE(0));
|
||||
bfin_write32(SICA_IWR1, 0);
|
||||
|
||||
bfin_write16(VR_CTL, val);
|
||||
SSYNC();
|
||||
asm("IDLE;");
|
||||
|
||||
bfin_write32(SICA_IWR0, iwr0);
|
||||
bfin_write32(SICA_IWR1, iwr1);
|
||||
local_irq_restore_hw(flags);
|
||||
}
|
||||
|
||||
#endif /* _CDEF_BF561_H */
|
||||
|
|
63
arch/blackfin/mach-bf561/include/mach/pll.h
Normal file
63
arch/blackfin/mach-bf561/include/mach/pll.h
Normal file
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Copyright 2005-2009 Analog Devices Inc.
|
||||
*
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
#ifndef _MACH_PLL_H
|
||||
#define _MACH_PLL_H
|
||||
|
||||
#include <asm/blackfin.h>
|
||||
#include <asm/irqflags.h>
|
||||
|
||||
/* Writing to PLL_CTL initiates a PLL relock sequence. */
|
||||
static __inline__ void bfin_write_PLL_CTL(unsigned int val)
|
||||
{
|
||||
unsigned long flags, iwr0, iwr1;
|
||||
|
||||
if (val == bfin_read_PLL_CTL())
|
||||
return;
|
||||
|
||||
local_irq_save_hw(flags);
|
||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
||||
iwr0 = bfin_read32(SICA_IWR0);
|
||||
iwr1 = bfin_read32(SICA_IWR1);
|
||||
/* Only allow PPL Wakeup) */
|
||||
bfin_write32(SICA_IWR0, IWR_ENABLE(0));
|
||||
bfin_write32(SICA_IWR1, 0);
|
||||
|
||||
bfin_write16(PLL_CTL, val);
|
||||
SSYNC();
|
||||
asm("IDLE;");
|
||||
|
||||
bfin_write32(SICA_IWR0, iwr0);
|
||||
bfin_write32(SICA_IWR1, iwr1);
|
||||
local_irq_restore_hw(flags);
|
||||
}
|
||||
|
||||
/* Writing to VR_CTL initiates a PLL relock sequence. */
|
||||
static __inline__ void bfin_write_VR_CTL(unsigned int val)
|
||||
{
|
||||
unsigned long flags, iwr0, iwr1;
|
||||
|
||||
if (val == bfin_read_VR_CTL())
|
||||
return;
|
||||
|
||||
local_irq_save_hw(flags);
|
||||
/* Enable the PLL Wakeup bit in SIC IWR */
|
||||
iwr0 = bfin_read32(SICA_IWR0);
|
||||
iwr1 = bfin_read32(SICA_IWR1);
|
||||
/* Only allow PPL Wakeup) */
|
||||
bfin_write32(SICA_IWR0, IWR_ENABLE(0));
|
||||
bfin_write32(SICA_IWR1, 0);
|
||||
|
||||
bfin_write16(VR_CTL, val);
|
||||
SSYNC();
|
||||
asm("IDLE;");
|
||||
|
||||
bfin_write32(SICA_IWR0, iwr0);
|
||||
bfin_write32(SICA_IWR1, iwr1);
|
||||
local_irq_restore_hw(flags);
|
||||
}
|
||||
|
||||
#endif /* _MACH_PLL_H */
|
|
@ -38,6 +38,7 @@
|
|||
#include <asm/blackfin.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/portmux.h>
|
||||
#include <mach/pll.h>
|
||||
|
||||
#include "bfin_mac.h"
|
||||
|
||||
|
|
Loading…
Reference in a new issue