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clk: tegra: change post IDDQ release delay to 5us
Increase delay after PLL IDDQ release to 5us per PLL specifications. based on work by Alex Frid <afrid@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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@ -363,7 +363,7 @@ static void _clk_pll_enable(struct clk_hw *hw)
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val = pll_readl(pll->params->iddq_reg, pll);
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val &= ~BIT(pll->params->iddq_bit_idx);
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pll_writel(val, pll->params->iddq_reg, pll);
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udelay(2);
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udelay(5);
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}
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if (pll->params->reset_reg) {
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