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clk: rockchip: fix the incorrect pclk_edp div width for RK3399
The range of the pclk_edp_div_con is [13:8] and 6 bits, not 5. Reported-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Tested-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -1132,7 +1132,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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RK3399_CLKGATE_CON(11), 8, GFLAGS),
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COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
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RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
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RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
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RK3399_CLKGATE_CON(11), 11, GFLAGS),
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GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
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RK3399_CLKGATE_CON(32), 12, GFLAGS),
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