ARM: entry: data abort: arrange for CPU abort helpers to take pc/psr in r4/r5
Re-jig the CPU abort helpers to take the PC/PSR in r4/r5 rather than r2/r3. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
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8dfe7ac96f
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3e287bec6f
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@ -56,14 +56,12 @@
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.endm
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.endm
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.macro dabt_helper
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.macro dabt_helper
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mov r2, r4
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mov r3, r5
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@
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@
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@ Call the processor-specific abort handler:
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@ Call the processor-specific abort handler:
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@
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@
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@ r2 - aborted context pc
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@ r4 - aborted context pc
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@ r3 - aborted context cpsr
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@ r5 - aborted context psr
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@
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@
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@ The abort handler must return the aborted address in r0, and
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@ The abort handler must return the aborted address in r0, and
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@ the fault status register in r1. r9 must be preserved.
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@ the fault status register in r1. r9 must be preserved.
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@ -3,8 +3,8 @@
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/*
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/*
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* Function: v4_early_abort
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* Function: v4_early_abort
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*
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*
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* Params : r2 = address of aborted instruction
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* Params : r4 = aborted context pc
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* : r3 = saved SPSR
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* : r5 = aborted context psr
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*
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*
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* Returns : r0 = address of abort
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* Returns : r0 = address of abort
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* : r1 = FSR, bit 11 = write
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* : r1 = FSR, bit 11 = write
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@ -21,10 +21,8 @@
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ENTRY(v4_early_abort)
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ENTRY(v4_early_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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ldr r3, [r2] @ read aborted ARM instruction
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ldr r3, [r4] @ read aborted ARM instruction
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bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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tst r3, #1 << 20 @ L = 1 -> write?
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tst r3, #1 << 20 @ L = 1 -> write?
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orreq r1, r1, #1 << 11 @ yes.
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orreq r1, r1, #1 << 11 @ yes.
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mov pc, lr
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mov pc, lr
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@ -4,8 +4,8 @@
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/*
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/*
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* Function: v4t_early_abort
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* Function: v4t_early_abort
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*
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*
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* Params : r2 = address of aborted instruction
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* Params : r4 = aborted context pc
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* : r3 = saved SPSR
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* : r5 = aborted context psr
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*
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*
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* Returns : r0 = address of abort
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* Returns : r0 = address of abort
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* : r1 = FSR, bit 11 = write
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* : r1 = FSR, bit 11 = write
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@ -22,8 +22,8 @@
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ENTRY(v4t_early_abort)
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ENTRY(v4t_early_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
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do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
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ldreq r3, [r2] @ read aborted ARM instruction
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ldreq r3, [r4] @ read aborted ARM instruction
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bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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tst r3, #1 << 20 @ check write
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tst r3, #1 << 20 @ check write
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orreq r1, r1, #1 << 11
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orreq r1, r1, #1 << 11
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@ -4,8 +4,8 @@
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/*
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/*
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* Function: v5t_early_abort
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* Function: v5t_early_abort
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*
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*
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* Params : r2 = address of aborted instruction
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* Params : r4 = aborted context pc
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* : r3 = saved SPSR
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* : r5 = aborted context psr
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*
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*
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* Returns : r0 = address of abort
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* Returns : r0 = address of abort
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* : r1 = FSR, bit 11 = write
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* : r1 = FSR, bit 11 = write
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@ -22,8 +22,8 @@
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ENTRY(v5t_early_abort)
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ENTRY(v5t_early_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
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do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
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ldreq r3, [r2] @ read aborted ARM instruction
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ldreq r3, [r4] @ read aborted ARM instruction
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bic r1, r1, #1 << 11 @ clear bits 11 of FSR
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bic r1, r1, #1 << 11 @ clear bits 11 of FSR
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do_ldrd_abort tmp=r2, insn=r3
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do_ldrd_abort tmp=r2, insn=r3
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tst r3, #1 << 20 @ check write
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tst r3, #1 << 20 @ check write
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@ -4,8 +4,8 @@
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/*
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/*
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* Function: v5tj_early_abort
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* Function: v5tj_early_abort
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*
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*
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* Params : r2 = address of aborted instruction
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* Params : r4 = aborted context pc
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* : r3 = saved SPSR
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* : r5 = aborted context psr
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*
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*
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* Returns : r0 = address of abort
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* Returns : r0 = address of abort
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* : r1 = FSR, bit 11 = write
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* : r1 = FSR, bit 11 = write
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@ -23,13 +23,11 @@ ENTRY(v5tj_early_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
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tst r3, #PSR_J_BIT @ Java?
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tst r5, #PSR_J_BIT @ Java?
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movne pc, lr
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movne pc, lr
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do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
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do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
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ldreq r3, [r2] @ read aborted ARM instruction
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ldreq r3, [r4] @ read aborted ARM instruction
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do_ldrd_abort tmp=r2, insn=r3
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do_ldrd_abort tmp=r2, insn=r3
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tst r3, #1 << 20 @ L = 0 -> write
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tst r3, #1 << 20 @ L = 0 -> write
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orreq r1, r1, #1 << 11 @ yes.
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orreq r1, r1, #1 << 11 @ yes.
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mov pc, lr
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mov pc, lr
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@ -4,8 +4,8 @@
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/*
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/*
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* Function: v6_early_abort
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* Function: v6_early_abort
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*
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*
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* Params : r2 = address of aborted instruction
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* Params : r4 = aborted context pc
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* : r3 = saved SPSR
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* : r5 = aborted context psr
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*
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*
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* Returns : r0 = address of abort
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* Returns : r0 = address of abort
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* : r1 = FSR, bit 11 = write
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* : r1 = FSR, bit 11 = write
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@ -33,10 +33,10 @@ ENTRY(v6_early_abort)
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* The test below covers all the write situations, including Java bytecodes
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* The test below covers all the write situations, including Java bytecodes
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*/
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*/
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bic r1, r1, #1 << 11 @ clear bit 11 of FSR
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bic r1, r1, #1 << 11 @ clear bit 11 of FSR
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tst r3, #PSR_J_BIT @ Java?
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tst r5, #PSR_J_BIT @ Java?
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movne pc, lr
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movne pc, lr
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do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
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do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
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ldreq r3, [r2] @ read aborted ARM instruction
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ldreq r3, [r4] @ read aborted ARM instruction
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#ifdef CONFIG_CPU_ENDIAN_BE8
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#ifdef CONFIG_CPU_ENDIAN_BE8
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reveq r3, r3
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reveq r3, r3
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#endif
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#endif
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@ -44,5 +44,3 @@ ENTRY(v6_early_abort)
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tst r3, #1 << 20 @ L = 0 -> write
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tst r3, #1 << 20 @ L = 0 -> write
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orreq r1, r1, #1 << 11 @ yes.
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orreq r1, r1, #1 << 11 @ yes.
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mov pc, lr
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mov pc, lr
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@ -3,8 +3,8 @@
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/*
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/*
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* Function: v7_early_abort
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* Function: v7_early_abort
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*
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*
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* Params : r2 = address of aborted instruction
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* Params : r4 = aborted context pc
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* : r3 = saved SPSR
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* : r5 = aborted context psr
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*
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*
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* Returns : r0 = address of abort
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* Returns : r0 = address of abort
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* : r1 = FSR, bit 11 = write
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* : r1 = FSR, bit 11 = write
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@ -3,8 +3,8 @@
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/*
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/*
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* Function: v4t_late_abort
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* Function: v4t_late_abort
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*
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*
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* Params : r2 = address of aborted instruction
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* Params : r4 = aborted context pc
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* : r3 = saved SPSR
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* : r5 = aborted context psr
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*
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*
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* Returns : r0 = address of abort
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* Returns : r0 = address of abort
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* : r1 = FSR, bit 11 = write
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* : r1 = FSR, bit 11 = write
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@ -18,7 +18,7 @@
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* picture. Unfortunately, this does happen. We live with it.
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* picture. Unfortunately, this does happen. We live with it.
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*/
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*/
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ENTRY(v4t_late_abort)
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ENTRY(v4t_late_abort)
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tst r3, #PSR_T_BIT @ check for thumb mode
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tst r5, #PSR_T_BIT @ check for thumb mode
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#ifdef CONFIG_CPU_CP15_MMU
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#ifdef CONFIG_CPU_CP15_MMU
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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@ -28,7 +28,7 @@ ENTRY(v4t_late_abort)
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mov r1, #0
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mov r1, #0
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#endif
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#endif
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bne .data_thumb_abort
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bne .data_thumb_abort
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ldr r8, [r2] @ read arm instruction
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ldr r8, [r4] @ read arm instruction
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tst r8, #1 << 20 @ L = 1 -> write?
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tst r8, #1 << 20 @ L = 1 -> write?
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orreq r1, r1, #1 << 11 @ yes.
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orreq r1, r1, #1 << 11 @ yes.
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and r7, r8, #15 << 24
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and r7, r8, #15 << 24
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@ -52,7 +52,7 @@ ENTRY(v4t_late_abort)
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/* e */ b .data_unknown
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/* e */ b .data_unknown
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/* f */
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/* f */
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.data_unknown: @ Part of jumptable
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.data_unknown: @ Part of jumptable
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mov r0, r2
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mov r0, r4
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mov r1, r8
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mov r1, r8
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mov r2, sp
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mov r2, sp
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bl baddataabort
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bl baddataabort
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@ -159,7 +159,7 @@ ENTRY(v4t_late_abort)
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b .data_unknown @ F: MUL?
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b .data_unknown @ F: MUL?
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.data_thumb_abort:
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.data_thumb_abort:
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ldrh r8, [r2] @ read instruction
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ldrh r8, [r4] @ read instruction
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tst r8, #1 << 11 @ L = 1 -> write?
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tst r8, #1 << 11 @ L = 1 -> write?
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orreq r1, r1, #1 << 8 @ yes
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orreq r1, r1, #1 << 8 @ yes
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and r7, r8, #15 << 12
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and r7, r8, #15 << 12
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@ -3,8 +3,8 @@
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/*
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/*
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* Function: nommu_early_abort
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* Function: nommu_early_abort
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*
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*
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* Params : r2 = address of aborted instruction
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* Params : r4 = aborted context pc
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* : r3 = saved SPSR
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* : r5 = aborted context psr
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*
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*
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* Returns : r0 = 0 (abort address)
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* Returns : r0 = 0 (abort address)
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* : r1 = 0 (FSR)
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* : r1 = 0 (FSR)
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@ -29,8 +29,8 @@ ENTRY(cpu_arm7_dcache_clean_area)
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/*
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/*
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* Function: arm6_7_data_abort ()
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* Function: arm6_7_data_abort ()
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*
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*
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* Params : r2 = address of aborted instruction
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* Params : r4 = aborted context pc
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* : sp = pointer to registers
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* : r5 = aborted context psr
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*
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*
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* Purpose : obtain information about current aborted instruction
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* Purpose : obtain information about current aborted instruction
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*
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*
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ENTRY(cpu_arm7_data_abort)
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ENTRY(cpu_arm7_data_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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ldr r8, [r2] @ read arm instruction
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ldr r8, [r4] @ read arm instruction
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tst r8, #1 << 20 @ L = 0 -> write?
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tst r8, #1 << 20 @ L = 0 -> write?
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orreq r1, r1, #1 << 11 @ yes.
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orreq r1, r1, #1 << 11 @ yes.
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and r7, r8, #15 << 24
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and r7, r8, #15 << 24
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@ -65,7 +65,7 @@ ENTRY(cpu_arm7_data_abort)
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/* e */ b .data_unknown
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/* e */ b .data_unknown
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/* f */
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/* f */
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.data_unknown: @ Part of jumptable
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.data_unknown: @ Part of jumptable
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mov r0, r2
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mov r0, r4
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mov r1, r8
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mov r1, r8
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mov r2, sp
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mov r2, sp
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bl baddataabort
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bl baddataabort
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@ -74,7 +74,7 @@ ENTRY(cpu_arm7_data_abort)
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ENTRY(cpu_arm6_data_abort)
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ENTRY(cpu_arm6_data_abort)
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r1, c5, c0, 0 @ get FSR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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mrc p15, 0, r0, c6, c0, 0 @ get FAR
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ldr r8, [r2] @ read arm instruction
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ldr r8, [r4] @ read arm instruction
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tst r8, #1 << 20 @ L = 0 -> write?
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tst r8, #1 << 20 @ L = 0 -> write?
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orreq r1, r1, #1 << 11 @ yes.
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orreq r1, r1, #1 << 11 @ yes.
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and r7, r8, #14 << 24
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and r7, r8, #14 << 24
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