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drm/amd/powerplay: support xgmi pstate setting on powerplay routine V2
Add xgmi pstate setting on powerplay routine. V2: split the change of is_support_sw_smu_xgmi into a separate patch Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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086e1c5616
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3e454860f2
6 changed files with 44 additions and 4 deletions
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@ -285,6 +285,11 @@ int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
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if (is_support_sw_smu_xgmi(adev))
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ret = smu_set_xgmi_pstate(&adev->smu, pstate);
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else if (adev->powerplay.pp_funcs &&
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adev->powerplay.pp_funcs->set_xgmi_pstate)
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ret = adev->powerplay.pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
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pstate);
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if (ret)
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dev_err(adev->dev,
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"XGMI: Set pstate failure on device %llx, hive %llx, ret %d",
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@ -220,6 +220,9 @@ enum pp_df_cstate {
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((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
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(support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
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#define XGMI_MODE_PSTATE_D3 0
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#define XGMI_MODE_PSTATE_D0 1
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struct seq_file;
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enum amd_pp_clock_type;
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struct amd_pp_simple_clock_info;
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@ -318,6 +321,7 @@ struct amd_pm_funcs {
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int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
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int (*asic_reset_mode_2)(void *handle);
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int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
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int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
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};
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#endif
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@ -1566,6 +1566,23 @@ static int pp_set_df_cstate(void *handle, enum pp_df_cstate state)
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return 0;
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}
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static int pp_set_xgmi_pstate(void *handle, uint32_t pstate)
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{
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struct pp_hwmgr *hwmgr = handle;
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if (!hwmgr)
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return -EINVAL;
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if (!hwmgr->pm_en || !hwmgr->hwmgr_func->set_xgmi_pstate)
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return 0;
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mutex_lock(&hwmgr->smu_lock);
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hwmgr->hwmgr_func->set_xgmi_pstate(hwmgr, pstate);
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mutex_unlock(&hwmgr->smu_lock);
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return 0;
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}
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static const struct amd_pm_funcs pp_dpm_funcs = {
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.load_firmware = pp_dpm_load_fw,
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.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
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@ -1625,4 +1642,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
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.asic_reset_mode_2 = pp_asic_reset_mode_2,
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.smu_i2c_bus_access = pp_smu_i2c_bus_access,
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.set_df_cstate = pp_set_df_cstate,
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.set_xgmi_pstate = pp_set_xgmi_pstate,
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};
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@ -4176,6 +4176,20 @@ static int vega20_set_df_cstate(struct pp_hwmgr *hwmgr,
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return ret;
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}
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static int vega20_set_xgmi_pstate(struct pp_hwmgr *hwmgr,
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uint32_t pstate)
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{
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int ret;
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ret = smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetXgmiMode,
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pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3);
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if (ret)
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pr_err("SetXgmiPstate failed!\n");
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return ret;
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}
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static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
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/* init/fini related */
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.backend_init = vega20_hwmgr_backend_init,
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@ -4245,6 +4259,7 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
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.set_mp1_state = vega20_set_mp1_state,
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.smu_i2c_bus_access = vega20_smu_i2c_bus_access,
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.set_df_cstate = vega20_set_df_cstate,
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.set_xgmi_pstate = vega20_set_xgmi_pstate,
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};
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int vega20_hwmgr_init(struct pp_hwmgr *hwmgr)
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@ -356,6 +356,7 @@ struct pp_hwmgr_func {
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int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
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int (*smu_i2c_bus_access)(struct pp_hwmgr *hwmgr, bool aquire);
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int (*set_df_cstate)(struct pp_hwmgr *hwmgr, enum pp_df_cstate state);
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int (*set_xgmi_pstate)(struct pp_hwmgr *hwmgr, uint32_t pstate);
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};
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struct pp_table_func {
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@ -1463,16 +1463,13 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
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return ret;
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}
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#define XGMI_STATE_D0 1
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#define XGMI_STATE_D3 0
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int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
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uint32_t pstate)
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{
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int ret = 0;
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ret = smu_send_smc_msg_with_param(smu,
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SMU_MSG_SetXgmiMode,
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pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
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pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3);
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return ret;
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}
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