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habanalabs/gaudi2: modify decoder to use virtual MSI-X doorbell
Modify the decoder wrapper blocks to generate interrupts using the virtual MSI-X doorbell. As a decoder wrapper block cannot write directly to HBW upon completion, it writes instead to SOB which is monitored by a master monitor. When resolved, this monitor will be the one to actually write to the virtual MSI-X doorbell. Signed-off-by: Tomer Tayar <ttayar@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
This commit is contained in:
Tomer Tayar
Oded Gabbay
parent
bfbf5a0a71
commit
3f043b3192
4 changed files with 161 additions and 11 deletions
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@ -4252,6 +4252,109 @@ static void gaudi2_init_edma(struct hl_device *hdev)
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}
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}
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/*
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* gaudi2_arm_monitors_for_virt_msix_db() - Arm monitors for writing to the virtual MSI-X doorbell.
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* @hdev: pointer to habanalabs device structure.
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* @sob_id: sync object ID.
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* @first_mon_id: ID of first monitor out of 3 consecutive monitors.
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* @interrupt_id: interrupt ID.
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*
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* Some initiators cannot have HBW address in their completion address registers, and thus cannot
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* write directly to the HBW host memory of the virtual MSI-X doorbell.
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* Instead, they are configured to LBW write to a sync object, and a monitor will do the HBW write.
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*
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* The mechanism in the sync manager block is composed of a master monitor with 3 messages.
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* In addition to the HBW write, the other 2 messages are for preparing the monitor to next
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* completion, by decrementing the sync object value and re-arming the monitor.
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*/
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static void gaudi2_arm_monitors_for_virt_msix_db(struct hl_device *hdev, u32 sob_id,
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u32 first_mon_id, u32 interrupt_id)
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{
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u32 sob_offset, first_mon_offset, mon_offset, payload, sob_group, mode, arm, config;
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struct gaudi2_device *gaudi2 = hdev->asic_specific;
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u64 addr;
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u8 mask;
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/* Reset the SOB value */
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sob_offset = sob_id * sizeof(u32);
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset, 0);
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/* Configure 3 monitors:
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* 1. Write interrupt ID to the virtual MSI-X doorbell (master monitor)
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* 2. Decrement SOB value by 1.
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* 3. Re-arm the master monitor.
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*/
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first_mon_offset = first_mon_id * sizeof(u32);
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/* 2nd monitor: Decrement SOB value by 1 */
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mon_offset = first_mon_offset + sizeof(u32);
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addr = CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_offset;
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_offset, lower_32_bits(addr));
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + mon_offset, upper_32_bits(addr));
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payload = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 0x7FFF) | /* "-1" */
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FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_MASK, 1) |
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FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1);
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_offset, payload);
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/* 3rd monitor: Re-arm the master monitor */
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mon_offset = first_mon_offset + 2 * sizeof(u32);
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addr = CFG_BASE + mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 + first_mon_offset;
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_offset, lower_32_bits(addr));
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + mon_offset, upper_32_bits(addr));
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sob_group = sob_id / 8;
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mask = ~BIT(sob_id & 0x7);
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mode = 0; /* comparison mode is "greater than or equal to" */
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arm = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SID_MASK, sob_group) |
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FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_MASK_MASK, mask) |
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FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOP_MASK, mode) |
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FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_ARM_SOD_MASK, 1);
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payload = arm;
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_offset, payload);
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/* 1st monitor (master): Write interrupt ID to the virtual MSI-X doorbell */
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mon_offset = first_mon_offset;
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config = FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_MON_CONFIG_WR_NUM_MASK, 2); /* "2": 3 writes */
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_CONFIG_0 + mon_offset, config);
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addr = gaudi2->virt_msix_db_dma_addr;
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 + mon_offset, lower_32_bits(addr));
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 + mon_offset, upper_32_bits(addr));
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payload = interrupt_id;
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_PAY_DATA_0 + mon_offset, payload);
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WREG32(mmDCORE0_SYNC_MNGR_OBJS_MON_ARM_0 + mon_offset, arm);
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}
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static void gaudi2_prepare_sm_for_virt_msix_db(struct hl_device *hdev)
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{
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u32 decoder_id, sob_id, first_mon_id, interrupt_id;
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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/* Decoder normal/abnormal interrupts */
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for (decoder_id = 0 ; decoder_id < NUMBER_OF_DEC ; ++decoder_id) {
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if (!(prop->decoder_enabled_mask & BIT(decoder_id)))
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continue;
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sob_id = GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + decoder_id;
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first_mon_id = GAUDI2_RESERVED_MON_DEC_NRM_FIRST + 3 * decoder_id;
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interrupt_id = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM + 2 * decoder_id;
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gaudi2_arm_monitors_for_virt_msix_db(hdev, sob_id, first_mon_id, interrupt_id);
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sob_id = GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + decoder_id;
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first_mon_id = GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST + 3 * decoder_id;
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interrupt_id += 1;
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gaudi2_arm_monitors_for_virt_msix_db(hdev, sob_id, first_mon_id, interrupt_id);
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}
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}
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static void gaudi2_init_sm(struct hl_device *hdev)
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{
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struct gaudi2_device *gaudi2 = hdev->asic_specific;
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@ -4304,6 +4407,9 @@ static void gaudi2_init_sm(struct hl_device *hdev)
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/* Configure kernel ASID and MMU BP*/
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WREG32(mmDCORE0_SYNC_MNGR_GLBL_ASID_SEC, 0x10000);
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WREG32(mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV, 0);
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/* Initialize sync objects and monitors which are used for the virtual MSI-X doorbell */
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gaudi2_prepare_sm_for_virt_msix_db(hdev);
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}
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static void gaudi2_init_mme_acc(struct hl_device *hdev, u32 reg_base)
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@ -4452,16 +4558,41 @@ static void gaudi2_init_rotator(struct hl_device *hdev)
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}
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}
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static void gaudi2_init_vdec_brdg_ctrl(struct hl_device *hdev, u64 base_addr, u32 msix_id)
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static void gaudi2_init_vdec_brdg_ctrl(struct hl_device *hdev, u64 base_addr, u32 decoder_id)
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{
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WREG32(base_addr + BRDG_CTRL_NRM_MSIX_LBW_WDATA, msix_id);
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WREG32(base_addr + BRDG_CTRL_ABNRM_MSIX_LBW_WDATA, msix_id + 1);
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u32 sob_id;
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/* TODO:
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* Remove when virtual MSI-X doorbell is supported in simulator (SW-93022) and in F/W
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* (SW-93024).
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*/
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if (!hdev->pdev || hdev->asic_prop.fw_security_enabled) {
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u32 interrupt_id = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM + 2 * decoder_id;
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WREG32(base_addr + BRDG_CTRL_NRM_MSIX_LBW_AWADDR, mmPCIE_DBI_MSIX_DOORBELL_OFF);
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WREG32(base_addr + BRDG_CTRL_NRM_MSIX_LBW_WDATA, interrupt_id);
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WREG32(base_addr + BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR, mmPCIE_DBI_MSIX_DOORBELL_OFF);
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WREG32(base_addr + BRDG_CTRL_ABNRM_MSIX_LBW_WDATA, interrupt_id + 1);
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return;
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}
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/* VCMD normal interrupt */
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sob_id = GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + decoder_id;
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WREG32(base_addr + BRDG_CTRL_NRM_MSIX_LBW_AWADDR,
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mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_id * sizeof(u32));
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WREG32(base_addr + BRDG_CTRL_NRM_MSIX_LBW_WDATA, GAUDI2_SOB_INCREMENT_BY_ONE);
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/* VCMD abnormal interrupt */
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sob_id = GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + decoder_id;
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WREG32(base_addr + BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR,
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mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_0 + sob_id * sizeof(u32));
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WREG32(base_addr + BRDG_CTRL_ABNRM_MSIX_LBW_WDATA, GAUDI2_SOB_INCREMENT_BY_ONE);
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}
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static void gaudi2_init_dec(struct hl_device *hdev)
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{
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struct gaudi2_device *gaudi2 = hdev->asic_specific;
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u32 dcore_id, dec_id, dec_bit, msix_id;
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u32 dcore_id, dec_id, dec_bit;
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u64 base_addr;
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if (!hdev->asic_prop.decoder_enabled_mask)
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@ -4482,10 +4613,7 @@ static void gaudi2_init_dec(struct hl_device *hdev)
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dcore_id * DCORE_OFFSET +
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dec_id * DCORE_VDEC_OFFSET;
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msix_id = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM +
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(dcore_id * NUM_OF_DEC_PER_DCORE + dec_id) * 2;
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gaudi2_init_vdec_brdg_ctrl(hdev, base_addr, msix_id);
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gaudi2_init_vdec_brdg_ctrl(hdev, base_addr, dec_bit);
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gaudi2->dec_hw_cap_initialized |= BIT_ULL(HW_CAP_DEC_SHIFT + dec_bit);
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}
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@ -4498,9 +4626,7 @@ static void gaudi2_init_dec(struct hl_device *hdev)
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base_addr = mmPCIE_DEC0_CMD_BASE + BRDG_CTRL_BLOCK_OFFSET +
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dec_id * DCORE_VDEC_OFFSET;
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msix_id = GAUDI2_IRQ_NUM_SHARED_DEC0_NRM + (dec_id * 2);
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gaudi2_init_vdec_brdg_ctrl(hdev, base_addr, msix_id);
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gaudi2_init_vdec_brdg_ctrl(hdev, base_addr, dec_bit);
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gaudi2->dec_hw_cap_initialized |= BIT_ULL(HW_CAP_DEC_SHIFT + dec_bit);
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}
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@ -243,11 +243,20 @@
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#define GAUDI2_ARC_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 28)) >> 28)
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#define GAUDI2_SOB_INCREMENT_BY_ONE (FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_MASK, 1) | \
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FIELD_PREP(DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_MASK, 1))
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enum gaudi2_reserved_sob_id {
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GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST,
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GAUDI2_RESERVED_SOB_CS_COMPLETION_LAST =
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GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
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GAUDI2_RESERVED_SOB_KDMA_COMPLETION,
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GAUDI2_RESERVED_SOB_DEC_NRM_FIRST,
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GAUDI2_RESERVED_SOB_DEC_NRM_LAST =
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GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + NUMBER_OF_DEC - 1,
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GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST,
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GAUDI2_RESERVED_SOB_DEC_ABNRM_LAST =
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GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + NUMBER_OF_DEC - 1,
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GAUDI2_RESERVED_SOB_NUMBER
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};
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@ -256,6 +265,12 @@ enum gaudi2_reserved_mon_id {
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GAUDI2_RESERVED_MON_CS_COMPLETION_LAST =
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GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
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GAUDI2_RESERVED_MON_KDMA_COMPLETION,
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GAUDI2_RESERVED_MON_DEC_NRM_FIRST,
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GAUDI2_RESERVED_MON_DEC_NRM_LAST =
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GAUDI2_RESERVED_MON_DEC_NRM_FIRST + 3 * NUMBER_OF_DEC - 1,
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GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST,
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GAUDI2_RESERVED_MON_DEC_ABNRM_LAST =
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GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST + 3 * NUMBER_OF_DEC - 1,
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GAUDI2_RESERVED_MON_NUMBER
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};
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@ -135,4 +135,7 @@
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#define PCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_SHIFT 0
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#define PCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_MASK 0x1
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#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_SHIFT 15
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#define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_MASK 0x8000
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#endif /* GAUDI2_MASKS_H_ */
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@ -415,9 +415,15 @@
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#define SFT_DCORE_OFFSET (mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE)
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#define SFT_IF_OFFSET (mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE)
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#define BRDG_CTRL_NRM_MSIX_LBW_AWADDR \
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(mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
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#define BRDG_CTRL_NRM_MSIX_LBW_WDATA \
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(mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
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#define BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR \
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(mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
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#define BRDG_CTRL_ABNRM_MSIX_LBW_WDATA \
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(mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA - mmDCORE0_VDEC0_BRDG_CTRL_BASE)
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