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irqchip/gic-v3: Switch to PMR masking before calling IRQ handler
Mask the IRQ priority through PMR and re-enable IRQs at CPU level, allowing only higher priority interrupts to be received during interrupt handling. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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3 changed files with 39 additions and 0 deletions
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@ -363,5 +363,22 @@ static inline void gits_write_vpendbaser(u64 val, void * __iomem addr)
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#define gits_read_vpendbaser(c) __gic_readq_nonatomic(c)
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static inline bool gic_prio_masking_enabled(void)
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{
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return false;
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}
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static inline void gic_pmr_mask_irqs(void)
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{
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/* Should not get called. */
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WARN_ON_ONCE(true);
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}
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static inline void gic_arch_enable_irqs(void)
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{
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/* Should not get called. */
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WARN_ON_ONCE(true);
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* !__ASM_ARCH_GICV3_H */
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@ -155,5 +155,22 @@ static inline u32 gic_read_rpr(void)
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#define gits_write_vpendbaser(v, c) writeq_relaxed(v, c)
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#define gits_read_vpendbaser(c) readq_relaxed(c)
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static inline bool gic_prio_masking_enabled(void)
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{
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return system_uses_irq_prio_masking();
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}
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static inline void gic_pmr_mask_irqs(void)
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{
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/* Should not get called yet. */
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WARN_ON_ONCE(true);
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}
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static inline void gic_arch_enable_irqs(void)
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{
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/* Should not get called yet. */
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WARN_ON_ONCE(true);
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}
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARCH_GICV3_H */
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@ -356,6 +356,11 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
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irqnr = gic_read_iar();
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if (gic_prio_masking_enabled()) {
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gic_pmr_mask_irqs();
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gic_arch_enable_irqs();
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}
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if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) {
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int err;
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