mirrors
/
linux-stable
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
1
0
Fork 0
Code Issues Releases Wiki Activity

staging/rdma/hfi1: Use BIT_ULL macro 

Use BIT_ULL macro to fix checkpatch check:
CHECK: Prefer using the BIT_ULL macro

Reviewed-by: Dennis Dalessandro <dennis.dalessandro@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: Jubin John <jubin.john@intel.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
Jubin John 2016-02-14 20:20:42 -08:00 committed by Doug Ledford
parent 58721b8f8c
commit 3f34d9588f
3 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/staging/rdma/hfi1/chip.h
View File

@ -93,15 +93,15 @@
#define TXE_PIO_SEND (TXE + TXE_PIO_SEND_OFFSET)
/* PBC flags */
#define PBC_INTR (1ull << 31)
#define PBC_INTR BIT_ULL(31)
#define PBC_DC_INFO_SHIFT (30)
#define PBC_DC_INFO (1ull << PBC_DC_INFO_SHIFT)
#define PBC_TEST_EBP (1ull << 29)
#define PBC_PACKET_BYPASS (1ull << 28)
#define PBC_CREDIT_RETURN (1ull << 25)
#define PBC_INSERT_BYPASS_ICRC (1ull << 24)
#define PBC_TEST_BAD_ICRC (1ull << 23)
#define PBC_FECN (1ull << 22)
#define PBC_DC_INFO BIT_ULL(PBC_DC_INFO_SHIFT)
#define PBC_TEST_EBP BIT_ULL(29)
#define PBC_PACKET_BYPASS BIT_ULL(28)
#define PBC_CREDIT_RETURN BIT_ULL(25)
#define PBC_INSERT_BYPASS_ICRC BIT_ULL(24)
#define PBC_TEST_BAD_ICRC BIT_ULL(23)
#define PBC_FECN BIT_ULL(22)
/* PbcInsertHcrc field settings */
#define PBC_IHCRC_LKDETH 0x0 /* insert @ local KDETH offset */

2
drivers/staging/rdma/hfi1/eprom.c
View File

@ -102,7 +102,7 @@
#define COUNT_DELAY_SEC(n) ((n) * (1000000 / WAIT_SLEEP_US))
/* GPIO pins */
#define EPROM_WP_N (1ull << 14) /* EPROM write line */
#define EPROM_WP_N BIT_ULL(14) /* EPROM write line */
/*
* Use the EP mutex to guard against other callers from within the driver.

8
drivers/staging/rdma/hfi1/sdma.h
View File

@ -107,8 +107,8 @@
/*
* Bits defined in the send DMA descriptor.
*/
#define SDMA_DESC0_FIRST_DESC_FLAG (1ULL << 63)
#define SDMA_DESC0_LAST_DESC_FLAG (1ULL << 62)
#define SDMA_DESC0_FIRST_DESC_FLAG BIT_ULL(63)
#define SDMA_DESC0_LAST_DESC_FLAG BIT_ULL(62)
#define SDMA_DESC0_BYTE_COUNT_SHIFT 48
#define SDMA_DESC0_BYTE_COUNT_WIDTH 14
#define SDMA_DESC0_BYTE_COUNT_MASK \
@ -152,8 +152,8 @@
((1ULL << SDMA_DESC1_GENERATION_WIDTH) - 1)
#define SDMA_DESC1_GENERATION_SMASK \
(SDMA_DESC1_GENERATION_MASK << SDMA_DESC1_GENERATION_SHIFT)
#define SDMA_DESC1_INT_REQ_FLAG (1ULL << 1)
#define SDMA_DESC1_HEAD_TO_HOST_FLAG (1ULL << 0)
#define SDMA_DESC1_INT_REQ_FLAG BIT_ULL(1)
#define SDMA_DESC1_HEAD_TO_HOST_FLAG BIT_ULL(0)
enum sdma_states {
sdma_state_s00_hw_down,