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[ARM] pxa: V4L2 soc_camera driver for PXA270
This patch adds a driver for the Quick Capture Interface on the PXA270. It is based on the original driver from Intel, but has been re-worked multiple times since then, now it also supports the V4L2 API. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Guennadi Liakhovetski
Russell King
parent
0e623941be
commit
3f3acefb63
3 changed files with 133 additions and 0 deletions
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@ -12,6 +12,7 @@
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#include <asm/arch/i2c.h>
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#include <asm/arch/ohci.h>
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#include <asm/arch/pxa27x_keypad.h>
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#include <asm/arch/camera.h>
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#include "devices.h"
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@ -566,6 +567,37 @@ struct platform_device pxa27x_device_ssp3 = {
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.resource = pxa27x_resource_ssp3,
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.num_resources = ARRAY_SIZE(pxa27x_resource_ssp3),
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};
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static struct resource pxa27x_resource_camera[] = {
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[0] = {
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.start = 0x50000000,
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.end = 0x50000fff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_CAMERA,
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.end = IRQ_CAMERA,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
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static struct platform_device pxa27x_device_camera = {
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.name = "pxa27x-camera",
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.id = 0, /* This is used to put cameras on this interface */
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.dev = {
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.dma_mask = &pxa27x_dma_mask_camera,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(pxa27x_resource_camera),
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.resource = pxa27x_resource_camera,
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};
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void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
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{
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pxa_register_device(&pxa27x_device_camera, info);
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}
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#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
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#ifdef CONFIG_PXA3xx
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48
include/asm-arm/arch-pxa/camera.h
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48
include/asm-arm/arch-pxa/camera.h
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@ -0,0 +1,48 @@
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/*
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camera.h - PXA camera driver header file
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Copyright (C) 2003, Intel Corporation
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Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_ARCH_CAMERA_H_
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#define __ASM_ARCH_CAMERA_H_
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#define PXA_CAMERA_MASTER 1
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#define PXA_CAMERA_DATAWIDTH_4 2
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#define PXA_CAMERA_DATAWIDTH_5 4
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#define PXA_CAMERA_DATAWIDTH_8 8
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#define PXA_CAMERA_DATAWIDTH_9 0x10
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#define PXA_CAMERA_DATAWIDTH_10 0x20
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#define PXA_CAMERA_PCLK_EN 0x40
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#define PXA_CAMERA_MCLK_EN 0x80
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#define PXA_CAMERA_PCP 0x100
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#define PXA_CAMERA_HSP 0x200
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#define PXA_CAMERA_VSP 0x400
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struct pxacamera_platform_data {
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int (*init)(struct device *);
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int (*power)(struct device *, int);
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int (*reset)(struct device *, int);
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unsigned long flags;
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unsigned long mclk_10khz;
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};
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extern void pxa_set_camera_info(struct pxacamera_platform_data *);
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#endif /* __ASM_ARCH_CAMERA_H_ */
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@ -22,10 +22,15 @@
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#define GPIO19_DREQ1 19 /* External DMA Request */
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#define GPIO20_DREQ0 20 /* External DMA Request */
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#define GPIO23_SCLK 23 /* SSP clock */
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#define GPIO23_CIF_MCLK 23 /* Camera Master Clock */
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#define GPIO24_SFRM 24 /* SSP Frame */
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#define GPIO24_CIF_FV 24 /* Camera frame start signal */
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#define GPIO25_STXD 25 /* SSP transmit */
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#define GPIO25_CIF_LV 25 /* Camera line start signal */
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#define GPIO26_SRXD 26 /* SSP receive */
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#define GPIO26_CIF_PCLK 26 /* Camera Pixel Clock */
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#define GPIO27_SEXTCLK 27 /* SSP ext_clk */
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#define GPIO27_CIF_DD_0 27 /* Camera data pin 0 */
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#define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
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#define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
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#define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
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@ -46,18 +51,24 @@
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#define GPIO41_FFRTS 41 /* FFUART request to send */
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#define GPIO42_BTRXD 42 /* BTUART receive data */
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#define GPIO42_HWRXD 42 /* HWUART receive data */
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#define GPIO42_CIF_MCLK 42 /* Camera Master Clock */
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#define GPIO43_BTTXD 43 /* BTUART transmit data */
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#define GPIO43_HWTXD 43 /* HWUART transmit data */
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#define GPIO43_CIF_FV 43 /* Camera frame start signal */
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#define GPIO44_BTCTS 44 /* BTUART clear to send */
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#define GPIO44_HWCTS 44 /* HWUART clear to send */
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#define GPIO44_CIF_LV 44 /* Camera line start signal */
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#define GPIO45_BTRTS 45 /* BTUART request to send */
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#define GPIO45_HWRTS 45 /* HWUART request to send */
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#define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */
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#define GPIO45_CIF_PCLK 45 /* Camera Pixel Clock */
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#define GPIO46_ICPRXD 46 /* ICP receive data */
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#define GPIO46_STRXD 46 /* STD_UART receive data */
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#define GPIO47_ICPTXD 47 /* ICP transmit data */
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#define GPIO47_STTXD 47 /* STD_UART transmit data */
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#define GPIO47_CIF_DD_0 47 /* Camera data pin 0 */
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#define GPIO48_nPOE 48 /* Output Enable for Card Space */
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#define GPIO48_CIF_DD_5 48 /* Camera data pin 5 */
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#define GPIO49_nPWE 49 /* Write Enable for Card Space */
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#define GPIO50_nPIOR 50 /* I/O Read for Card Space */
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#define GPIO50_CIF_DD_3 50 /* Camera data pin 3 */
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@ -112,12 +123,25 @@
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#define GPIO82_NSFRM 82 /* NSSP Frame */
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#define GPIO82_CIF_DD_5 82 /* Camera data pin 5 */
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#define GPIO83_NSTXD 83 /* NSSP transmit */
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#define GPIO83_CIF_DD_4 83 /* Camera data pin 4 */
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#define GPIO84_NSRXD 84 /* NSSP receive */
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#define GPIO84_CIF_FV 84 /* Camera frame start signal */
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#define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */
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#define GPIO85_CIF_LV 85 /* Camera line start signal */
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#define GPIO90_CIF_DD_4 90 /* Camera data pin 4 */
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#define GPIO91_CIF_DD_5 91 /* Camera data pin 5 */
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#define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */
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#define GPIO93_CIF_DD_6 93 /* Camera data pin 6 */
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#define GPIO94_CIF_DD_5 94 /* Camera data pin 5 */
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#define GPIO95_CIF_DD_4 95 /* Camera data pin 4 */
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#define GPIO98_CIF_DD_0 98 /* Camera data pin 0 */
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#define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */
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#define GPIO103_CIF_DD_3 103 /* Camera data pin 3 */
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#define GPIO104_CIF_DD_2 104 /* Camera data pin 2 */
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#define GPIO105_CIF_DD_1 105 /* Camera data pin 1 */
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#define GPIO106_CIF_DD_9 106 /* Camera data pin 9 */
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#define GPIO107_CIF_DD_8 107 /* Camera data pin 8 */
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#define GPIO108_CIF_DD_7 108 /* Camera data pin 7 */
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#define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */
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#define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */
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#define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */
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@ -126,6 +150,9 @@
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#define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */
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#define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */
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#define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */
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#define GPIO114_CIF_DD_1 114 /* Camera data pin 1 */
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#define GPIO115_CIF_DD_3 115 /* Camera data pin 3 */
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#define GPIO116_CIF_DD_2 116 /* Camera data pin 2 */
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/* GPIO alternate function mode & direction */
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@ -161,11 +188,16 @@
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#define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
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#define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
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#define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
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#define GPIO23_CIF_MCLK_MD (23 | GPIO_ALT_FN_1_OUT)
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#define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT)
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#define GPIO24_CIF_FV_MD (24 | GPIO_ALT_FN_1_OUT)
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#define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
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#define GPIO25_CIF_LV_MD (25 | GPIO_ALT_FN_1_OUT)
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#define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
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#define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
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#define GPIO26_CIF_PCLK_MD (26 | GPIO_ALT_FN_2_IN)
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#define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
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#define GPIO27_CIF_DD_0_MD (27 | GPIO_ALT_FN_3_IN)
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#define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
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#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
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#define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT)
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@ -193,25 +225,33 @@
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#define GPIO41_KP_MKOUT7_MD (41 | GPIO_ALT_FN_1_OUT)
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#define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
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#define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN)
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#define GPIO42_CIF_MCLK_MD (42 | GPIO_ALT_FN_3_OUT)
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#define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
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#define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT)
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#define GPIO43_CIF_FV_MD (43 | GPIO_ALT_FN_3_OUT)
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#define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
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#define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN)
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#define GPIO44_CIF_LV_MD (44 | GPIO_ALT_FN_3_OUT)
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#define GPIO45_CIF_PCLK_MD (45 | GPIO_ALT_FN_3_IN)
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#define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
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#define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT)
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#define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT)
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#define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
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#define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
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#define GPIO47_CIF_DD_0_MD (47 | GPIO_ALT_FN_1_IN)
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#define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
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#define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
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#define GPIO48_CIF_DD_5_MD (48 | GPIO_ALT_FN_1_IN)
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#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
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#define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT)
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#define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
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#define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN)
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#define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
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#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN)
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#define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
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#define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN)
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#define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN)
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#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN)
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#define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
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#define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT)
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#define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN)
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@ -269,26 +309,39 @@
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#define GPIO82_CIF_DD_5_MD (82 | GPIO_ALT_FN_3_IN)
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#define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT)
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#define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN)
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#define GPIO83_CIF_DD_4_MD (83 | GPIO_ALT_FN_3_IN)
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#define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT)
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#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)
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#define GPIO84_CIF_FV_MD (84 | GPIO_ALT_FN_3_IN)
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#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
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#define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN)
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#define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT)
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#define GPIO90_CIF_DD_4_MD (90 | GPIO_ALT_FN_3_IN)
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#define GPIO91_CIF_DD_5_MD (91 | GPIO_ALT_FN_3_IN)
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#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
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#define GPIO93_CIF_DD_6_MD (93 | GPIO_ALT_FN_2_IN)
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#define GPIO94_CIF_DD_5_MD (94 | GPIO_ALT_FN_2_IN)
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#define GPIO95_CIF_DD_4_MD (95 | GPIO_ALT_FN_2_IN)
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#define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN)
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#define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN)
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#define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN)
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#define GPIO98_CIF_DD_0_MD (98 | GPIO_ALT_FN_2_IN)
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#define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN)
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#define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN)
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#define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT)
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#define GPIO102_KP_MKIN2_MD (102 | GPIO_ALT_FN_1_IN)
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#define GPIO103_CIF_DD_3_MD (103 | GPIO_ALT_FN_1_IN)
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#define GPIO103_KP_MKOUT0_MD (103 | GPIO_ALT_FN_2_OUT)
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#define GPIO104_CIF_DD_2_MD (104 | GPIO_ALT_FN_1_IN)
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#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT)
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#define GPIO104_KP_MKOUT1_MD (104 | GPIO_ALT_FN_2_OUT)
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#define GPIO105_CIF_DD_1_MD (105 | GPIO_ALT_FN_1_IN)
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#define GPIO105_KP_MKOUT2_MD (105 | GPIO_ALT_FN_2_OUT)
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#define GPIO106_CIF_DD_9_MD (106 | GPIO_ALT_FN_1_IN)
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#define GPIO106_KP_MKOUT3_MD (106 | GPIO_ALT_FN_2_OUT)
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#define GPIO107_CIF_DD_8_MD (107 | GPIO_ALT_FN_1_IN)
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#define GPIO107_KP_MKOUT4_MD (107 | GPIO_ALT_FN_2_OUT)
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#define GPIO108_CIF_DD_7_MD (108 | GPIO_ALT_FN_1_IN)
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#define GPIO108_KP_MKOUT5_MD (108 | GPIO_ALT_FN_2_OUT)
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#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)
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#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)
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