From 4a77579c73413deb4aa562b6e781e3c65ff7abb2 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 21 Mar 2022 16:15:55 -0700 Subject: [PATCH 01/33] soc: qcom: socinfo: add SC7280 entry to soc_id array Add an entry for SC7280 SoC. Signed-off-by: Douglas Anderson Reviewed-by: Sai Prakash Ranjan Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220321161546.1.Ifc4270fbe9bad536f08a47696e00cca5a0714abd@changeid --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 8b38d134720a..dbdbad5db3e5 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -330,6 +330,7 @@ static const struct soc_id soc_id[] = { { 459, "SM7225" }, { 460, "SA8540P" }, { 480, "SM8450" }, + { 487, "SC7280" }, }; static const char *socinfo_machine(struct device *dev, unsigned int id) From 54c2e9256a5688a98225207734688b4b7c0f40c9 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 28 Feb 2022 22:00:13 +0300 Subject: [PATCH 02/33] soc: qcom: socinfo: Add another ID for SM8450 Add another id for SM8450. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220228190013.1790617-1-dmitry.baryshkov@linaro.org --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index dbdbad5db3e5..146ff934fdc8 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -330,6 +330,7 @@ static const struct soc_id soc_id[] = { { 459, "SM7225" }, { 460, "SA8540P" }, { 480, "SM8450" }, + { 482, "SM8450" }, { 487, "SC7280" }, }; From 8fd3f18ea31a398ecce4a6d3804433658678b0a3 Mon Sep 17 00:00:00 2001 From: Miaoqian Lin Date: Tue, 8 Mar 2022 07:19:42 +0000 Subject: [PATCH 03/33] soc: qcom: smp2p: Fix missing of_node_put() in smp2p_parse_ipc The device_node pointer is returned by of_parse_phandle() with refcount incremented. We should use of_node_put() on it when done. Fixes: 50e99641413e ("soc: qcom: smp2p: Qualcomm Shared Memory Point to Point") Signed-off-by: Miaoqian Lin Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220308071942.22942-1-linmq006@gmail.com --- drivers/soc/qcom/smp2p.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index 4a157240f419..59dbf4b61e6c 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -493,6 +493,7 @@ static int smp2p_parse_ipc(struct qcom_smp2p *smp2p) } smp2p->ipc_regmap = syscon_node_to_regmap(syscon); + of_node_put(syscon); if (IS_ERR(smp2p->ipc_regmap)) return PTR_ERR(smp2p->ipc_regmap); From aad66a3c78da668f4506356c2fdb70b7a19ecc76 Mon Sep 17 00:00:00 2001 From: Miaoqian Lin Date: Tue, 8 Mar 2022 07:36:48 +0000 Subject: [PATCH 04/33] soc: qcom: smsm: Fix missing of_node_put() in smsm_parse_ipc The device_node pointer is returned by of_parse_phandle() with refcount incremented. We should use of_node_put() on it when done. Fixes: c97c4090ff72 ("soc: qcom: smsm: Add driver for Qualcomm SMSM") Signed-off-by: Miaoqian Lin Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220308073648.24634-1-linmq006@gmail.com --- drivers/soc/qcom/smsm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c index ef15d014c03a..9df9bba242f3 100644 --- a/drivers/soc/qcom/smsm.c +++ b/drivers/soc/qcom/smsm.c @@ -374,6 +374,7 @@ static int smsm_parse_ipc(struct qcom_smsm *smsm, unsigned host_id) return 0; host->ipc_regmap = syscon_node_to_regmap(syscon); + of_node_put(syscon); if (IS_ERR(host->ipc_regmap)) return PTR_ERR(host->ipc_regmap); From ccc706353d1b89d8ff1726e575dd4a10f8550fb7 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 16 Mar 2022 11:37:14 +0530 Subject: [PATCH 05/33] dt-bindings: power: Add rpm power domain bindings for SDX65 Add RPM power domain bindings for the SDX65 SoC. Signed-off-by: Rohit Agarwal Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1647410837-22537-4-git-send-email-quic_rohiagar@quicinc.com --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 940e97b565bf..b90c4427beec 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -33,6 +33,7 @@ properties: - qcom,sc8180x-rpmhpd - qcom,sdm845-rpmhpd - qcom,sdx55-rpmhpd + - qcom,sdx65-rpmhpd - qcom,sm6115-rpmpd - qcom,sm6125-rpmpd - qcom,sm6350-rpmhpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index c002cc6ddf55..0a8978d0c78c 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -20,6 +20,14 @@ #define SDX55_MX 1 #define SDX55_CX 2 +/* SDX65 Power Domain Indexes */ +#define SDX65_MSS 0 +#define SDX65_MX 1 +#define SDX65_MX_AO 2 +#define SDX65_CX 3 +#define SDX65_CX_AO 4 +#define SDX65_MXC 5 + /* SM6350 Power Domain Indexes */ #define SM6350_CX 0 #define SM6350_GFX 1 From 3edff6262c48fe73feedc7277a3a6ebc3ed35a37 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 16 Mar 2022 11:37:15 +0530 Subject: [PATCH 06/33] soc: qcom: rpmhpd: Add SDX65 power domains Add power domains found in Qualcomm SDX65 SoC. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1647410837-22537-5-git-send-email-quic_rohiagar@quicinc.com --- drivers/soc/qcom/rpmhpd.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index 58f1dc9b9cb7..11102ac47769 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -210,6 +210,21 @@ static const struct rpmhpd_desc sdx55_desc = { .num_pds = ARRAY_SIZE(sdx55_rpmhpds), }; +/* SDX65 RPMH powerdomains */ +static struct rpmhpd *sdx65_rpmhpds[] = { + [SDX65_CX] = &cx_w_mx_parent, + [SDX65_CX_AO] = &cx_ao_w_mx_parent, + [SDX65_MSS] = &mss, + [SDX65_MX] = &mx, + [SDX65_MX_AO] = &mx_ao, + [SDX65_MXC] = &mxc, +}; + +static const struct rpmhpd_desc sdx65_desc = { + .rpmhpds = sdx65_rpmhpds, + .num_pds = ARRAY_SIZE(sdx65_rpmhpds), +}; + /* SM6350 RPMH powerdomains */ static struct rpmhpd *sm6350_rpmhpds[] = { [SM6350_CX] = &cx_w_mx_parent, @@ -369,6 +384,7 @@ static const struct of_device_id rpmhpd_match_table[] = { { .compatible = "qcom,sc8180x-rpmhpd", .data = &sc8180x_desc }, { .compatible = "qcom,sdm845-rpmhpd", .data = &sdm845_desc }, { .compatible = "qcom,sdx55-rpmhpd", .data = &sdx55_desc}, + { .compatible = "qcom,sdx65-rpmhpd", .data = &sdx65_desc}, { .compatible = "qcom,sm6350-rpmhpd", .data = &sm6350_desc }, { .compatible = "qcom,sm8150-rpmhpd", .data = &sm8150_desc }, { .compatible = "qcom,sm8250-rpmhpd", .data = &sm8250_desc }, From 3be066542ec400e7cdbcef2a6ac1d36c5366a6f6 Mon Sep 17 00:00:00 2001 From: Jakob Koschel Date: Thu, 24 Mar 2022 08:24:35 +0100 Subject: [PATCH 07/33] soc: qcom: pdr: replace usage of found with dedicated list iterator variable To move the list iterator variable into the list_for_each_entry_*() macro in the future it should be avoided to use the list iterator variable after the loop body. To *never* use the list iterator variable after the loop it was concluded to use a separate iterator variable instead of a found boolean [1]. This removes the need to use a found variable and simply checking if the variable was set, can determine if the break/goto was hit. Link: https://lore.kernel.org/all/CAHk-=wgRr_D8CB-D9Kg-c=EHreAsk5SqXPwr9Y7k9sA6cWXJ6w@mail.gmail.com/ Signed-off-by: Jakob Koschel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220324072435.63070-1-jakobkoschel@gmail.com --- drivers/soc/qcom/pdr_interface.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/soc/qcom/pdr_interface.c b/drivers/soc/qcom/pdr_interface.c index fc580a3c4336..0034af927b48 100644 --- a/drivers/soc/qcom/pdr_interface.c +++ b/drivers/soc/qcom/pdr_interface.c @@ -304,24 +304,23 @@ static void pdr_indication_cb(struct qmi_handle *qmi, notifier_hdl); const struct servreg_state_updated_ind *ind_msg = data; struct pdr_list_node *ind; - struct pdr_service *pds; - bool found = false; + struct pdr_service *pds = NULL, *iter; if (!ind_msg || !ind_msg->service_path[0] || strlen(ind_msg->service_path) > SERVREG_NAME_LENGTH) return; mutex_lock(&pdr->list_lock); - list_for_each_entry(pds, &pdr->lookups, node) { - if (strcmp(pds->service_path, ind_msg->service_path)) + list_for_each_entry(iter, &pdr->lookups, node) { + if (strcmp(iter->service_path, ind_msg->service_path)) continue; - found = true; + pds = iter; break; } mutex_unlock(&pdr->list_lock); - if (!found) + if (!pds) return; pr_info("PDR: Indication received from %s, state: 0x%x, trans-id: %d\n", From a1793920b6647447e4757aec4434eb919840acb8 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 24 Feb 2022 19:54:15 -0800 Subject: [PATCH 08/33] dt-bindings: arm: qcom: Document sa8540p, sc8180x and sc8280xp Add compatibles for the sa8540p automotive, as well as sc8180x and sc8280xp compute platforms. Also add compatibles for the ADP devboard, the Lenovo Flex 5G, Microsoft Surface Pro X and the sc8280xp QRD. Signed-off-by: Bjorn Andersson Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220225035415.2294821-1-bjorn.andersson@linaro.org --- .../devicetree/bindings/arm/qcom.yaml | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 129cdd246223..93e4e4256e73 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -39,8 +39,11 @@ description: | msm8994 msm8996 sa8155p + sa8540p sc7180 sc7280 + sc8180x + sc8280xp sdm630 sdm632 sdm660 @@ -225,6 +228,18 @@ properties: - google,senor - const: qcom,sc7280 + - items: + - enum: + - lenovo,flex-5g + - microsoft,surface-prox + - qcom,sc8180x-primus + - const: qcom,sc8180x + + - items: + - enum: + - qcom,sc8280xp-qrd + - const: qcom,sc8280xp + - items: - enum: - fairphone,fp3 @@ -258,6 +273,11 @@ properties: - qcom,sa8155p-adp - const: qcom,sa8155p + - items: + - enum: + - qcom,sa8295p-adp + - const: qcom,sa8540p + - items: - enum: - fairphone,fp4 From 5334a3b12a7233b31788de60d61bfd890059d783 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 8 Apr 2022 14:33:36 -0700 Subject: [PATCH 09/33] soc: qcom: llcc: Add MODULE_DEVICE_TABLE() The llcc-qcom driver can be compiled as a module, but lacks MODULE_DEVICE_TABLE() and will therefore not be loaded automatically. Fix this. Fixes: a3134fb09e0b ("drivers: soc: Add LLCC driver") Signed-off-by: Bjorn Andersson Reviewed-by: Sai Prakash Ranjan Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220408213336.581661-3-bjorn.andersson@linaro.org --- drivers/soc/qcom/llcc-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index eecafeded56f..85ba8209b182 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -749,6 +749,7 @@ static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sm8450-llcc", .data = &sm8450_cfg }, { } }; +MODULE_DEVICE_TABLE(of, qcom_llcc_of_match); static struct platform_driver qcom_llcc_driver = { .driver = { From d00004c4563f6c00a79f7228524966ac7a1aa29c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Apr 2022 08:55:12 +0200 Subject: [PATCH 10/33] dt-bindings: soc: qcom,smsm: convert to dtschema Convert the Qualcomm Shared Memory State Machine to DT schema. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220405065512.26521-1-krzysztof.kozlowski@linaro.org --- .../bindings/soc/qcom/qcom,smsm.txt | 104 ------------- .../bindings/soc/qcom/qcom,smsm.yaml | 138 ++++++++++++++++++ 2 files changed, 138 insertions(+), 104 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt deleted file mode 100644 index 2993b5a97dd6..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.txt +++ /dev/null @@ -1,104 +0,0 @@ -Qualcomm Shared Memory State Machine - -The Shared Memory State Machine facilitates broadcasting of single bit state -information between the processors in a Qualcomm SoC. Each processor is -assigned 32 bits of state that can be modified. A processor can through a -matrix of bitmaps signal subscription of notifications upon changes to a -certain bit owned by a certain remote processor. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,smsm" - -- qcom,ipc-N: - Usage: required - Value type: - Definition: three entries specifying the outgoing ipc bit used for - signaling the N:th remote processor - - phandle to a syscon node representing the apcs registers - - u32 representing offset to the register within the syscon - - u32 representing the ipc bit within the register - -- qcom,local-host: - Usage: optional - Value type: - Definition: identifier of the local processor in the list of hosts, or - in other words specifier of the column in the subscription - matrix representing the local processor - defaults to host 0 - -- #address-cells: - Usage: required - Value type: - Definition: must be 1 - -- #size-cells: - Usage: required - Value type: - Definition: must be 0 - -= SUBNODES -Each processor's state bits are described by a subnode of the smsm device node. -Nodes can either be flagged as an interrupt-controller to denote a remote -processor's state bits or the local processors bits. The node names are not -important. - -- reg: - Usage: required - Value type: - Definition: specifies the offset, in words, of the first bit for this - entry - -- #qcom,smem-state-cells: - Usage: required for local entry - Value type: - Definition: must be 1 - denotes bit number - -- interrupt-controller: - Usage: required for remote entries - Value type: - Definition: marks the entry as a interrupt-controller and the state bits - to belong to a remote processor - -- #interrupt-cells: - Usage: required for remote entries - Value type: - Definition: must be 2 - denotes bit number and IRQ flags - -- interrupts: - Usage: required for remote entries - Value type: - Definition: one entry specifying remote IRQ used by the remote processor - to signal changes of its state bits - - -= EXAMPLE -The following example shows the SMEM setup for controlling properties of the -wireless processor, defined from the 8974 apps processor's point-of-view. It -encompasses one outbound entry and the outgoing interrupt for the wireless -processor. - -smsm { - compatible = "qcom,smsm"; - - #address-cells = <1>; - #size-cells = <0>; - - qcom,ipc-3 = <&apcs 8 19>; - - apps_smsm: apps@0 { - reg = <0>; - - #qcom,smem-state-cells = <1>; - }; - - wcnss_smsm: wcnss@7 { - reg = <7>; - interrupts = <0 144 1>; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml new file mode 100644 index 000000000000..db67cf043256 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smsm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,smsm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Shared Memory State Machine + +maintainers: + - Andy Gross + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The Shared Memory State Machine facilitates broadcasting of single bit state + information between the processors in a Qualcomm SoC. Each processor is + assigned 32 bits of state that can be modified. A processor can through a + matrix of bitmaps signal subscription of notifications upon changes to a + certain bit owned by a certain remote processor. + +properties: + compatible: + const: qcom,smsm + + '#address-cells': + const: 1 + + qcom,local-host: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + description: + Identifier of the local processor in the list of hosts, or in other words + specifier of the column in the subscription matrix representing the local + processor. + + '#size-cells': + const: 0 + +patternProperties: + "^qcom,ipc-[1-4]$": + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to a syscon node representing the APCS registers + - description: u32 representing offset to the register within the syscon + - description: u32 representing the ipc bit within the register + description: + Three entries specifying the outgoing ipc bit used for signaling the N:th + remote processor. + + "@[0-9a-f]$": + type: object + description: + Each processor's state bits are described by a subnode of the SMSM device + node. Nodes can either be flagged as an interrupt-controller to denote a + remote processor's state bits or the local processors bits. The node + names are not important. + + properties: + reg: + maxItems: 1 + + interrupt-controller: + description: + Marks the entry as a interrupt-controller and the state bits to + belong to a remote processor. + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + description: + One entry specifying remote IRQ used by the remote processor to + signal changes of its state bits. + + '#qcom,smem-state-cells': + $ref: /schemas/types.yaml#/definitions/uint32 + const: 1 + description: + Required for local entry. Denotes bit number. + + required: + - reg + + oneOf: + - required: + - '#qcom,smem-state-cells' + - required: + - interrupt-controller + - '#interrupt-cells' + - interrupts + + additionalProperties: false + +required: + - compatible + - '#address-cells' + - '#size-cells' + +anyOf: + - required: + - qcom,ipc-1 + - required: + - qcom,ipc-2 + - required: + - qcom,ipc-3 + - required: + - qcom,ipc-4 + +additionalProperties: false + +examples: + # The following example shows the SMEM setup for controlling properties of + # the wireless processor, defined from the 8974 apps processor's + # point-of-view. It encompasses one outbound entry and the outgoing interrupt + # for the wireless processor. + - | + #include + + shared-memory { + compatible = "qcom,smsm"; + #address-cells = <1>; + #size-cells = <0>; + qcom,ipc-3 = <&apcs 8 19>; + + apps_smsm: apps@0 { + reg = <0>; + #qcom,smem-state-cells = <1>; + }; + + wcnss_smsm: wcnss@7 { + reg = <7>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; From a5ffbc04ad0327919157a643cc56de513a4c6928 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Apr 2022 08:57:52 +0200 Subject: [PATCH 11/33] dt-bindings: soc: qcom,wcnss: convert to dtschema Convert the Qualcomm WCNSS bindings to DT Schema. Changes against original bindings: fix qcom,smd-channels and qcom,smem-states names (how they are used in DTS and driver), enforce child node naming of bluetooth and wifi. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220405065752.27389-3-krzysztof.kozlowski@linaro.org --- .../bindings/soc/qcom/qcom,wcnss.txt | 131 ----------------- .../bindings/soc/qcom/qcom,wcnss.yaml | 137 ++++++++++++++++++ 2 files changed, 137 insertions(+), 131 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt deleted file mode 100644 index 1382b64e1381..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt +++ /dev/null @@ -1,131 +0,0 @@ -Qualcomm WCNSS Binding - -This binding describes the Qualcomm WCNSS hardware. It consists of control -block and a BT, WiFi and FM radio block, all using SMD as command channels. - -- compatible: - Usage: required - Value type: - Definition: must be: "qcom,wcnss", - -- qcom,smd-channel: - Usage: required - Value type: - Definition: standard SMD property specifying the SMD channel used for - communication with the WiFi firmware. - Should be "WCNSS_CTRL". - -- qcom,mmio: - Usage: required - Value type: - Definition: reference to a node specifying the wcnss "ccu" and "dxe" - register blocks. The node must be compatible with one of - the following: - "qcom,riva", - "qcom,pronto" - -- firmware-name: - Usage: optional - Value type: - Definition: specifies the relative firmware image path for the WLAN NV - blob. Defaults to "wlan/prima/WCNSS_qcom_wlan_nv.bin" if - not specified. - -= SUBNODES -The subnodes of the wcnss node are optional and describe the individual blocks in -the WCNSS. - -== Bluetooth -The following properties are defined to the bluetooth node: - -- compatible: - Usage: required - Value type: - Definition: must be: - "qcom,wcnss-bt" - -- local-bd-address: - Usage: optional - Value type: - Definition: see Documentation/devicetree/bindings/net/bluetooth.txt - -== WiFi -The following properties are defined to the WiFi node: - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,wcnss-wlan", - -- interrupts: - Usage: required - Value type: - Definition: should specify the "rx" and "tx" interrupts - -- interrupt-names: - Usage: required - Value type: - Definition: must contain "rx" and "tx" - -- qcom,smem-state: - Usage: required - Value type: - Definition: should reference the tx-enable and tx-rings-empty SMEM states - -- qcom,smem-state-names: - Usage: required - Value type: - Definition: must contain "tx-enable" and "tx-rings-empty" - -= EXAMPLE -The following example represents a SMD node, with one edge representing the -"pronto" subsystem, with the wcnss device and its wcn3680 BT and WiFi blocks -described; as found on the 8974 platform. - -smd { - compatible = "qcom,smd"; - - pronto-edge { - interrupts = <0 142 1>; - - qcom,ipc = <&apcs 8 17>; - qcom,smd-edge = <6>; - - wcnss { - compatible = "qcom,wcnss"; - qcom,smd-channels = "WCNSS_CTRL"; - - #address-cells = <1>; - #size-cells = <1>; - - qcom,mmio = <&pronto>; - - bt { - compatible = "qcom,wcnss-bt"; - - /* BD address 00:11:22:33:44:55 */ - local-bd-address = [ 55 44 33 22 11 00 ]; - }; - - wlan { - compatible = "qcom,wcnss-wlan"; - - interrupts = <0 145 0>, <0 146 0>; - interrupt-names = "tx", "rx"; - - qcom,smem-state = <&apps_smsm 10>, <&apps_smsm 9>; - qcom,smem-state-names = "tx-enable", "tx-rings-empty"; - }; - }; - }; -}; - -soc { - pronto: pronto { - compatible = "qcom,pronto"; - - reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>; - reg-names = "ccu", "dxe", "pmu"; - }; -}; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml new file mode 100644 index 000000000000..d891ecfb2691 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,wcnss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm WCNSS + +maintainers: + - Andy Gross + - Bjorn Andersson + +description: + The Qualcomm WCNSS hardware consists of control block and a BT, WiFi and FM + radio block, all using SMD as command channels. + +properties: + compatible: + const: qcom,wcnss + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + default: "wlan/prima/WCNSS_qcom_wlan_nv.bin" + description: + Relative firmware image path for the WLAN NV blob. + + qcom,mmio: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Reference to a node specifying the wcnss "ccu" and "dxe" register blocks. + The node must be compatible with one of the following:: + - qcom,riva" + - qcom,pronto" + + qcom,smd-channels: + $ref: /schemas/types.yaml#/definitions/string + const: WCNSS_CTRL + description: + Standard SMD property specifying the SMD channel used for communication + with the WiFi firmware. + + bluetooth: + type: object + additionalProperties: false + properties: + compatible: + const: qcom,wcnss-bt + + local-bd-address: + $ref: /schemas/types.yaml#/definitions/uint8-array + maxItems: 6 + description: + See Documentation/devicetree/bindings/net/bluetooth.txt + + required: + - compatible + + wifi: + additionalProperties: false + type: object + properties: + compatible: + const: qcom,wcnss-wlan + + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: tx + - const: rx + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + maxItems: 2 + description: + Should reference the tx-enable and tx-rings-empty SMEM states. + + qcom,smem-state-names: + $ref: /schemas/types.yaml#/definitions/string-array + items: + - const: tx-enable + - const: tx-rings-empty + description: + Names of SMEM states. + + required: + - compatible + - interrupts + - interrupt-names + - qcom,smem-states + - qcom,smem-state-names + +required: + - compatible + - qcom,mmio + - qcom,smd-channels + +additionalProperties: false + +examples: + - | + #include + + smd-edge { + interrupts = ; + + qcom,ipc = <&apcs 8 17>; + qcom,smd-edge = <6>; + qcom,remote-pid = <4>; + + label = "pronto"; + + wcnss { + compatible = "qcom,wcnss"; + qcom,smd-channels = "WCNSS_CTRL"; + + qcom,mmio = <&pronto>; + + bluetooth { + compatible = "qcom,wcnss-bt"; + /* BD address 00:11:22:33:44:55 */ + local-bd-address = [ 55 44 33 22 11 00 ]; + }; + + wifi { + compatible = "qcom,wcnss-wlan"; + + interrupts = , + ; + interrupt-names = "tx", "rx"; + + qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; + qcom,smem-state-names = "tx-enable", "tx-rings-empty"; + }; + }; + }; From 1dcf37365e7de6214af55587c69f4cced06262de Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Apr 2022 08:34:51 +0200 Subject: [PATCH 12/33] dt-bindings: qcom: qcom,gsbi: convert to dtschema Convert the Qualcomm General Serial Bus Interface (GSBI) to DT Schema. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220405063451.12011-10-krzysztof.kozlowski@linaro.org --- .../bindings/soc/qcom/qcom,gsbi.txt | 87 ------------ .../bindings/soc/qcom/qcom,gsbi.yaml | 132 ++++++++++++++++++ 2 files changed, 132 insertions(+), 87 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt deleted file mode 100644 index fe1855f09dcc..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt +++ /dev/null @@ -1,87 +0,0 @@ -QCOM GSBI (General Serial Bus Interface) Driver - -The GSBI controller is modeled as a node with zero or more child nodes, each -representing a serial sub-node device that is mux'd as part of the GSBI -configuration settings. The mode setting will govern the input/output mode of -the 4 GSBI IOs. - -Required properties: -- compatible: Should contain "qcom,gsbi-v1.0.0" -- cell-index: Should contain the GSBI index -- reg: Address range for GSBI registers -- clocks: required clock -- clock-names: must contain "iface" entry -- qcom,mode : indicates MUX value for configuration of the serial interface. - Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values. - -Optional properties: -- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference - dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values. -- syscon-tcsr: indicates phandle of TCSR syscon node. Required if child uses - dma. - -Required properties if child node exists: -- #address-cells: Must be 1 -- #size-cells: Must be 1 -- ranges: Must be present - -Properties for children: - -A GSBI controller node can contain 0 or more child nodes representing serial -devices. These serial devices can be a QCOM UART, I2C controller, spi -controller, or some combination of aforementioned devices. - -See the following for child node definitions: -Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt -Documentation/devicetree/bindings/spi/qcom,spi-qup.txt -Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt - -Example for APQ8064: - -#include - - gsbi4@16300000 { - compatible = "qcom,gsbi-v1.0.0"; - cell-index = <4>; - reg = <0x16300000 0x100>; - clocks = <&gcc GSBI4_H_CLK>; - clock-names = "iface"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - qcom,mode = ; - qcom,crci = ; - - syscon-tcsr = <&tcsr>; - - /* child nodes go under here */ - - i2c_qup4: i2c@16380000 { - compatible = "qcom,i2c-qup-v1.1.1"; - reg = <0x16380000 0x1000>; - interrupts = <0 153 0>; - - clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - - clock-frequency = <200000>; - - #address-cells = <1>; - #size-cells = <0>; - - }; - - uart4: serial@16340000 { - compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; - reg = <0x16340000 0x1000>, - <0x16300000 0x1000>; - interrupts = <0 152 0x0>; - clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; - clock-names = "core", "iface"; - }; - }; - - tcsr: syscon@1a400000 { - compatible = "qcom,apq8064-tcsr", "syscon"; - reg = <0x1a400000 0x100>; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.yaml new file mode 100644 index 000000000000..c33704333e49 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,gsbi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm General Serial Bus Interface (GSBI) + +maintainers: + - Andy Gross + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The GSBI controller is modeled as a node with zero or more child nodes, each + representing a serial sub-node device that is mux'd as part of the GSBI + configuration settings. The mode setting will govern the input/output mode + of the 4 GSBI IOs. + + A GSBI controller node can contain 0 or more child nodes representing serial + devices. These serial devices can be a QCOM UART, I2C controller, spi + controller, or some combination of aforementioned devices. + +properties: + compatible: + const: qcom,gsbi-v1.0.0 + + '#address-cells': + const: 1 + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The GSBI index. + + clocks: + maxItems: 1 + + clock-names: + const: iface + + qcom,crci: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + CRCI MUX value for QUP CRCI ports. Please reference + include/dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values. + + qcom,mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + MUX value for configuration of the serial interface. Please reference + include/dt-bindings/soc/qcom,gsbi.h for valid mux values. + + '#size-cells': + const: 1 + + syscon-tcsr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle of TCSR syscon node.Required if child uses dma. + + ranges: true + + reg: + maxItems: 1 + +patternProperties: + "spi@[0-9a-f]+$": + type: object + $ref: /schemas/spi/qcom,spi-qup.yaml# + + "i2c@[0-9a-f]+$": + type: object + $ref: /schemas/i2c/qcom,i2c-qup.yaml# + + "serial@[0-9a-f]+$": + type: object + $ref: /schemas/serial/qcom,msm-uartdm.yaml# + +required: + - compatible + - cell-index + - clocks + - clock-names + - qcom,mode + - reg + +additionalProperties: false + +examples: + - | + #include + #include + #include + + gsbi@12440000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12440000 0x100>; + cell-index = <1>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon-tcsr = <&tcsr>; + qcom,mode = ; + + serial@12450000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12450000 0x100>, + <0x12400000 0x03>; + interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + }; + + i2c@12460000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x12460000 0x1000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_pins_sleep>; + pinctrl-names = "default", "sleep"; + interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; /* UART chosen */ + }; + }; From ca1666463eec6a80724701bf58f33530f5642a2b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 1 Apr 2022 22:27:59 +0200 Subject: [PATCH 13/33] dt-bindings: qcom,smd-rpm: update maintainers (drop Kathiravan) Kathiravan's email bounces (585: Recipient address rejected: undeliverable address: No such user here) so switch maintainers to Andy and Bjorn (as Qualcomm platform maintainers). Signed-off-by: Krzysztof Kozlowski Acked-by: Mark Brown Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220401202759.191560-1-krzysztof.kozlowski@linaro.org --- .../devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml | 3 ++- Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml index f052e03be402..8069d32cf899 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml @@ -69,7 +69,8 @@ description: l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22 maintainers: - - Kathiravan T + - Andy Gross + - Bjorn Andersson properties: compatible: diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index b32457c2fc0b..d91b62eed5c6 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -25,7 +25,8 @@ description: | rpm_requests. maintainers: - - Kathiravan T + - Andy Gross + - Bjorn Andersson properties: compatible: From 20bb6c9de1b7e13f11d2ffe73686f4449c426807 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Singh Date: Tue, 1 Mar 2022 20:48:32 +0530 Subject: [PATCH 14/33] soc: qcom: smem: map only partitions used by local HOST SMEM driver is IO mapping complete region and CPU is doing a speculative read into a partition where local HOST does not have permission resulting in a NOC error. Map only those partitions which are accessibly to local HOST. Signed-off-by: Deepak Kumar Singh Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1646147913-15791-1-git-send-email-quic_deesin@quicinc.com --- drivers/soc/qcom/smem.c | 226 +++++++++++++++++++++++++++++----------- 1 file changed, 164 insertions(+), 62 deletions(-) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index e2057d8f1eff..fcf8e40436e3 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -195,6 +195,20 @@ struct smem_partition_header { __le32 reserved[3]; }; +/** + * struct smem_partition - describes smem partition + * @virt_base: starting virtual address of partition + * @phys_base: starting physical address of partition + * @cacheline: alignment for "cached" entries + * @size: size of partition + */ +struct smem_partition { + void __iomem *virt_base; + phys_addr_t phys_base; + size_t cacheline; + size_t size; +}; + static const u8 SMEM_PART_MAGIC[] = { 0x24, 0x50, 0x52, 0x54 }; /** @@ -250,11 +264,9 @@ struct smem_region { * struct qcom_smem - device data for the smem device * @dev: device pointer * @hwlock: reference to a hwspinlock - * @global_partition: pointer to global partition when in use - * @global_cacheline: cacheline size for global partition - * @partitions: list of pointers to partitions affecting the current - * processor/host - * @cacheline: list of cacheline sizes for each host + * @ptable: virtual base of partition table + * @global_partition: describes for global partition when in use + * @partitions: list of partitions of current processor/host * @item_count: max accepted item number * @socinfo: platform device pointer * @num_regions: number of @regions @@ -265,12 +277,11 @@ struct qcom_smem { struct hwspinlock *hwlock; - struct smem_partition_header *global_partition; - size_t global_cacheline; - struct smem_partition_header *partitions[SMEM_HOST_COUNT]; - size_t cacheline[SMEM_HOST_COUNT]; u32 item_count; struct platform_device *socinfo; + struct smem_ptable *ptable; + struct smem_partition global_partition; + struct smem_partition partitions[SMEM_HOST_COUNT]; unsigned num_regions; struct smem_region regions[]; @@ -348,14 +359,17 @@ static struct qcom_smem *__smem; #define HWSPINLOCK_TIMEOUT 1000 static int qcom_smem_alloc_private(struct qcom_smem *smem, - struct smem_partition_header *phdr, + struct smem_partition *part, unsigned item, size_t size) { struct smem_private_entry *hdr, *end; + struct smem_partition_header *phdr; size_t alloc_size; void *cached; + phdr = (struct smem_partition_header __force *)part->virt_base; + hdr = phdr_to_first_uncached_entry(phdr); end = phdr_to_last_uncached_entry(phdr); cached = phdr_to_last_cached_entry(phdr); @@ -442,7 +456,7 @@ static int qcom_smem_alloc_global(struct qcom_smem *smem, */ int qcom_smem_alloc(unsigned host, unsigned item, size_t size) { - struct smem_partition_header *phdr; + struct smem_partition *part; unsigned long flags; int ret; @@ -464,12 +478,12 @@ int qcom_smem_alloc(unsigned host, unsigned item, size_t size) if (ret) return ret; - if (host < SMEM_HOST_COUNT && __smem->partitions[host]) { - phdr = __smem->partitions[host]; - ret = qcom_smem_alloc_private(__smem, phdr, item, size); - } else if (__smem->global_partition) { - phdr = __smem->global_partition; - ret = qcom_smem_alloc_private(__smem, phdr, item, size); + if (host < SMEM_HOST_COUNT && __smem->partitions[host].virt_base) { + part = &__smem->partitions[host]; + ret = qcom_smem_alloc_private(__smem, part, item, size); + } else if (__smem->global_partition.virt_base) { + part = &__smem->global_partition; + ret = qcom_smem_alloc_private(__smem, part, item, size); } else { ret = qcom_smem_alloc_global(__smem, item, size); } @@ -511,12 +525,14 @@ static void *qcom_smem_get_global(struct qcom_smem *smem, } static void *qcom_smem_get_private(struct qcom_smem *smem, - struct smem_partition_header *phdr, - size_t cacheline, + struct smem_partition *part, unsigned item, size_t *size) { struct smem_private_entry *e, *end; + struct smem_partition_header *phdr; + + phdr = (struct smem_partition_header __force *)part->virt_base; e = phdr_to_first_uncached_entry(phdr); end = phdr_to_last_uncached_entry(phdr); @@ -538,7 +554,7 @@ static void *qcom_smem_get_private(struct qcom_smem *smem, /* Item was not found in the uncached list, search the cached list */ - e = phdr_to_first_cached_entry(phdr, cacheline); + e = phdr_to_first_cached_entry(phdr, part->cacheline); end = phdr_to_last_cached_entry(phdr); while (e > end) { @@ -553,7 +569,7 @@ static void *qcom_smem_get_private(struct qcom_smem *smem, return cached_entry_to_item(e); } - e = cached_entry_next(e, cacheline); + e = cached_entry_next(e, part->cacheline); } return ERR_PTR(-ENOENT); @@ -576,9 +592,8 @@ invalid_canary: */ void *qcom_smem_get(unsigned host, unsigned item, size_t *size) { - struct smem_partition_header *phdr; + struct smem_partition *part; unsigned long flags; - size_t cacheln; int ret; void *ptr = ERR_PTR(-EPROBE_DEFER); @@ -594,14 +609,12 @@ void *qcom_smem_get(unsigned host, unsigned item, size_t *size) if (ret) return ERR_PTR(ret); - if (host < SMEM_HOST_COUNT && __smem->partitions[host]) { - phdr = __smem->partitions[host]; - cacheln = __smem->cacheline[host]; - ptr = qcom_smem_get_private(__smem, phdr, cacheln, item, size); - } else if (__smem->global_partition) { - phdr = __smem->global_partition; - cacheln = __smem->global_cacheline; - ptr = qcom_smem_get_private(__smem, phdr, cacheln, item, size); + if (host < SMEM_HOST_COUNT && __smem->partitions[host].virt_base) { + part = &__smem->partitions[host]; + ptr = qcom_smem_get_private(__smem, part, item, size); + } else if (__smem->global_partition.virt_base) { + part = &__smem->global_partition; + ptr = qcom_smem_get_private(__smem, part, item, size); } else { ptr = qcom_smem_get_global(__smem, item, size); } @@ -622,6 +635,7 @@ EXPORT_SYMBOL(qcom_smem_get); */ int qcom_smem_get_free_space(unsigned host) { + struct smem_partition *part; struct smem_partition_header *phdr; struct smem_header *header; unsigned ret; @@ -629,12 +643,14 @@ int qcom_smem_get_free_space(unsigned host) if (!__smem) return -EPROBE_DEFER; - if (host < SMEM_HOST_COUNT && __smem->partitions[host]) { - phdr = __smem->partitions[host]; + if (host < SMEM_HOST_COUNT && __smem->partitions[host].virt_base) { + part = &__smem->partitions[host]; + phdr = part->virt_base; ret = le32_to_cpu(phdr->offset_free_cached) - le32_to_cpu(phdr->offset_free_uncached); - } else if (__smem->global_partition) { - phdr = __smem->global_partition; + } else if (__smem->global_partition.virt_base) { + part = &__smem->global_partition; + phdr = part->virt_base; ret = le32_to_cpu(phdr->offset_free_cached) - le32_to_cpu(phdr->offset_free_uncached); } else { @@ -646,6 +662,11 @@ int qcom_smem_get_free_space(unsigned host) } EXPORT_SYMBOL(qcom_smem_get_free_space); +static bool addr_in_range(void __iomem *base, size_t size, void *addr) +{ + return base && (addr >= base && addr < base + size); +} + /** * qcom_smem_virt_to_phys() - return the physical address associated * with an smem item pointer (previously returned by qcom_smem_get() @@ -655,17 +676,36 @@ EXPORT_SYMBOL(qcom_smem_get_free_space); */ phys_addr_t qcom_smem_virt_to_phys(void *p) { - unsigned i; + struct smem_partition *part; + struct smem_region *area; + u64 offset; + u32 i; + + for (i = 0; i < SMEM_HOST_COUNT; i++) { + part = &__smem->partitions[i]; + + if (addr_in_range(part->virt_base, part->size, p)) { + offset = p - part->virt_base; + + return (phys_addr_t)part->phys_base + offset; + } + } + + part = &__smem->global_partition; + + if (addr_in_range(part->virt_base, part->size, p)) { + offset = p - part->virt_base; + + return (phys_addr_t)part->phys_base + offset; + } for (i = 0; i < __smem->num_regions; i++) { - struct smem_region *region = &__smem->regions[i]; + area = &__smem->regions[i]; - if (p < region->virt_base) - continue; - if (p < region->virt_base + region->size) { - u64 offset = p - region->virt_base; + if (addr_in_range(area->virt_base, area->size, p)) { + offset = p - area->virt_base; - return region->aux_base + offset; + return (phys_addr_t)area->aux_base + offset; } } @@ -689,7 +729,7 @@ static struct smem_ptable *qcom_smem_get_ptable(struct qcom_smem *smem) struct smem_ptable *ptable; u32 version; - ptable = smem->regions[0].virt_base + smem->regions[0].size - SZ_4K; + ptable = smem->ptable; if (memcmp(ptable->magic, SMEM_PTABLE_MAGIC, sizeof(ptable->magic))) return ERR_PTR(-ENOENT); @@ -728,9 +768,14 @@ qcom_smem_partition_header(struct qcom_smem *smem, struct smem_ptable_entry *entry, u16 host0, u16 host1) { struct smem_partition_header *header; + u32 phys_addr; u32 size; - header = smem->regions[0].virt_base + le32_to_cpu(entry->offset); + phys_addr = smem->regions[0].aux_base + le32_to_cpu(entry->offset); + header = devm_ioremap_wc(smem->dev, phys_addr, le32_to_cpu(entry->size)); + + if (!header) + return NULL; if (memcmp(header->magic, SMEM_PART_MAGIC, sizeof(header->magic))) { dev_err(smem->dev, "bad partition magic %4ph\n", header->magic); @@ -772,7 +817,7 @@ static int qcom_smem_set_global_partition(struct qcom_smem *smem) bool found = false; int i; - if (smem->global_partition) { + if (smem->global_partition.virt_base) { dev_err(smem->dev, "Already found the global partition\n"); return -EINVAL; } @@ -807,8 +852,11 @@ static int qcom_smem_set_global_partition(struct qcom_smem *smem) if (!header) return -EINVAL; - smem->global_partition = header; - smem->global_cacheline = le32_to_cpu(entry->cacheline); + smem->global_partition.virt_base = (void __iomem *)header; + smem->global_partition.phys_base = smem->regions[0].aux_base + + le32_to_cpu(entry->offset); + smem->global_partition.size = le32_to_cpu(entry->size); + smem->global_partition.cacheline = le32_to_cpu(entry->cacheline); return 0; } @@ -848,7 +896,7 @@ qcom_smem_enumerate_partitions(struct qcom_smem *smem, u16 local_host) return -EINVAL; } - if (smem->partitions[remote_host]) { + if (smem->partitions[remote_host].virt_base) { dev_err(smem->dev, "duplicate host %hu\n", remote_host); return -EINVAL; } @@ -857,13 +905,47 @@ qcom_smem_enumerate_partitions(struct qcom_smem *smem, u16 local_host) if (!header) return -EINVAL; - smem->partitions[remote_host] = header; - smem->cacheline[remote_host] = le32_to_cpu(entry->cacheline); + smem->partitions[remote_host].virt_base = (void __iomem *)header; + smem->partitions[remote_host].phys_base = smem->regions[0].aux_base + + le32_to_cpu(entry->offset); + smem->partitions[remote_host].size = le32_to_cpu(entry->size); + smem->partitions[remote_host].cacheline = le32_to_cpu(entry->cacheline); } return 0; } +static int qcom_smem_map_toc(struct qcom_smem *smem, struct smem_region *region) +{ + u32 ptable_start; + + /* map starting 4K for smem header */ + region->virt_base = devm_ioremap_wc(smem->dev, region->aux_base, SZ_4K); + ptable_start = region->aux_base + region->size - SZ_4K; + /* map last 4k for toc */ + smem->ptable = devm_ioremap_wc(smem->dev, ptable_start, SZ_4K); + + if (!region->virt_base || !smem->ptable) + return -ENOMEM; + + return 0; +} + +static int qcom_smem_map_global(struct qcom_smem *smem, u32 size) +{ + u32 phys_addr; + + phys_addr = smem->regions[0].aux_base; + + smem->regions[0].size = size; + smem->regions[0].virt_base = devm_ioremap_wc(smem->dev, phys_addr, size); + + if (!smem->regions[0].virt_base) + return -ENOMEM; + + return 0; +} + static int qcom_smem_resolve_mem(struct qcom_smem *smem, const char *name, struct smem_region *region) { @@ -894,10 +976,12 @@ static int qcom_smem_probe(struct platform_device *pdev) struct smem_header *header; struct reserved_mem *rmem; struct qcom_smem *smem; + unsigned long flags; size_t array_size; int num_regions; int hwlock_id; u32 version; + u32 size; int ret; int i; @@ -933,7 +1017,12 @@ static int qcom_smem_probe(struct platform_device *pdev) return ret; } - for (i = 0; i < num_regions; i++) { + + ret = qcom_smem_map_toc(smem, &smem->regions[0]); + if (ret) + return ret; + + for (i = 1; i < num_regions; i++) { smem->regions[i].virt_base = devm_ioremap_wc(&pdev->dev, smem->regions[i].aux_base, smem->regions[i].size); @@ -950,7 +1039,30 @@ static int qcom_smem_probe(struct platform_device *pdev) return -EINVAL; } + hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); + if (hwlock_id < 0) { + if (hwlock_id != -EPROBE_DEFER) + dev_err(&pdev->dev, "failed to retrieve hwlock\n"); + return hwlock_id; + } + + smem->hwlock = hwspin_lock_request_specific(hwlock_id); + if (!smem->hwlock) + return -ENXIO; + + ret = hwspin_lock_timeout_irqsave(smem->hwlock, HWSPINLOCK_TIMEOUT, &flags); + if (ret) + return ret; + size = readl_relaxed(&header->available) + readl_relaxed(&header->free_offset); + hwspin_unlock_irqrestore(smem->hwlock, &flags); + version = qcom_smem_get_sbl_version(smem); + /* + * smem header mapping is required only in heap version scheme, so unmap + * it here. It will be remapped in qcom_smem_map_global() when whole + * partition is mapped again. + */ + devm_iounmap(smem->dev, smem->regions[0].virt_base); switch (version >> 16) { case SMEM_GLOBAL_PART_VERSION: ret = qcom_smem_set_global_partition(smem); @@ -959,6 +1071,7 @@ static int qcom_smem_probe(struct platform_device *pdev) smem->item_count = qcom_smem_get_item_count(smem); break; case SMEM_GLOBAL_HEAP_VERSION: + qcom_smem_map_global(smem, size); smem->item_count = SMEM_ITEM_COUNT; break; default: @@ -971,17 +1084,6 @@ static int qcom_smem_probe(struct platform_device *pdev) if (ret < 0 && ret != -ENOENT) return ret; - hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); - if (hwlock_id < 0) { - if (hwlock_id != -EPROBE_DEFER) - dev_err(&pdev->dev, "failed to retrieve hwlock\n"); - return hwlock_id; - } - - smem->hwlock = hwspin_lock_request_specific(hwlock_id); - if (!smem->hwlock) - return -ENXIO; - __smem = smem; smem->socinfo = platform_device_register_data(&pdev->dev, "qcom-socinfo", From f1383348ad0fe0d568dfd37f2552b0b4f044dbe5 Mon Sep 17 00:00:00 2001 From: Deepak Kumar Singh Date: Tue, 1 Mar 2022 20:48:33 +0530 Subject: [PATCH 15/33] soc: qcom: smem: validate fields of shared structures Structures in shared memory that can be modified by remote processors may have untrusted values, they should be validated before use. Adding proper validation before using fields of shared structures. Signed-off-by: Deepak Kumar Singh Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1646147913-15791-2-git-send-email-quic_deesin@quicinc.com --- drivers/soc/qcom/smem.c | 79 +++++++++++++++++++++++++++++++++++------ 1 file changed, 69 insertions(+), 10 deletions(-) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index fcf8e40436e3..3e95835653ea 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -367,13 +367,18 @@ static int qcom_smem_alloc_private(struct qcom_smem *smem, struct smem_partition_header *phdr; size_t alloc_size; void *cached; + void *p_end; phdr = (struct smem_partition_header __force *)part->virt_base; + p_end = (void *)phdr + part->size; hdr = phdr_to_first_uncached_entry(phdr); end = phdr_to_last_uncached_entry(phdr); cached = phdr_to_last_cached_entry(phdr); + if (WARN_ON((void *)end > p_end || cached > p_end)) + return -EINVAL; + while (hdr < end) { if (hdr->canary != SMEM_PRIVATE_CANARY) goto bad_canary; @@ -383,6 +388,9 @@ static int qcom_smem_alloc_private(struct qcom_smem *smem, hdr = uncached_entry_next(hdr); } + if (WARN_ON((void *)hdr > p_end)) + return -EINVAL; + /* Check that we don't grow into the cached region */ alloc_size = sizeof(*hdr) + ALIGN(size, 8); if ((void *)hdr + alloc_size > cached) { @@ -501,6 +509,8 @@ static void *qcom_smem_get_global(struct qcom_smem *smem, struct smem_header *header; struct smem_region *region; struct smem_global_entry *entry; + u64 entry_offset; + u32 e_size; u32 aux_base; unsigned i; @@ -515,9 +525,16 @@ static void *qcom_smem_get_global(struct qcom_smem *smem, region = &smem->regions[i]; if ((u32)region->aux_base == aux_base || !aux_base) { + e_size = le32_to_cpu(entry->size); + entry_offset = le32_to_cpu(entry->offset); + + if (WARN_ON(e_size + entry_offset > region->size)) + return ERR_PTR(-EINVAL); + if (size != NULL) - *size = le32_to_cpu(entry->size); - return region->virt_base + le32_to_cpu(entry->offset); + *size = e_size; + + return region->virt_base + entry_offset; } } @@ -531,8 +548,12 @@ static void *qcom_smem_get_private(struct qcom_smem *smem, { struct smem_private_entry *e, *end; struct smem_partition_header *phdr; + void *item_ptr, *p_end; + u32 padding_data; + u32 e_size; phdr = (struct smem_partition_header __force *)part->virt_base; + p_end = (void *)phdr + part->size; e = phdr_to_first_uncached_entry(phdr); end = phdr_to_last_uncached_entry(phdr); @@ -542,36 +563,65 @@ static void *qcom_smem_get_private(struct qcom_smem *smem, goto invalid_canary; if (le16_to_cpu(e->item) == item) { - if (size != NULL) - *size = le32_to_cpu(e->size) - - le16_to_cpu(e->padding_data); + if (size != NULL) { + e_size = le32_to_cpu(e->size); + padding_data = le16_to_cpu(e->padding_data); - return uncached_entry_to_item(e); + if (WARN_ON(e_size > part->size || padding_data > e_size)) + return ERR_PTR(-EINVAL); + + *size = e_size - padding_data; + } + + item_ptr = uncached_entry_to_item(e); + if (WARN_ON(item_ptr > p_end)) + return ERR_PTR(-EINVAL); + + return item_ptr; } e = uncached_entry_next(e); } + if (WARN_ON((void *)e > p_end)) + return ERR_PTR(-EINVAL); + /* Item was not found in the uncached list, search the cached list */ e = phdr_to_first_cached_entry(phdr, part->cacheline); end = phdr_to_last_cached_entry(phdr); + if (WARN_ON((void *)e < (void *)phdr || (void *)end > p_end)) + return ERR_PTR(-EINVAL); + while (e > end) { if (e->canary != SMEM_PRIVATE_CANARY) goto invalid_canary; if (le16_to_cpu(e->item) == item) { - if (size != NULL) - *size = le32_to_cpu(e->size) - - le16_to_cpu(e->padding_data); + if (size != NULL) { + e_size = le32_to_cpu(e->size); + padding_data = le16_to_cpu(e->padding_data); - return cached_entry_to_item(e); + if (WARN_ON(e_size > part->size || padding_data > e_size)) + return ERR_PTR(-EINVAL); + + *size = e_size - padding_data; + } + + item_ptr = cached_entry_to_item(e); + if (WARN_ON(item_ptr < (void *)phdr)) + return ERR_PTR(-EINVAL); + + return item_ptr; } e = cached_entry_next(e, part->cacheline); } + if (WARN_ON((void *)e < (void *)phdr)) + return ERR_PTR(-EINVAL); + return ERR_PTR(-ENOENT); invalid_canary: @@ -648,14 +698,23 @@ int qcom_smem_get_free_space(unsigned host) phdr = part->virt_base; ret = le32_to_cpu(phdr->offset_free_cached) - le32_to_cpu(phdr->offset_free_uncached); + + if (ret > le32_to_cpu(part->size)) + return -EINVAL; } else if (__smem->global_partition.virt_base) { part = &__smem->global_partition; phdr = part->virt_base; ret = le32_to_cpu(phdr->offset_free_cached) - le32_to_cpu(phdr->offset_free_uncached); + + if (ret > le32_to_cpu(part->size)) + return -EINVAL; } else { header = __smem->regions[0].virt_base; ret = le32_to_cpu(header->available); + + if (ret > __smem->regions[0].size) + return -EINVAL; } return ret; From a175c6faaa36b1a4c7d945bd3fb0c354c9323623 Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Mon, 7 Mar 2022 20:17:24 +0100 Subject: [PATCH 16/33] dt-bindings: firmware: qcom-scm: Document msm8976 bindings SCM driver on MSM8976 requires 3 clocks. Signed-off-by: Adam Skladowski Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220307191726.10869-4-a39.skl@gmail.com --- Documentation/devicetree/bindings/firmware/qcom,scm.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index b1cd4ad1889a..0f4e5ab26477 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -19,6 +19,7 @@ Required properties: * "qcom,scm-msm8953" * "qcom,scm-msm8960" * "qcom,scm-msm8974" + * "qcom,scm-msm8976" * "qcom,scm-msm8994" * "qcom,scm-msm8996" * "qcom,scm-msm8998" @@ -37,7 +38,7 @@ Required properties: * core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and "qcom,scm-msm8960" * core, iface and bus clocks required for "qcom,scm-apq8084", - "qcom,scm-msm8916", "qcom,scm-msm8953" and "qcom,scm-msm8974" + "qcom,scm-msm8916", "qcom,scm-msm8953", "qcom,scm-msm8974" and "qcom,scm-msm8976" - clock-names: Must contain "core" for the core clock, "iface" for the interface clock and "bus" for the bus clock per the requirements of the compatible. - qcom,dload-mode: phandle to the TCSR hardware block and offset of the From 34128350b838840b17a1770269158dc0430177d3 Mon Sep 17 00:00:00 2001 From: Adam Skladowski Date: Mon, 7 Mar 2022 20:17:25 +0100 Subject: [PATCH 17/33] firmware: qcom_scm: Add compatible for MSM8976 SoC Add compatible for SCM on MSM8976. Signed-off-by: Adam Skladowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220307191726.10869-5-a39.skl@gmail.com --- drivers/firmware/qcom_scm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 491bbf70c94a..3163660fa8e2 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1379,6 +1379,10 @@ static const struct of_device_id qcom_scm_dt_match[] = { SCM_HAS_IFACE_CLK | SCM_HAS_BUS_CLK) }, + { .compatible = "qcom,scm-msm8976", .data = (void *)(SCM_HAS_CORE_CLK | + SCM_HAS_IFACE_CLK | + SCM_HAS_BUS_CLK) + }, { .compatible = "qcom,scm-msm8994" }, { .compatible = "qcom,scm-msm8996" }, { .compatible = "qcom,scm" }, From 375eed5f51a84dee4cf933a2ec0710bab9a8df69 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 1 Apr 2022 22:10:33 +0200 Subject: [PATCH 18/33] dt-bindings: soc: qcom,smd: convert to dtschema Convert the Qualcomm Shared Memory Driver bindings to DT Schema. Changes against original bindings: enforce only specific names of child nodes, instead of any names. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220401201035.189106-9-krzysztof.kozlowski@linaro.org --- .../regulator/qcom,smd-rpm-regulator.yaml | 2 +- .../bindings/remoteproc/qcom,q6v5.txt | 2 +- .../bindings/remoteproc/qcom,wcnss-pil.txt | 2 +- .../bindings/soc/qcom/qcom,smd-rpm.yaml | 4 +- .../devicetree/bindings/soc/qcom/qcom,smd.txt | 98 ------------- .../bindings/soc/qcom/qcom,smd.yaml | 137 ++++++++++++++++++ 6 files changed, 142 insertions(+), 103 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml index 8069d32cf899..6a9a7eed466f 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml @@ -12,7 +12,7 @@ description: resides as a subnode of the SMD. As such, the SMD-RPM regulator requires that the SMD and RPM nodes be present. - Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt for + Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml for information pertaining to the SMD node. Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt index 8f1507052afd..b677900b3aae 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt @@ -250,7 +250,7 @@ the memory regions used by the Hexagon firmware. Each sub-node must contain: The Hexagon node may also have an subnode named either "smd-edge" or "glink-edge" that describes the communication edge, channels and devices -related to the Hexagon. See ../soc/qcom/qcom,smd.txt and +related to the Hexagon. See ../soc/qcom/qcom,smd.yaml and ../soc/qcom/qcom,glink.txt for details on how to describe these. = EXAMPLE diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt index a83080b8905c..ac423f4c3f1b 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt +++ b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.txt @@ -111,7 +111,7 @@ and its resource dependencies. It is described by the following properties: The wcnss node can also have an subnode named "smd-edge" that describes the SMD edge, channels and devices related to the WCNSS. -See ../soc/qcom/qcom,smd.txt for details on how to describe the SMD edge. +See ../soc/qcom/qcom,smd.yaml for details on how to describe the SMD edge. = EXAMPLE The following example describes the resources needed to boot control the WCNSS, diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index d91b62eed5c6..c4ca384be196 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -12,7 +12,7 @@ description: | to vote for state of the system resources, such as clocks, regulators and bus frequencies. - The SMD information for the RPM edge should be filled out. See qcom,smd.txt + The SMD information for the RPM edge should be filled out. See qcom,smd.yaml for the required edge properties. All SMD related properties will reside within the RPM node itself. @@ -83,7 +83,7 @@ examples: qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - rpm_requests { + rpm-requests { compatible = "qcom,rpm-msm8974"; qcom,smd-channels = "rpm_requests"; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt deleted file mode 100644 index 234ae2256501..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt +++ /dev/null @@ -1,98 +0,0 @@ -Qualcomm Shared Memory Driver (SMD) binding - -This binding describes the Qualcomm Shared Memory Driver, a fifo based -communication channel for sending data between the various subsystems in -Qualcomm platforms. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,smd" - -= EDGES - -Each subnode of the SMD node represents a remote subsystem or a remote -processor of some sort - or in SMD language an "edge". The name of the edges -are not important. -The edge is described by the following properties: - -- interrupts: - Usage: required - Value type: - Definition: should specify the IRQ used by the remote processor to - signal this processor about communication related updates - -- mboxes: - Usage: required - Value type: - Definition: reference to the associated doorbell in APCS, as described - in mailbox/mailbox.txt - -- qcom,ipc: - Usage: required, unless mboxes is specified - Value type: - Definition: three entries specifying the outgoing ipc bit used for - signaling the remote processor: - - phandle to a syscon node representing the apcs registers - - u32 representing offset to the register within the syscon - - u32 representing the ipc bit within the register - -- qcom,smd-edge: - Usage: required - Value type: - Definition: the identifier of the remote processor in the smd channel - allocation table - -- qcom,remote-pid: - Usage: optional - Value type: - Definition: the identifier for the remote processor as known by the rest - of the system. - -- label: - Usage: optional - Value type: - Definition: name of the edge, used for debugging and identification - purposes. The node name will be used if this is not - present. - -= SMD DEVICES - -In turn, subnodes of the "edges" represent devices tied to SMD channels on that -"edge". The names of the devices are not important. The properties of these -nodes are defined by the individual bindings for the SMD devices - but must -contain the following property: - -- qcom,smd-channels: - Usage: required - Value type: - Definition: a list of channels tied to this device, used for matching - the device to channels - -= EXAMPLE - -The following example represents a smd node, with one edge representing the -"rpm" subsystem. For the "rpm" subsystem we have a device tied to the -"rpm_request" channel. - - apcs: syscon@f9011000 { - compatible = "syscon"; - reg = <0xf9011000 0x1000>; - }; - - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = <0 168 1>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests { - compatible = "qcom,rpm-msm8974"; - qcom,smd-channels = "rpm_requests"; - - ... - }; - }; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml new file mode 100644 index 000000000000..e6f9ffa1c0ea --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,smd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Shared Memory Driver + +maintainers: + - Andy Gross + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The Qualcomm Shared Memory Driver is a FIFO based communication channel for + sending data between the various subsystems in Qualcomm platforms. + +properties: + compatible: + const: qcom,smd + +patternProperties: + "^.*-edge|rpm$": + type: object + description: + Each subnode of the SMD node represents a remote subsystem or a remote + processor of some sort - or in SMD language an "edge". The name of the + edges are not important. + + properties: + interrupts: + maxItems: 1 + + label: + $ref: /schemas/types.yaml#/definitions/string + description: + Name of the edge, used for debugging and identification purposes. The + node name will be used if this is not present. + + mboxes: + maxItems: 1 + description: + Reference to the mailbox representing the outgoing doorbell in APCS for + this client. + + qcom,ipc: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to a syscon node representing the APCS registers + - description: u32 representing offset to the register within the syscon + - description: u32 representing the ipc bit within the register + description: + Three entries specifying the outgoing ipc bit used for signaling the + remote processor. + + qcom,smd-edge: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The identifier of the remote processor in the smd channel allocation + table. + + qcom,remote-pid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The identifier for the remote processor as known by the rest of the + system. + + # Binding for edge subnodes is not complete + patternProperties: + "^rpm-requests$": + type: object + description: + In turn, subnodes of the "edges" represent devices tied to SMD + channels on that "edge". The names of the devices are not + important. The properties of these nodes are defined by the + individual bindings for the SMD devices. + + properties: + qcom,smd-channels: + $ref: /schemas/types.yaml#/definitions/string-array + minItems: 1 + maxItems: 32 + description: + A list of channels tied to this device, used for matching the + device to channels. + + required: + - compatible + - qcom,smd-channels + + additionalProperties: true + + required: + - interrupts + - qcom,smd-edge + + oneOf: + - required: + - mboxes + - required: + - qcom,ipc + + additionalProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + # The following example represents a smd node, with one edge representing the + # "rpm" subsystem. For the "rpm" subsystem we have a device tied to the + # "rpm_request" channel. + - | + #include + + shared-memory { + compatible = "qcom,smd"; + + rpm { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm-requests { + compatible = "qcom,rpm-msm8974"; + qcom,smd-channels = "rpm_requests"; + + clock-controller { + compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + }; + }; + }; From 7b5d44212076e7474bc8d86bcf38829992a14cc2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 08:40:17 +0200 Subject: [PATCH 19/33] dt-bindings: qcom: qcom,geni-se: refer to dtschema for SPI After adding DT schema for the SPI controller, the Qualcomm GENI Serial Engine QUP Wrapper Controller bindings can reference it directly for full schema validation. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Kuldeep Singh Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220404064017.68634-2-krzysztof.kozlowski@linaro.org --- .../bindings/soc/qcom/qcom,geni-se.yaml | 22 +------------------ 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml index 95fcb43675d6..1ca081b1664e 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml @@ -103,27 +103,7 @@ patternProperties: supports up to 50MHz, up to four chip selects, programmable data path from 4 bits to 32 bits and numerous protocol variants. - $ref: /schemas/spi/spi-controller.yaml# - - properties: - compatible: - enum: - - qcom,geni-spi - - interrupts: - maxItems: 1 - - "#address-cells": - const: 1 - - "#size-cells": - const: 0 - - required: - - compatible - - interrupts - - "#address-cells" - - "#size-cells" + $ref: /schemas/spi/qcom,spi-geni-qcom.yaml# "i2c@[0-9a-f]+$": type: object From 0b9fe9b7792f31674fbc8eb165c3b22a32d0a434 Mon Sep 17 00:00:00 2001 From: Michael Srba Date: Mon, 11 Apr 2022 09:21:54 +0200 Subject: [PATCH 20/33] dt-bindings: bus: add device tree bindings for qcom,ssc-block-bus Adds bindings for the AHB bus which exposes the SSC block in the global address space. This bus (and the SSC block itself) is present on certain qcom SoCs. In typical configuration, this bus (as some of the clocks and registers that we need to manipulate) is not accessible to the OS, and the resources on this bus are indirectly accessed by communicating with a hexagon CPU core residing in the SSC block. In this configuration, the hypervisor is the one performing the bus initialization for the purposes of bringing the haxagon CPU core out of reset. However, it is possible to change the configuration, in which case this binding serves to allow the OS to initialize the bus. Signed-off-by: Michael Srba Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411072156.24451-4-michael.srba@seznam.cz --- .../bindings/bus/qcom,ssc-block-bus.yaml | 147 ++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml diff --git a/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml new file mode 100644 index 000000000000..5b9705079015 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs + +maintainers: + - Michael Srba + +description: | + This binding describes the dependencies (clocks, resets, power domains) which + need to be turned on in a sequence before communication over the AHB bus + becomes possible. + + Additionally, the reg property is used to pass to the driver the location of + two sadly undocumented registers which need to be poked as part of the sequence. + + The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart + controllers, a hexagon core, and a clock controller which provides clocks for + the above. + +properties: + compatible: + items: + - const: qcom,msm8998-ssc-block-bus + - const: qcom,ssc-block-bus + + reg: + description: | + Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1 + registers + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: mpm_sscaon_config0 + - const: mpm_sscaon_config1 + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + + ranges: true + + clocks: + minItems: 6 + maxItems: 6 + + clock-names: + items: + - const: xo + - const: aggre2 + - const: gcc_im_sleep + - const: aggre2_north + - const: ssc_xo + - const: ssc_ahbs + + power-domains: + description: Power domain phandles for the ssc_cx and ssc_mx power domains + minItems: 2 + maxItems: 2 + + power-domain-names: + items: + - const: ssc_cx + - const: ssc_mx + + resets: + description: | + Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the + branch control register associated with the ssc_xo and ssc_ahbs clocks) + minItems: 2 + maxItems: 2 + + reset-names: + items: + - const: ssc_reset + - const: ssc_bcr + + qcom,halt-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: describes how to locate the ssc AXI halt register + items: + - items: + - description: Phandle reference to a syscon representing TCSR + - description: offset for the ssc AXI halt register + +required: + - compatible + - reg + - reg-names + - '#address-cells' + - '#size-cells' + - ranges + - clocks + - clock-names + - power-domains + - power-domain-names + - resets + - reset-names + - qcom,halt-regs + +additionalProperties: + type: object + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + // devices under this node are physically located in the SSC block, connected to an ssc-internal bus; + ssc_ahb_slave: bus@10ac008 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus"; + reg = <0x10ac008 0x4>, <0x10ac010 0x4>; + reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1"; + + clocks = <&xo>, + <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, + <&gcc GCC_IM_SLEEP>, + <&gcc AGGRE2_SNOC_NORTH_AXI>, + <&gcc SSC_XO>, + <&gcc SSC_CNOC_AHBS_CLK>; + clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs"; + + resets = <&gcc GCC_SSC_RESET>, <&gcc GCC_SSC_BCR>; + reset-names = "ssc_reset", "ssc_bcr"; + + power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>; + power-domain-names = "ssc_cx", "ssc_mx"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x26000>; + }; + }; From 97d485edc1d9902c9ae3b2242144abdf85edd4c1 Mon Sep 17 00:00:00 2001 From: Michael Srba Date: Mon, 11 Apr 2022 09:21:55 +0200 Subject: [PATCH 21/33] bus: add driver for initializing the SSC bus on (some) qcom SoCs Add bindings for the AHB bus which exposes the SSC (Snapdragon Sensor Core) block in the global address space. This bus (and the SSC block itself) is present on certain qcom SoCs. In typical configuration, this bus (as some of the clocks and registers that we need to manipulate) is not accessible to Linux, and the resources on this bus are indirectly accessed by communicating with a hexagon CPU core residing in the SSC block. In this configuration, the hypervisor is the one performing the bus initialization for the purposes of bringing the hexagon CPU core out of reset. However, it is possible to change the configuration, in which case this driver will initialize the bus. In combination with drivers for resources on the SSC bus, this driver can aid in debugging, and for example with a TLMM driver can be used to directly access SSC-dedicated GPIO pins, removing the need to commit to a particular usecase during hw design. Finally, until open firmware for the hexagon core is available, this approach allows for using sensors hooked up to SSC-dedicated GPIO pins on mainline Linux simply by utilizing the existing in-tree drivers for these sensors. Signed-off-by: Michael Srba Reviewed-by: Jeffrey Hugo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411072156.24451-5-michael.srba@seznam.cz --- drivers/bus/Kconfig | 11 + drivers/bus/Makefile | 1 + drivers/bus/qcom-ssc-block-bus.c | 389 +++++++++++++++++++++++++++++++ 3 files changed, 401 insertions(+) create mode 100644 drivers/bus/qcom-ssc-block-bus.c diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 3c68e174a113..7bfe998f3514 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -152,6 +152,17 @@ config QCOM_EBI2 Interface 2, which can be used to connect things like NAND Flash, SRAM, ethernet adapters, FPGAs and LCD displays. +config QCOM_SSC_BLOCK_BUS + bool "Qualcomm SSC Block Bus Init Driver" + depends on ARCH_QCOM + help + Say y here to enable support for initializing the bus that connects + the SSC block's internal bus to the cNoC (configurantion NoC) on + (some) qcom SoCs. + The SSC (Snapdragon Sensor Core) block contains a gpio controller, + i2c/spi/uart controllers, a hexagon core, and a clock controller + which provides clocks for the above. + config SUN50I_DE2_BUS bool "Allwinner A64 DE2 Bus Driver" default ARM64 diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index 16da51130d1a..d90eed189a65 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o +obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/qcom-ssc-block-bus.c b/drivers/bus/qcom-ssc-block-bus.c new file mode 100644 index 000000000000..eedeb29a5ff3 --- /dev/null +++ b/drivers/bus/qcom-ssc-block-bus.c @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2021, Michael Srba + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* AXI Halt Register Offsets */ +#define AXI_HALTREQ_REG 0x0 +#define AXI_HALTACK_REG 0x4 +#define AXI_IDLE_REG 0x8 + +#define SSCAON_CONFIG0_CLAMP_EN_OVRD BIT(4) +#define SSCAON_CONFIG0_CLAMP_EN_OVRD_VAL BIT(5) + +static const char *const qcom_ssc_block_pd_names[] = { + "ssc_cx", + "ssc_mx" +}; + +struct qcom_ssc_block_bus_data { + const char *const *pd_names; + struct device *pds[ARRAY_SIZE(qcom_ssc_block_pd_names)]; + char __iomem *reg_mpm_sscaon_config0; + char __iomem *reg_mpm_sscaon_config1; + struct regmap *halt_map; + struct clk *xo_clk; + struct clk *aggre2_clk; + struct clk *gcc_im_sleep_clk; + struct clk *aggre2_north_clk; + struct clk *ssc_xo_clk; + struct clk *ssc_ahbs_clk; + struct reset_control *ssc_bcr; + struct reset_control *ssc_reset; + u32 ssc_axi_halt; + int num_pds; +}; + +static void reg32_set_bits(char __iomem *reg, u32 value) +{ + u32 tmp = ioread32(reg); + + iowrite32(tmp | value, reg); +} + +static void reg32_clear_bits(char __iomem *reg, u32 value) +{ + u32 tmp = ioread32(reg); + + iowrite32(tmp & (~value), reg); +} + +static int qcom_ssc_block_bus_init(struct device *dev) +{ + int ret; + + struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev); + + ret = clk_prepare_enable(data->xo_clk); + if (ret) { + dev_err(dev, "error enabling xo_clk: %d\n", ret); + goto err_xo_clk; + } + + ret = clk_prepare_enable(data->aggre2_clk); + if (ret) { + dev_err(dev, "error enabling aggre2_clk: %d\n", ret); + goto err_aggre2_clk; + } + + ret = clk_prepare_enable(data->gcc_im_sleep_clk); + if (ret) { + dev_err(dev, "error enabling gcc_im_sleep_clk: %d\n", ret); + goto err_gcc_im_sleep_clk; + } + + /* + * We need to intervene here because the HW logic driving these signals cannot handle + * initialization after power collapse by itself. + */ + reg32_clear_bits(data->reg_mpm_sscaon_config0, + SSCAON_CONFIG0_CLAMP_EN_OVRD | SSCAON_CONFIG0_CLAMP_EN_OVRD_VAL); + /* override few_ack/rest_ack */ + reg32_clear_bits(data->reg_mpm_sscaon_config1, BIT(31)); + + ret = clk_prepare_enable(data->aggre2_north_clk); + if (ret) { + dev_err(dev, "error enabling aggre2_north_clk: %d\n", ret); + goto err_aggre2_north_clk; + } + + ret = reset_control_deassert(data->ssc_reset); + if (ret) { + dev_err(dev, "error deasserting ssc_reset: %d\n", ret); + goto err_ssc_reset; + } + + ret = reset_control_deassert(data->ssc_bcr); + if (ret) { + dev_err(dev, "error deasserting ssc_bcr: %d\n", ret); + goto err_ssc_bcr; + } + + regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 0); + + ret = clk_prepare_enable(data->ssc_xo_clk); + if (ret) { + dev_err(dev, "error deasserting ssc_xo_clk: %d\n", ret); + goto err_ssc_xo_clk; + } + + ret = clk_prepare_enable(data->ssc_ahbs_clk); + if (ret) { + dev_err(dev, "error deasserting ssc_ahbs_clk: %d\n", ret); + goto err_ssc_ahbs_clk; + } + + return 0; + +err_ssc_ahbs_clk: + clk_disable(data->ssc_xo_clk); + +err_ssc_xo_clk: + regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 1); + + reset_control_assert(data->ssc_bcr); + +err_ssc_bcr: + reset_control_assert(data->ssc_reset); + +err_ssc_reset: + clk_disable(data->aggre2_north_clk); + +err_aggre2_north_clk: + reg32_set_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5)); + reg32_set_bits(data->reg_mpm_sscaon_config1, BIT(31)); + + clk_disable(data->gcc_im_sleep_clk); + +err_gcc_im_sleep_clk: + clk_disable(data->aggre2_clk); + +err_aggre2_clk: + clk_disable(data->xo_clk); + +err_xo_clk: + return ret; +} + +static void qcom_ssc_block_bus_deinit(struct device *dev) +{ + int ret; + + struct qcom_ssc_block_bus_data *data = dev_get_drvdata(dev); + + clk_disable(data->ssc_xo_clk); + clk_disable(data->ssc_ahbs_clk); + + ret = reset_control_assert(data->ssc_bcr); + if (ret) + dev_err(dev, "error asserting ssc_bcr: %d\n", ret); + + regmap_write(data->halt_map, data->ssc_axi_halt + AXI_HALTREQ_REG, 1); + + reg32_set_bits(data->reg_mpm_sscaon_config1, BIT(31)); + reg32_set_bits(data->reg_mpm_sscaon_config0, BIT(4) | BIT(5)); + + ret = reset_control_assert(data->ssc_reset); + if (ret) + dev_err(dev, "error asserting ssc_reset: %d\n", ret); + + clk_disable(data->gcc_im_sleep_clk); + + clk_disable(data->aggre2_north_clk); + + clk_disable(data->aggre2_clk); + clk_disable(data->xo_clk); +} + +static int qcom_ssc_block_bus_pds_attach(struct device *dev, struct device **pds, + const char *const *pd_names, size_t num_pds) +{ + int ret; + int i; + + for (i = 0; i < num_pds; i++) { + pds[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]); + if (IS_ERR_OR_NULL(pds[i])) { + ret = PTR_ERR(pds[i]) ? : -ENODATA; + goto unroll_attach; + } + } + + return num_pds; + +unroll_attach: + for (i--; i >= 0; i--) + dev_pm_domain_detach(pds[i], false); + + return ret; +}; + +static void qcom_ssc_block_bus_pds_detach(struct device *dev, struct device **pds, size_t num_pds) +{ + int i; + + for (i = 0; i < num_pds; i++) + dev_pm_domain_detach(pds[i], false); +} + +static int qcom_ssc_block_bus_pds_enable(struct device **pds, size_t num_pds) +{ + int ret; + int i; + + for (i = 0; i < num_pds; i++) { + dev_pm_genpd_set_performance_state(pds[i], INT_MAX); + ret = pm_runtime_get_sync(pds[i]); + if (ret < 0) + goto unroll_pd_votes; + } + + return 0; + +unroll_pd_votes: + for (i--; i >= 0; i--) { + dev_pm_genpd_set_performance_state(pds[i], 0); + pm_runtime_put(pds[i]); + } + + return ret; +}; + +static void qcom_ssc_block_bus_pds_disable(struct device **pds, size_t num_pds) +{ + int i; + + for (i = 0; i < num_pds; i++) { + dev_pm_genpd_set_performance_state(pds[i], 0); + pm_runtime_put(pds[i]); + } +} + +static int qcom_ssc_block_bus_probe(struct platform_device *pdev) +{ + struct qcom_ssc_block_bus_data *data; + struct device_node *np = pdev->dev.of_node; + struct of_phandle_args halt_args; + struct resource *res; + int ret; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + platform_set_drvdata(pdev, data); + + data->pd_names = qcom_ssc_block_pd_names; + data->num_pds = ARRAY_SIZE(qcom_ssc_block_pd_names); + + /* power domains */ + ret = qcom_ssc_block_bus_pds_attach(&pdev->dev, data->pds, data->pd_names, data->num_pds); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "error when attaching power domains\n"); + + ret = qcom_ssc_block_bus_pds_enable(data->pds, data->num_pds); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "error when enabling power domains\n"); + + /* low level overrides for when the HW logic doesn't "just work" */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config0"); + data->reg_mpm_sscaon_config0 = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->reg_mpm_sscaon_config0)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->reg_mpm_sscaon_config0), + "Failed to ioremap mpm_sscaon_config0\n"); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpm_sscaon_config1"); + data->reg_mpm_sscaon_config1 = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(data->reg_mpm_sscaon_config1)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->reg_mpm_sscaon_config1), + "Failed to ioremap mpm_sscaon_config1\n"); + + /* resets */ + data->ssc_bcr = devm_reset_control_get_exclusive(&pdev->dev, "ssc_bcr"); + if (IS_ERR(data->ssc_bcr)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->ssc_bcr), + "Failed to acquire reset: scc_bcr\n"); + + data->ssc_reset = devm_reset_control_get_exclusive(&pdev->dev, "ssc_reset"); + if (IS_ERR(data->ssc_reset)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->ssc_reset), + "Failed to acquire reset: ssc_reset:\n"); + + /* clocks */ + data->xo_clk = devm_clk_get(&pdev->dev, "xo"); + if (IS_ERR(data->xo_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->xo_clk), + "Failed to get clock: xo\n"); + + data->aggre2_clk = devm_clk_get(&pdev->dev, "aggre2"); + if (IS_ERR(data->aggre2_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->aggre2_clk), + "Failed to get clock: aggre2\n"); + + data->gcc_im_sleep_clk = devm_clk_get(&pdev->dev, "gcc_im_sleep"); + if (IS_ERR(data->gcc_im_sleep_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->gcc_im_sleep_clk), + "Failed to get clock: gcc_im_sleep\n"); + + data->aggre2_north_clk = devm_clk_get(&pdev->dev, "aggre2_north"); + if (IS_ERR(data->aggre2_north_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->aggre2_north_clk), + "Failed to get clock: aggre2_north\n"); + + data->ssc_xo_clk = devm_clk_get(&pdev->dev, "ssc_xo"); + if (IS_ERR(data->ssc_xo_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->ssc_xo_clk), + "Failed to get clock: ssc_xo\n"); + + data->ssc_ahbs_clk = devm_clk_get(&pdev->dev, "ssc_ahbs"); + if (IS_ERR(data->ssc_ahbs_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(data->ssc_ahbs_clk), + "Failed to get clock: ssc_ahbs\n"); + + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, "qcom,halt-regs", 1, 0, + &halt_args); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to parse qcom,halt-regs\n"); + + data->halt_map = syscon_node_to_regmap(halt_args.np); + of_node_put(halt_args.np); + if (IS_ERR(data->halt_map)) + return PTR_ERR(data->halt_map); + + data->ssc_axi_halt = halt_args.args[0]; + + qcom_ssc_block_bus_init(&pdev->dev); + + of_platform_populate(np, NULL, NULL, &pdev->dev); + + return 0; +} + +static int qcom_ssc_block_bus_remove(struct platform_device *pdev) +{ + struct qcom_ssc_block_bus_data *data = platform_get_drvdata(pdev); + + qcom_ssc_block_bus_deinit(&pdev->dev); + + iounmap(data->reg_mpm_sscaon_config0); + iounmap(data->reg_mpm_sscaon_config1); + + qcom_ssc_block_bus_pds_disable(data->pds, data->num_pds); + qcom_ssc_block_bus_pds_detach(&pdev->dev, data->pds, data->num_pds); + pm_runtime_disable(&pdev->dev); + pm_clk_destroy(&pdev->dev); + + return 0; +} + +static const struct of_device_id qcom_ssc_block_bus_of_match[] = { + { .compatible = "qcom,ssc-block-bus", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, qcom_ssc_block_bus_of_match); + +static struct platform_driver qcom_ssc_block_bus_driver = { + .probe = qcom_ssc_block_bus_probe, + .remove = qcom_ssc_block_bus_remove, + .driver = { + .name = "qcom-ssc-block-bus", + .of_match_table = qcom_ssc_block_bus_of_match, + }, +}; + +module_platform_driver(qcom_ssc_block_bus_driver); + +MODULE_DESCRIPTION("A driver for handling the init sequence needed for accessing the SSC block on (some) qcom SoCs over AHB"); +MODULE_AUTHOR("Michael Srba "); +MODULE_LICENSE("GPL v2"); From 38d46b0f41ec57c734f1a647055644c2131c3d8f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 11 Apr 2022 10:59:35 +0200 Subject: [PATCH 22/33] dt-bindings: soc: qcom,rpmh-rsc: convert to dtschema Convert the Qualcomm RPMH RSC bindings to DT Schema. Changes against original bindings: 1. Add qcom,tcs-offset as a property instead of one of reg (not used that way). 2. Add limits to interrupts. 3. Add child nodes (bcm-voter, clock-controller, power-controller). 4. Extend the example with more complex one. The device description and DTS examples were copied from existing sources, so keep the license as GPL-2.0-only. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411085935.130072-4-krzysztof.kozlowski@linaro.org --- .../bindings/interconnect/qcom,bcm-voter.yaml | 8 +- .../bindings/soc/qcom/qcom,rpmh-rsc.yaml | 272 ++++++++++++++++++ .../devicetree/bindings/soc/qcom/rpmh-rsc.txt | 137 --------- 3 files changed, 276 insertions(+), 141 deletions(-) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml delete mode 100644 Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt diff --git a/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml b/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml index e23df4836c6f..eec987640b37 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.yaml @@ -45,20 +45,20 @@ additionalProperties: false examples: # Example 1: apps bcm_voter on SDM845 SoC should be defined inside &apps_rsc node - # as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt + # as defined in Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml - | - apps_bcm_voter: bcm_voter { + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; # Example 2: disp bcm_voter on SDM845 should be defined inside &disp_rsc node - # as defined in Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt + # as defined in Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml - | #include - disp_bcm_voter: bcm_voter { + disp_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; qcom,tcs-wait = ; }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml new file mode 100644 index 000000000000..f5ecf4a8c377 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml @@ -0,0 +1,272 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMH RSC + +maintainers: + - Bjorn Andersson + +description: | + Resource Power Manager Hardened (RPMH) is the mechanism for communicating + with the hardened resource accelerators on Qualcomm SoCs. Requests to the + resources can be written to the Trigger Command Set (TCS) registers and + using a (addr, val) pair and triggered. Messages in the TCS are then sent in + sequence over an internal bus. + + The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity + (Resource State Coordinator a.k.a RSC) that can handle multiple sleep and + active/wake resource requests. Multiple such DRVs can exist in a SoC and can + be written to from Linux. The structure of each DRV follows the same template + with a few variations that are captured by the properties here. + + A TCS may be triggered from Linux or triggered by the F/W after all the CPUs + have powered off to facilitate idle power saving. TCS could be classified as:: + ACTIVE - Triggered by Linux + SLEEP - Triggered by F/W + WAKE - Triggered by F/W + CONTROL - Triggered by F/W + See also:: + + The order in which they are described in the DT, should match the hardware + configuration. + + Requests can be made for the state of a resource, when the subsystem is + active or idle. When all subsystems like Modem, GPU, CPU are idle, the + resource state will be an aggregate of the sleep votes from each of those + subsystems. Clients may request a sleep value for their shared resources in + addition to the active mode requests. + + Drivers that want to use the RSC to communicate with RPMH must specify their + bindings as child nodes of the RSC controllers they wish to communicate with. + +properties: + compatible: + const: qcom,rpmh-rsc + + interrupts: + minItems: 1 + maxItems: 4 + description: + The interrupt that trips when a message complete/response is received for + this DRV from the accelerators. + Number of interrupts must match number of DRV blocks. + + label: + description: + Name for the RSC. The name would be used in trace logs. + + qcom,drv-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The ID of the DRV in the RSC block that will be used by this controller. + + qcom,tcs-config: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + - items: + - description: TCS type + enum: [ 0, 1, 2, 3 ] + - description: Number of TCS + - items: + - description: TCS type + enum: [ 0, 1, 2, 3 ] + - description: Number of TCS + - items: + - description: TCS type + enum: [ 0, 1, 2, 3] + - description: Numbe r of TCS + - items: + - description: TCS type + enum: [ 0, 1, 2, 3 ] + - description: Number of TCS + description: | + The tuple defining the configuration of TCS. Must have two cells which + describe each TCS type. The order of the TCS must match the hardware + configuration. + Cell 1 (TCS Type):: TCS types to be specified:: + - ACTIVE_TCS + - SLEEP_TCS + - WAKE_TCS + - CONTROL_TCS + Cell 2 (Number of TCS):: + + qcom,tcs-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The offset of the TCS blocks. + + reg: + minItems: 1 + maxItems: 4 + + reg-names: + minItems: 1 + items: + - const: drv-0 + - const: drv-1 + - const: drv-2 + - const: drv-3 + + bcm-voter: + $ref: /schemas/interconnect/qcom,bcm-voter.yaml# + + clock-controller: + $ref: /schemas/clock/qcom,rpmhcc.yaml# + + power-controller: + $ref: /schemas/power/qcom,rpmpd.yaml# + +patternProperties: + '-regulators$': + $ref: /schemas/regulator/qcom,rpmh-regulator.yaml# + +required: + - compatible + - interrupts + - qcom,drv-id + - qcom,tcs-config + - qcom,tcs-offset + - reg + - reg-names + +additionalProperties: false + +examples: + - | + // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of + // 2, the register offsets for DRV2 start at 0D00, the register + // calculations are like this:: + // DRV0: 0x179C0000 + // DRV2: 0x179C0000 + 0x10000 = 0x179D0000 + // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000 + // TCS-OFFSET: 0xD00 + #include + #include + + rsc@179c0000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x179c0000 0x10000>, + <0x179d0000 0x10000>, + <0x179e0000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + label = "apps_rsc"; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + }; + + - | + // For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the + // register offsets for DRV0 start at 01C00, the register calculations are + // like this:: + // DRV0: 0xAF20000 + // TCS-OFFSET: 0x1C00 + #include + #include + + rsc@af20000 { + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x10000>; + reg-names = "drv-0"; + interrupts = ; + label = "disp_rsc"; + qcom,tcs-offset = <0x1c00>; + qcom,drv-id = <0>; + qcom,tcs-config = , + , + , + ; + }; + + - | + #include + #include + #include + + rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x18200000 0x10000>, + <0x18210000 0x10000>, + <0x18220000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + label = "apps_rsc"; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + clock-controller { + compatible = "qcom,sm8350-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + power-controller { + compatible = "qcom,sm8350-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; + + bcm-voter { + compatible = "qcom,bcm-voter"; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt b/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt deleted file mode 100644 index 9b86d1eff219..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/rpmh-rsc.txt +++ /dev/null @@ -1,137 +0,0 @@ -RPMH RSC: ------------- - -Resource Power Manager Hardened (RPMH) is the mechanism for communicating with -the hardened resource accelerators on Qualcomm SoCs. Requests to the resources -can be written to the Trigger Command Set (TCS) registers and using a (addr, -val) pair and triggered. Messages in the TCS are then sent in sequence over an -internal bus. - -The hardware block (Direct Resource Voter or DRV) is a part of the h/w entity -(Resource State Coordinator a.k.a RSC) that can handle multiple sleep and -active/wake resource requests. Multiple such DRVs can exist in a SoC and can -be written to from Linux. The structure of each DRV follows the same template -with a few variations that are captured by the properties here. - -A TCS may be triggered from Linux or triggered by the F/W after all the CPUs -have powered off to facilitate idle power saving. TCS could be classified as - - - ACTIVE /* Triggered by Linux */ - SLEEP /* Triggered by F/W */ - WAKE /* Triggered by F/W */ - CONTROL /* Triggered by F/W */ - -The order in which they are described in the DT, should match the hardware -configuration. - -Requests can be made for the state of a resource, when the subsystem is active -or idle. When all subsystems like Modem, GPU, CPU are idle, the resource state -will be an aggregate of the sleep votes from each of those subsystems. Clients -may request a sleep value for their shared resources in addition to the active -mode requests. - -Properties: - -- compatible: - Usage: required - Value type: - Definition: Should be "qcom,rpmh-rsc". - -- reg: - Usage: required - Value type: - Definition: The first register specifies the base address of the - DRV(s). The number of DRVs in the dependent on the RSC. - The tcs-offset specifies the start address of the - TCS in the DRVs. - -- reg-names: - Usage: required - Value type: - Definition: Maps the register specified in the reg property. Must be - "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The - -- interrupts: - Usage: required - Value type: - Definition: The interrupt that trips when a message complete/response - is received for this DRV from the accelerators. - -- qcom,drv-id: - Usage: required - Value type: - Definition: The id of the DRV in the RSC block that will be used by - this controller. - -- qcom,tcs-config: - Usage: required - Value type: - Definition: The tuple defining the configuration of TCS. - Must have 2 cells which describe each TCS type. - . - The order of the TCS must match the hardware - configuration. - - Cell #1 (TCS Type): TCS types to be specified - - ACTIVE_TCS - SLEEP_TCS - WAKE_TCS - CONTROL_TCS - - Cell #2 (Number of TCS): - -- label: - Usage: optional - Value type: - Definition: Name for the RSC. The name would be used in trace logs. - -Drivers that want to use the RSC to communicate with RPMH must specify their -bindings as child nodes of the RSC controllers they wish to communicate with. - -Example 1: - -For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the -register offsets for DRV2 start at 0D00, the register calculations are like -this - -DRV0: 0x179C0000 -DRV2: 0x179C0000 + 0x10000 = 0x179D0000 -DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000 -TCS-OFFSET: 0xD00 - - apps_rsc: rsc@179c0000 { - label = "apps_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0x179c0000 0x10000>, - <0x179d0000 0x10000>, - <0x179e0000 0x10000>; - reg-names = "drv-0", "drv-1", "drv-2"; - interrupts = , - , - ; - qcom,tcs-offset = <0xd00>; - qcom,drv-id = <2>; - qcom,tcs-config = , - , - , - ; - }; - -Example 2: - -For a TCS whose RSC base address is 0xAF20000 and is at DRV id of 0, the -register offsets for DRV0 start at 01C00, the register calculations are like -this - -DRV0: 0xAF20000 -TCS-OFFSET: 0x1C00 - - disp_rsc: rsc@af20000 { - label = "disp_rsc"; - compatible = "qcom,rpmh-rsc"; - reg = <0xaf20000 0x10000>; - reg-names = "drv-0"; - interrupts = ; - qcom,tcs-offset = <0x1c00>; - qcom,drv-id = <0>; - qcom,tcs-config = , - , - , - ; - }; From fcf2c0f7cbcad29f1decb88567e54c2451b60ba5 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Mon, 4 Apr 2022 23:59:35 +0530 Subject: [PATCH 23/33] dt-bindings: qcom: geni-se: Update I2C schema reference We now have geni based QUP I2C controller binding in place as dt-bindigs/i2c/qcom,i2c-geni-qcom.yaml similar to other controllers, update reference in parent schema and while at it, also remove properties defined for the controller from common wrapper. Signed-off-by: Kuldeep Singh Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220404182938.29492-3-singh.kuldeep87k@gmail.com --- .../bindings/soc/qcom/qcom,geni-se.yaml | 26 +------------------ 1 file changed, 1 insertion(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml index 1ca081b1664e..d3c89a6dd9f3 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml @@ -108,31 +108,7 @@ patternProperties: "i2c@[0-9a-f]+$": type: object description: GENI serial engine based I2C controller. - $ref: /schemas/i2c/i2c-controller.yaml# - - properties: - compatible: - enum: - - qcom,geni-i2c - - interrupts: - maxItems: 1 - - "#address-cells": - const: 1 - - "#size-cells": - const: 0 - - clock-frequency: - description: Desired I2C bus clock frequency in Hz. - default: 100000 - - required: - - compatible - - interrupts - - "#address-cells" - - "#size-cells" + $ref: /schemas/i2c/qcom,i2c-geni-qcom.yaml# "serial@[0-9a-f]+$": type: object From 6579f39290bf056442850094b8f4b95163c17996 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Mon, 4 Apr 2022 23:59:37 +0530 Subject: [PATCH 24/33] dt-bindings: qcom: geni-se: Update UART schema reference We now have geni based QUP UART controller individual binding, update reference in parent schema and remove properties from common wrapper. With removal of last child node schema, remove common properties of all the controllers as they have become obsolete now. Signed-off-by: Kuldeep Singh Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220404182938.29492-5-singh.kuldeep87k@gmail.com --- .../bindings/soc/qcom/qcom,geni-se.yaml | 51 +------------------ 1 file changed, 1 insertion(+), 50 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml index d3c89a6dd9f3..006e9f6f4dc5 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml @@ -64,39 +64,6 @@ required: - ranges patternProperties: - "^.*@[0-9a-f]+$": - type: object - description: Common properties for GENI Serial Engine based I2C, SPI and - UART controller. - - properties: - reg: - description: GENI Serial Engine register address and length. - maxItems: 1 - - clock-names: - const: se - - clocks: - description: Serial engine core clock needed by the device. - maxItems: 1 - - interconnects: - minItems: 2 - maxItems: 3 - - interconnect-names: - minItems: 2 - items: - - const: qup-core - - const: qup-config - - const: qup-memory - - required: - - reg - - clock-names - - clocks - "spi@[0-9a-f]+$": type: object description: GENI serial engine based SPI controller. SPI in master mode @@ -113,23 +80,7 @@ patternProperties: "serial@[0-9a-f]+$": type: object description: GENI Serial Engine based UART Controller. - $ref: /schemas/serial.yaml# - - properties: - compatible: - enum: - - qcom,geni-uart - - qcom,geni-debug-uart - - interrupts: - minItems: 1 - items: - - description: UART core irq - - description: Wakeup irq (RX GPIO) - - required: - - compatible - - interrupts + $ref: /schemas/serial/qcom,serial-geni-qcom.yaml# additionalProperties: false From 5f9e72a4025b232ef0ddd5b6e4189e81091322fe Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 11 Apr 2022 17:55:28 +0200 Subject: [PATCH 25/33] dt-bindings: soc: qcom,smp2p: convert to dtschema Convert the Qualcomm Shared Memory Point 2 Point bindings to DT Schema. Changes against original bindings: enforce only specific names of child nodes, instead of any names. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411155528.502889-1-krzysztof.kozlowski@linaro.org --- .../bindings/soc/qcom/qcom,smp2p.txt | 110 ------------- .../bindings/soc/qcom/qcom,smp2p.yaml | 145 ++++++++++++++++++ 2 files changed, 145 insertions(+), 110 deletions(-) delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt deleted file mode 100644 index 49e1d72d3648..000000000000 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.txt +++ /dev/null @@ -1,110 +0,0 @@ -Qualcomm Shared Memory Point 2 Point binding - -The Shared Memory Point to Point (SMP2P) protocol facilitates communication of -a single 32-bit value between two processors. Each value has a single writer -(the local side) and a single reader (the remote side). Values are uniquely -identified in the system by the directed edge (local processor ID to remote -processor ID) and a string identifier. - -- compatible: - Usage: required - Value type: - Definition: must be one of: - "qcom,smp2p" - -- interrupts: - Usage: required - Value type: - Definition: one entry specifying the smp2p notification interrupt - -- mboxes: - Usage: required - Value type: - Definition: reference to the associated doorbell in APCS, as described - in mailbox/mailbox.txt - -- qcom,ipc: - Usage: required, unless mboxes is specified - Value type: - Definition: three entries specifying the outgoing ipc bit used for - signaling the remote end of the smp2p edge: - - phandle to a syscon node representing the apcs registers - - u32 representing offset to the register within the syscon - - u32 representing the ipc bit within the register - -- qcom,smem: - Usage: required - Value type: - Definition: two identifiers of the inbound and outbound smem items used - for this edge - -- qcom,local-pid: - Usage: required - Value type: - Definition: specifies the identifier of the local endpoint of this edge - -- qcom,remote-pid: - Usage: required - Value type: - Definition: specifies the identifier of the remote endpoint of this edge - -= SUBNODES -Each SMP2P pair contain a set of inbound and outbound entries, these are -described in subnodes of the smp2p device node. The node names are not -important. - -- qcom,entry-name: - Usage: required - Value type: - Definition: specifies the name of this entry, for inbound entries this - will be used to match against the remotely allocated entry - and for outbound entries this name is used for allocating - entries - -- interrupt-controller: - Usage: required for incoming entries - Value type: - Definition: marks the entry as inbound; the node should be specified - as a two cell interrupt-controller as defined in - "../interrupt-controller/interrupts.txt" - If not specified this node will denote the outgoing entry - -- #interrupt-cells: - Usage: required for incoming entries - Value type: - Definition: must be 2 - denoting the bit in the entry and IRQ flags - -- #qcom,smem-state-cells: - Usage: required for outgoing entries - Value type: - Definition: must be 1 - denoting the bit in the entry - -= EXAMPLE -The following example shows the SMP2P setup with the wireless processor, -defined from the 8974 apps processor's point-of-view. It encompasses one -inbound and one outbound entry: - -wcnss-smp2p { - compatible = "qcom,smp2p"; - qcom,smem = <431>, <451>; - - interrupts = <0 143 1>; - - qcom,ipc = <&apcs 8 18>; - - qcom,local-pid = <0>; - qcom,remote-pid = <4>; - - wcnss_smp2p_out: master-kernel { - qcom,entry-name = "master-kernel"; - - #qcom,smem-state-cells = <1>; - }; - - wcnss_smp2p_in: slave-kernel { - qcom,entry-name = "slave-kernel"; - - interrupt-controller; - #interrupt-cells = <2>; - }; -}; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml new file mode 100644 index 000000000000..795bd8cd4104 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smp2p.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,smp2p.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Shared Memory Point 2 Point + +maintainers: + - Andy Gross + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The Shared Memory Point to Point (SMP2P) protocol facilitates communication + of a single 32-bit value between two processors. Each value has a single + writer (the local side) and a single reader (the remote side). Values are + uniquely identified in the system by the directed edge (local processor ID to + remote processor ID) and a string identifier. + +properties: + compatible: + const: qcom,smp2p + + interrupts: + maxItems: 1 + + mboxes: + maxItems: 1 + description: + Reference to the mailbox representing the outgoing doorbell in APCS for + this client. + + qcom,ipc: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to a syscon node representing the APCS registers + - description: u32 representing offset to the register within the syscon + - description: u32 representing the ipc bit within the register + description: + Three entries specifying the outgoing ipc bit used for signaling the + remote end of the smp2p edge. + + qcom,local-pid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The identifier of the local endpoint of this edge. + + qcom,remote-pid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The identifier of the remote endpoint of this edge. + + qcom,smem: + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + maxItems: 2 + description: + Two identifiers of the inbound and outbound smem items used for this edge. + +patternProperties: + "^master-kernel|slave-kernel|ipa-ap-to-modem|ipa-modem-to-ap$": + type: object + description: + Each SMP2P pair contain a set of inbound and outbound entries, these are + described in subnodes of the smp2p device node. The node names are not + important. + + properties: + interrupt-controller: + description: + Marks the entry as inbound; the node should be specified as a two + cell interrupt-controller. If not specified this node will denote + the outgoing entry. + + '#interrupt-cells': + const: 2 + + qcom,entry-name: + $ref: /schemas/types.yaml#/definitions/string + description: + The name of this entry, for inbound entries this will be used to + match against the remotely allocated entry and for outbound entries + this name is used for allocating entries. + + '#qcom,smem-state-cells': + $ref: /schemas/types.yaml#/definitions/uint32 + const: 1 + description: + Required for outgoing entries. + + required: + - qcom,entry-name + + oneOf: + - required: + - interrupt-controller + - '#interrupt-cells' + - required: + - '#qcom,smem-state-cells' + + additionalProperties: false + +required: + - compatible + - interrupts + - qcom,local-pid + - qcom,remote-pid + - qcom,smem + +oneOf: + - required: + - mboxes + - required: + - qcom,ipc + +additionalProperties: false + +examples: + # The following example shows the SMP2P setup with the wireless processor, + # defined from the 8974 apps processor's point-of-view. It encompasses one + # inbound and one outbound entry. + - | + #include + + shared-memory { + compatible = "qcom,smp2p"; + qcom,smem = <431>, <451>; + interrupts = ; + qcom,ipc = <&apcs 8 18>; + qcom,local-pid = <0>; + qcom,remote-pid = <4>; + + wcnss_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + wcnss_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; From a555b382e7640b80b20816cf9179d091dd7716eb Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 15 Apr 2022 21:54:49 +0200 Subject: [PATCH 26/33] soc: qcom: socinfo: Sort out 8974PRO names MSM8974PRO is commonly used for referring to Snapdragon 801, compared to MSM8974 which is Snapdragon 800. The Snapdragon 801 has three variants with different clock speeds, with the -AA, -AB and -AC suffix. Adjust the names in socinfo to reflect this. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415195449.617040-1-luca@z3ntu.xyz --- drivers/soc/qcom/socinfo.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 146ff934fdc8..cee579a267a6 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -236,24 +236,24 @@ static const struct soc_id soc_id[] = { { 184, "APQ8074" }, { 185, "MSM8274" }, { 186, "MSM8674" }, - { 194, "MSM8974PRO" }, + { 194, "MSM8974PRO-AC" }, { 198, "MSM8126" }, { 199, "APQ8026" }, { 200, "MSM8926" }, { 205, "MSM8326" }, { 206, "MSM8916" }, { 207, "MSM8994" }, - { 208, "APQ8074-AA" }, - { 209, "APQ8074-AB" }, - { 210, "APQ8074PRO" }, - { 211, "MSM8274-AA" }, - { 212, "MSM8274-AB" }, - { 213, "MSM8274PRO" }, - { 214, "MSM8674-AA" }, - { 215, "MSM8674-AB" }, - { 216, "MSM8674PRO" }, - { 217, "MSM8974-AA" }, - { 218, "MSM8974-AB" }, + { 208, "APQ8074PRO-AA" }, + { 209, "APQ8074PRO-AB" }, + { 210, "APQ8074PRO-AC" }, + { 211, "MSM8274PRO-AA" }, + { 212, "MSM8274PRO-AB" }, + { 213, "MSM8274PRO-AC" }, + { 214, "MSM8674PRO-AA" }, + { 215, "MSM8674PRO-AB" }, + { 216, "MSM8674PRO-AC" }, + { 217, "MSM8974PRO-AA" }, + { 218, "MSM8974PRO-AB" }, { 219, "APQ8028" }, { 220, "MSM8128" }, { 221, "MSM8228" }, From 5bdcae1fe1c567c08e8bb7ef20fc70d0b70d5fc4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 08:40:16 +0200 Subject: [PATCH 27/33] spi: dt-bindings: qcom,spi-geni-qcom: convert to dtschema Convert the GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) bindings to DT Schema. The original bindings in TXT were not complete, so add during conversion properties already used in DTS and/or in the driver: dmas, interconnects, operating points and power-domains. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220404064017.68634-1-krzysztof.kozlowski@linaro.org --- .../bindings/spi/qcom,spi-geni-qcom.txt | 39 ------ .../bindings/spi/qcom,spi-geni-qcom.yaml | 116 ++++++++++++++++++ 2 files changed, 116 insertions(+), 39 deletions(-) delete mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt deleted file mode 100644 index c8c1e913f4e7..000000000000 --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt +++ /dev/null @@ -1,39 +0,0 @@ -GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) - -The QUP v3 core is a GENI based AHB slave that provides a common data path -(an output FIFO and an input FIFO) for serial peripheral interface (SPI) -mini-core. - -SPI in master mode supports up to 50MHz, up to four chip selects, programmable -data path from 4 bits to 32 bits and numerous protocol variants. - -Required properties: -- compatible: Must contain "qcom,geni-spi". -- reg: Must contain SPI register location and length. -- interrupts: Must contain SPI controller interrupts. -- clock-names: Must contain "se". -- clocks: Serial engine core clock needed by the device. -- #address-cells: Must be <1> to define a chip select address on - the SPI bus. -- #size-cells: Must be <0>. - -SPI Controller nodes must be child of GENI based Qualcomm Universal -Peripharal. Please refer GENI based QUP wrapper controller node bindings -described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml. - -SPI slave nodes must be children of the SPI master node and conform to SPI bus -binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt. - -Example: - spi0: spi@a84000 { - compatible = "qcom,geni-spi"; - reg = <0xa84000 0x4000>; - interrupts = ; - clock-names = "se"; - clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qup_1_spi_2_active>; - pinctrl-1 = <&qup_1_spi_2_sleep>; - #address-cells = <1>; - #size-cells = <0>; - }; diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml new file mode 100644 index 000000000000..e2c7b934c50d --- /dev/null +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-geni-qcom.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI) + +maintainers: + - Andy Gross + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + The QUP v3 core is a GENI based AHB slave that provides a common data path + (an output FIFO and an input FIFO) for serial peripheral interface (SPI) + mini-core. + + SPI in master mode supports up to 50MHz, up to four chip selects, + programmable data path from 4 bits to 32 bits and numerous protocol variants. + + SPI Controller nodes must be child of GENI based Qualcomm Universal + Peripharal. Please refer GENI based QUP wrapper controller node bindings + described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: qcom,geni-spi + + clocks: + maxItems: 1 + + clock-names: + const: se + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: qup-core + - const: qup-config + + interrupts: + maxItems: 1 + + operating-points-v2: true + + power-domains: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - interrupts + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x00880000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7180_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + }; + + - | + #include + + spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x00884000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_default>; + interrupts = ; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + }; From dbfb5f94e084287f0a3f23d14ef6692c43c98855 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 26 Apr 2022 16:35:06 -0700 Subject: [PATCH 28/33] dt-bindings: power: rpmpd: Add sc8280xp RPMh power-domains The sc8280xp has 13 power-domains controlled through the RPMh, document the compatible and provide definitions for the power-domains - and their active-only variants where applicable. The SA8540p differs slightly in the power domains exposed, so add a separate compatible for this, but reuse the constants to allow sharing the DeviceTree source. Signed-off-by: Bjorn Andersson Acked-by: Krzysztof Kozlowski Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20220426233508.1762345-2-bjorn.andersson@linaro.org --- .../devicetree/bindings/power/qcom,rpmpd.yaml | 2 ++ include/dt-bindings/power/qcom-rpmpd.h | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index b90c4427beec..ad77a6380f38 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -27,10 +27,12 @@ properties: - qcom,msm8998-rpmpd - qcom,qcm2290-rpmpd - qcom,qcs404-rpmpd + - qcom,sa8540p-rpmhpd - qcom,sdm660-rpmpd - qcom,sc7180-rpmhpd - qcom,sc7280-rpmhpd - qcom,sc8180x-rpmhpd + - qcom,sc8280xp-rpmhpd - qcom,sdm845-rpmhpd - qcom,sdx55-rpmhpd - qcom,sdx65-rpmhpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 0a8978d0c78c..6cce5b7aa940 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -125,6 +125,24 @@ #define SC8180X_MX 9 #define SC8180X_MX_AO 10 +/* SC8280XP Power Domain Indexes */ +#define SC8280XP_CX 0 +#define SC8280XP_CX_AO 1 +#define SC8280XP_DDR 2 +#define SC8280XP_EBI 3 +#define SC8280XP_GFX 4 +#define SC8280XP_LCX 5 +#define SC8280XP_LMX 6 +#define SC8280XP_MMCX 7 +#define SC8280XP_MMCX_AO 8 +#define SC8280XP_MSS 9 +#define SC8280XP_MX 10 +#define SC8280XP_MXC 12 +#define SC8280XP_MX_AO 11 +#define SC8280XP_NSP 13 +#define SC8280XP_QPHY 14 +#define SC8280XP_XO 15 + /* SDM845 Power Domain performance levels */ #define RPMH_REGULATOR_LEVEL_RETENTION 16 #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 From af77132e9d2bc8ca477003fef15e2c677ae958b1 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 26 Apr 2022 16:35:07 -0700 Subject: [PATCH 29/33] soc: qcom: rpmhpd: Don't warn about sparse rpmhpd arrays In some cases the DT binding will fully describe the set of available RPMh power-domains, but there is no reason for exposing them all in the implementation. Omitting individual data->domains is handle gracefully by of_genpd_add_provider_onecell(), so there's no reason for printing a warning when this occurs. Signed-off-by: Bjorn Andersson Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20220426233508.1762345-3-bjorn.andersson@linaro.org --- drivers/soc/qcom/rpmhpd.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index 11102ac47769..f8d28e902942 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -613,10 +613,8 @@ static int rpmhpd_probe(struct platform_device *pdev) data->num_domains = num_pds; for (i = 0; i < num_pds; i++) { - if (!rpmhpds[i]) { - dev_warn(dev, "rpmhpds[%d] is empty\n", i); + if (!rpmhpds[i]) continue; - } rpmhpds[i]->dev = dev; rpmhpds[i]->addr = cmd_db_read_addr(rpmhpds[i]->res_name); From f68f1cb3437d338ee88a9fc05acd19dacdb9aabd Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 26 Apr 2022 16:35:08 -0700 Subject: [PATCH 30/33] soc: qcom: rpmhpd: add sc8280xp & sa8540p rpmh power-domains The Qualcomm sc8280xp platform has 13 and the sa8540p platform has 11 power-domains. Add compatibles, the typically used ones power-domains and their relevant active-only variants, to the RPMh power-domain driver. Signed-off-by: Bjorn Andersson Reviewed-by: Johan Hovold Link: https://lore.kernel.org/r/20220426233508.1762345-4-bjorn.andersson@linaro.org --- drivers/soc/qcom/rpmhpd.c | 53 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index f8d28e902942..05fff8691ee3 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -180,6 +180,36 @@ static struct rpmhpd mxc_ao = { .res_name = "mxc.lvl", }; +static struct rpmhpd nsp = { + .pd = { .name = "nsp", }, + .res_name = "nsp.lvl", +}; + +static struct rpmhpd qphy = { + .pd = { .name = "qphy", }, + .res_name = "qphy.lvl", +}; + +/* SA8540P RPMH powerdomains */ +static struct rpmhpd *sa8540p_rpmhpds[] = { + [SC8280XP_CX] = &cx, + [SC8280XP_CX_AO] = &cx_ao, + [SC8280XP_EBI] = &ebi, + [SC8280XP_GFX] = &gfx, + [SC8280XP_LCX] = &lcx, + [SC8280XP_LMX] = &lmx, + [SC8280XP_MMCX] = &mmcx, + [SC8280XP_MMCX_AO] = &mmcx_ao, + [SC8280XP_MX] = &mx, + [SC8280XP_MX_AO] = &mx_ao, + [SC8280XP_NSP] = &nsp, +}; + +static const struct rpmhpd_desc sa8540p_desc = { + .rpmhpds = sa8540p_rpmhpds, + .num_pds = ARRAY_SIZE(sa8540p_rpmhpds), +}; + /* SDM845 RPMH powerdomains */ static struct rpmhpd *sdm845_rpmhpds[] = { [SDM845_CX] = &cx_w_mx_parent, @@ -378,10 +408,33 @@ static const struct rpmhpd_desc sc8180x_desc = { .num_pds = ARRAY_SIZE(sc8180x_rpmhpds), }; +/* SC8280xp RPMH powerdomains */ +static struct rpmhpd *sc8280xp_rpmhpds[] = { + [SC8280XP_CX] = &cx, + [SC8280XP_CX_AO] = &cx_ao, + [SC8280XP_EBI] = &ebi, + [SC8280XP_GFX] = &gfx, + [SC8280XP_LCX] = &lcx, + [SC8280XP_LMX] = &lmx, + [SC8280XP_MMCX] = &mmcx, + [SC8280XP_MMCX_AO] = &mmcx_ao, + [SC8280XP_MX] = &mx, + [SC8280XP_MX_AO] = &mx_ao, + [SC8280XP_NSP] = &nsp, + [SC8280XP_QPHY] = &qphy, +}; + +static const struct rpmhpd_desc sc8280xp_desc = { + .rpmhpds = sc8280xp_rpmhpds, + .num_pds = ARRAY_SIZE(sc8280xp_rpmhpds), +}; + static const struct of_device_id rpmhpd_match_table[] = { + { .compatible = "qcom,sa8540p-rpmhpd", .data = &sa8540p_desc }, { .compatible = "qcom,sc7180-rpmhpd", .data = &sc7180_desc }, { .compatible = "qcom,sc7280-rpmhpd", .data = &sc7280_desc }, { .compatible = "qcom,sc8180x-rpmhpd", .data = &sc8180x_desc }, + { .compatible = "qcom,sc8280xp-rpmhpd", .data = &sc8280xp_desc }, { .compatible = "qcom,sdm845-rpmhpd", .data = &sdm845_desc }, { .compatible = "qcom,sdx55-rpmhpd", .data = &sdx55_desc}, { .compatible = "qcom,sdx65-rpmhpd", .data = &sdx65_desc}, From d0d8cb7b94b8d23e9721cbbec5c7b00c04ae6514 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 2 May 2022 14:54:05 -0700 Subject: [PATCH 31/33] dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles Add compatibles for the SC8180X and SC8280XP platforms to the existing LLCC binding. Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220502215406.612967-2-bjorn.andersson@linaro.org --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 30fcbe2ad8a3..5ea506412b4e 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -23,6 +23,8 @@ properties: enum: - qcom,sc7180-llcc - qcom,sc7280-llcc + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc - qcom,sdm845-llcc - qcom,sm6350-llcc - qcom,sm8150-llcc From ec69dfbdc426f22a9557e5c5408d7902fe0e0144 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 2 May 2022 14:54:06 -0700 Subject: [PATCH 32/33] soc: qcom: llcc: Add sc8180x and sc8280xp configurations Add LLCC configuration data for the SC8180X and SC8280XP platforms, based on the downstream tables. Signed-off-by: Bjorn Andersson Reviewed-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/20220502215406.612967-3-bjorn.andersson@linaro.org --- drivers/soc/qcom/llcc-qcom.c | 60 ++++++++++++++++++++++++++++++ include/linux/soc/qcom/llcc-qcom.h | 2 + 2 files changed, 62 insertions(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 85ba8209b182..4b143cf7b4ce 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -130,6 +130,50 @@ static const struct llcc_slice_config sc7280_data[] = { { LLCC_MODPE, 29, 64, 1, 1, 0x3f, 0x0, 0, 0, 0, 1, 0, 0}, }; +static const struct llcc_slice_config sc8180x_data[] = { + { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1 }, + { LLCC_VIDSC0, 2, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_VIDSC1, 3, 512, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_MDMHPGRW, 7, 3072, 1, 1, 0x3ff, 0xc00, 0, 0, 0, 1, 0 }, + { LLCC_MDM, 8, 3072, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_MODHW, 9, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_GPU, 12, 5120, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1 }, + { LLCC_CMPTDMA, 15, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_VIDFW, 17, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_MDMPNG, 21, 1024, 0, 1, 0xc, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_AUDHW, 22, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_NPU, 23, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_WLHW, 24, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_MODPE, 29, 512, 1, 1, 0xc, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_APTCM, 30, 512, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, + { LLCC_WRCACHE, 31, 128, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0 }, +}; + +static const struct llcc_slice_config sc8280xp_data[] = { + { LLCC_CPUSS, 1, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 1, 0 }, + { LLCC_VIDSC0, 2, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_AUDIO, 6, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, + { LLCC_CMPT, 10, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 0, 0 }, + { LLCC_GPUHTW, 11, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_GPU, 12, 4096, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 1 }, + { LLCC_MMUHWT, 13, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_DISP, 16, 6144, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_AUDHW, 22, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_DRE, 26, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_CVP, 28, 512, 3, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_APTCM, 30, 1024, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0, 0 }, + { LLCC_WRCACHE, 31, 1024, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, + { LLCC_CVPFW, 32, 512, 1, 0, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_CPUSS1, 33, 2048, 1, 1, 0xfff, 0x0, 0, 0, 0, 1, 0, 0 }, + { LLCC_CPUHWT, 36, 512, 1, 1, 0xfff, 0x0, 0, 0, 0, 0, 1, 0 }, +}; + static const struct llcc_slice_config sdm845_data[] = { { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 }, { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, @@ -276,6 +320,20 @@ static const struct qcom_llcc_config sc7280_cfg = { .reg_offset = llcc_v1_2_reg_offset, }; +static const struct qcom_llcc_config sc8180x_cfg = { + .sct_data = sc8180x_data, + .size = ARRAY_SIZE(sc8180x_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_2_reg_offset, +}; + +static const struct qcom_llcc_config sc8280xp_cfg = { + .sct_data = sc8280xp_data, + .size = ARRAY_SIZE(sc8280xp_data), + .need_llcc_cfg = true, + .reg_offset = llcc_v1_2_reg_offset, +}; + static const struct qcom_llcc_config sdm845_cfg = { .sct_data = sdm845_data, .size = ARRAY_SIZE(sdm845_data), @@ -741,6 +799,8 @@ err: static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, { .compatible = "qcom,sc7280-llcc", .data = &sc7280_cfg }, + { .compatible = "qcom,sc8180x-llcc", .data = &sc8180x_cfg }, + { .compatible = "qcom,sc8280xp-llcc", .data = &sc8280xp_cfg }, { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, { .compatible = "qcom,sm6350-llcc", .data = &sm6350_cfg }, { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 0bc21ee58fac..9ed5384c5ca1 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -29,6 +29,8 @@ #define LLCC_AUDHW 22 #define LLCC_NPU 23 #define LLCC_WLHW 24 +#define LLCC_PIMEM 25 +#define LLCC_DRE 26 #define LLCC_CVP 28 #define LLCC_MODPE 29 #define LLCC_APTCM 30 From 28e3dc8f8cd37eedc14e97e80a7a2e33359491df Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Fri, 22 Apr 2022 13:38:06 -0400 Subject: [PATCH 33/33] soc: qcom: pdr: use static for servreg_* variables Sparse reports this repesentative issue pdr_internal.h:31:22: warning: symbol 'servreg_location_entry_ei' was not declared. Should it be static? Similar for other servreg_* Global variables should not be defined in header files. This only works because pdr_internal.h is only included by pdr_interface.c. Single file use variables should be static so add static to their storage-class specifiers. Signed-off-by: Tom Rix Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220422173806.21982-1-trix@redhat.com --- drivers/soc/qcom/pdr_internal.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/soc/qcom/pdr_internal.h b/drivers/soc/qcom/pdr_internal.h index ab9ae8cdfa54..a30422214943 100644 --- a/drivers/soc/qcom/pdr_internal.h +++ b/drivers/soc/qcom/pdr_internal.h @@ -28,7 +28,7 @@ struct servreg_location_entry { u32 instance; }; -struct qmi_elem_info servreg_location_entry_ei[] = { +static struct qmi_elem_info servreg_location_entry_ei[] = { { .data_type = QMI_STRING, .elem_len = SERVREG_NAME_LENGTH + 1, @@ -74,7 +74,7 @@ struct servreg_get_domain_list_req { u32 domain_offset; }; -struct qmi_elem_info servreg_get_domain_list_req_ei[] = { +static struct qmi_elem_info servreg_get_domain_list_req_ei[] = { { .data_type = QMI_STRING, .elem_len = SERVREG_NAME_LENGTH + 1, @@ -116,7 +116,7 @@ struct servreg_get_domain_list_resp { struct servreg_location_entry domain_list[SERVREG_DOMAIN_LIST_LENGTH]; }; -struct qmi_elem_info servreg_get_domain_list_resp_ei[] = { +static struct qmi_elem_info servreg_get_domain_list_resp_ei[] = { { .data_type = QMI_STRUCT, .elem_len = 1, @@ -199,7 +199,7 @@ struct servreg_register_listener_req { char service_path[SERVREG_NAME_LENGTH + 1]; }; -struct qmi_elem_info servreg_register_listener_req_ei[] = { +static struct qmi_elem_info servreg_register_listener_req_ei[] = { { .data_type = QMI_UNSIGNED_1_BYTE, .elem_len = 1, @@ -227,7 +227,7 @@ struct servreg_register_listener_resp { enum servreg_service_state curr_state; }; -struct qmi_elem_info servreg_register_listener_resp_ei[] = { +static struct qmi_elem_info servreg_register_listener_resp_ei[] = { { .data_type = QMI_STRUCT, .elem_len = 1, @@ -263,7 +263,7 @@ struct servreg_restart_pd_req { char service_path[SERVREG_NAME_LENGTH + 1]; }; -struct qmi_elem_info servreg_restart_pd_req_ei[] = { +static struct qmi_elem_info servreg_restart_pd_req_ei[] = { { .data_type = QMI_STRING, .elem_len = SERVREG_NAME_LENGTH + 1, @@ -280,7 +280,7 @@ struct servreg_restart_pd_resp { struct qmi_response_type_v01 resp; }; -struct qmi_elem_info servreg_restart_pd_resp_ei[] = { +static struct qmi_elem_info servreg_restart_pd_resp_ei[] = { { .data_type = QMI_STRUCT, .elem_len = 1, @@ -300,7 +300,7 @@ struct servreg_state_updated_ind { u16 transaction_id; }; -struct qmi_elem_info servreg_state_updated_ind_ei[] = { +static struct qmi_elem_info servreg_state_updated_ind_ei[] = { { .data_type = QMI_SIGNED_4_BYTE_ENUM, .elem_len = 1, @@ -336,7 +336,7 @@ struct servreg_set_ack_req { u16 transaction_id; }; -struct qmi_elem_info servreg_set_ack_req_ei[] = { +static struct qmi_elem_info servreg_set_ack_req_ei[] = { { .data_type = QMI_STRING, .elem_len = SERVREG_NAME_LENGTH + 1, @@ -362,7 +362,7 @@ struct servreg_set_ack_resp { struct qmi_response_type_v01 resp; }; -struct qmi_elem_info servreg_set_ack_resp_ei[] = { +static struct qmi_elem_info servreg_set_ack_resp_ei[] = { { .data_type = QMI_STRUCT, .elem_len = 1,