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[ARM] 3333/1: S3C2XX - add dclk and clkout clock support
Patch from Ben Dooks Add enable and set_parent calls for the dclk and clkout clocks. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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parent
a08ceff2a9
commit
3fc3e1c064
2 changed files with 95 additions and 1 deletions
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@ -45,6 +45,7 @@
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#include <asm/io.h>
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#include <asm/arch/regs-clock.h>
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#include <asm/arch/regs-gpio.h>
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#include "clock.h"
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#include "cpu.h"
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@ -285,24 +286,115 @@ static struct clk clk_p = {
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/* clocks that could be registered by external code */
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static int s3c24xx_dclk_enable(struct clk *clk, int enable)
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{
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unsigned long dclkcon = __raw_readl(S3C2410_DCLKCON);
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if (enable)
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dclkcon |= clk->ctrlbit;
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else
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dclkcon &= ~clk->ctrlbit;
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__raw_writel(dclkcon, S3C2410_DCLKCON);
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return 0;
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}
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static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
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{
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unsigned long dclkcon;
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unsigned int uclk;
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if (parent == &clk_upll)
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uclk = 1;
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else if (parent == &clk_p)
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uclk = 0;
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else
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return -EINVAL;
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clk->parent = parent;
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dclkcon = __raw_readl(S3C2410_DCLKCON);
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if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
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if (uclk)
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dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
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else
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dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
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} else {
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if (uclk)
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dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
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else
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dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
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}
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__raw_writel(dclkcon, S3C2410_DCLKCON);
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return 0;
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}
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static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
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{
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unsigned long mask;
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unsigned long source;
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/* calculate the MISCCR setting for the clock */
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if (parent == &clk_xtal)
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source = S3C2410_MISCCR_CLK0_MPLL;
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else if (parent == &clk_upll)
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source = S3C2410_MISCCR_CLK0_UPLL;
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else if (parent == &clk_f)
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source = S3C2410_MISCCR_CLK0_FCLK;
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else if (parent == &clk_p)
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source = S3C2410_MISCCR_CLK0_PCLK;
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else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
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source = S3C2410_MISCCR_CLK0_DCLK0;
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else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
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source = S3C2410_MISCCR_CLK0_DCLK0;
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else
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return -EINVAL;
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if (clk == &s3c24xx_dclk0)
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mask = S3C2410_MISCCR_CLK0_MASK;
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else {
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source <<= 4;
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mask = S3C2410_MISCCR_CLK1_MASK;
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}
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s3c2410_modify_misccr(mask, source);
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return 0;
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}
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/* external clock definitions */
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struct clk s3c24xx_dclk0 = {
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.name = "dclk0",
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.id = -1,
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.ctrlbit = S3C2410_DCLKCON_DCLK0EN,
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.enable = s3c24xx_dclk_enable,
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.set_parent = s3c24xx_dclk_setparent,
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};
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struct clk s3c24xx_dclk1 = {
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.name = "dclk1",
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.id = -1,
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.ctrlbit = S3C2410_DCLKCON_DCLK0EN,
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.enable = s3c24xx_dclk_enable,
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.set_parent = s3c24xx_dclk_setparent,
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};
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struct clk s3c24xx_clkout0 = {
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.name = "clkout0",
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.id = -1,
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.set_parent = s3c24xx_clkout_setparent,
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};
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struct clk s3c24xx_clkout1 = {
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.name = "clkout1",
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.id = -1,
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.set_parent = s3c24xx_clkout_setparent,
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};
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struct clk s3c24xx_uclk = {
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@ -423,7 +515,7 @@ int s3c24xx_register_clock(struct clk *clk)
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/* if this is a standard clock, set the usage state */
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if (clk->ctrlbit) {
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if (clk->ctrlbit && clk->enable == s3c24xx_clkcon_enable) {
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unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
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clk->usage = (clkcon & clk->ctrlbit) ? 1 : 0;
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@ -979,6 +979,7 @@
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#define S3C2410_MISCCR_CLK0_HCLK (3<<4)
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#define S3C2410_MISCCR_CLK0_PCLK (4<<4)
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#define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
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#define S3C2410_MISCCR_CLK0_MASK (7<<4)
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#define S3C2410_MISCCR_CLK1_MPLL (0<<8)
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#define S3C2410_MISCCR_CLK1_UPLL (1<<8)
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@ -986,6 +987,7 @@
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#define S3C2410_MISCCR_CLK1_HCLK (3<<8)
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#define S3C2410_MISCCR_CLK1_PCLK (4<<8)
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#define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
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#define S3C2410_MISCCR_CLK1_MASK (7<<8)
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#define S3C2410_MISCCR_USBSUSPND0 (1<<12)
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#define S3C2410_MISCCR_USBSUSPND1 (1<<13)
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