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clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME} macros, we can reference parents locally via pointers to struct clk_hw or DT clock-names. Convert existing CLK_FIXED_FACTOR definitions to either the _HW or _FW_NAME variant based on whether the parent clock is internal or external to the CCU. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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1 changed files with 29 additions and 17 deletions
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@ -952,25 +952,37 @@ static struct ccu_common *sun8i_r40_ccu_clks[] = {
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};
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/* Fixed Factor clocks */
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static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0);
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static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
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static const struct clk_hw *clk_parent_pll_audio[] = {
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&pll_audio_base_clk.common.hw
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};
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/* We hardcode the divider to 4 for now */
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static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
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"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
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static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
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"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
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static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
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"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
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static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
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"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
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static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
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"pll-periph0", 1, 2, 0);
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static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x",
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"pll-periph1", 1, 2, 0);
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static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
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"pll-video0", 1, 2, 0);
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static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
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"pll-video1", 1, 2, 0);
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static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
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clk_parent_pll_audio,
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4, 1, CLK_SET_RATE_PARENT);
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static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
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clk_parent_pll_audio,
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2, 1, CLK_SET_RATE_PARENT);
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static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
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clk_parent_pll_audio,
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1, 1, CLK_SET_RATE_PARENT);
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static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
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clk_parent_pll_audio,
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1, 2, CLK_SET_RATE_PARENT);
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static CLK_FIXED_FACTOR_HW(pll_periph0_2x_clk, "pll-periph0-2x",
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&pll_periph0_clk.common.hw,
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1, 2, 0);
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static CLK_FIXED_FACTOR_HW(pll_periph1_2x_clk, "pll-periph1-2x",
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&pll_periph1_clk.common.hw,
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1, 2, 0);
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static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
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&pll_video0_clk.common.hw,
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1, 2, 0);
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static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
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&pll_video1_clk.common.hw,
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1, 2, 0);
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static struct clk_hw_onecell_data sun8i_r40_hw_clks = {
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.hws = {
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