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drm/i915/tgl: Add gmbus gpio pin to port mapping
Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are mapped to TC ports. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-18-lucas.demarchi@intel.com
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parent
30fcc338bc
commit
3fd53262f0
3 changed files with 23 additions and 3 deletions
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@ -45,6 +45,8 @@ enum i915_gpio {
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GPIOK,
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GPIOL,
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GPIOM,
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GPION,
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GPIOO,
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};
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/*
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@ -94,11 +94,25 @@ static const struct gmbus_pin gmbus_pins_mcc[] = {
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[GMBUS_PIN_9_TC1_ICP] = { "dpc", GPIOJ },
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};
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static const struct gmbus_pin gmbus_pins_tgp[] = {
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[GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
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[GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
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[GMBUS_PIN_3_BXT] = { "dpc", GPIOD },
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[GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
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[GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
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[GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
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[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
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[GMBUS_PIN_13_TC5_TGP] = { "tc5", GPION },
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[GMBUS_PIN_14_TC6_TGP] = { "tc6", GPIOO },
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};
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/* pin is expected to be valid */
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static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
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unsigned int pin)
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{
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if (HAS_PCH_MCC(dev_priv))
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if (HAS_PCH_TGP(dev_priv))
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return &gmbus_pins_tgp[pin];
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else if (HAS_PCH_MCC(dev_priv))
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return &gmbus_pins_mcc[pin];
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else if (HAS_PCH_ICP(dev_priv))
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return &gmbus_pins_icp[pin];
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@ -119,7 +133,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
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{
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unsigned int size;
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if (HAS_PCH_MCC(dev_priv))
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if (HAS_PCH_TGP(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_tgp);
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else if (HAS_PCH_MCC(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_mcc);
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else if (HAS_PCH_ICP(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_icp);
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@ -3254,8 +3254,10 @@ enum i915_power_well_id {
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#define GMBUS_PIN_10_TC2_ICP 10
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#define GMBUS_PIN_11_TC3_ICP 11
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#define GMBUS_PIN_12_TC4_ICP 12
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#define GMBUS_PIN_13_TC5_TGP 13
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#define GMBUS_PIN_14_TC6_TGP 14
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#define GMBUS_NUM_PINS 13 /* including 0 */
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#define GMBUS_NUM_PINS 15 /* including 0 */
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#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
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#define GMBUS_SW_CLR_INT (1 << 31)
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#define GMBUS_SW_RDY (1 << 30)
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