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perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints
SPR M3UPI have the exact same event constraints as ICX, so add the
constraints.
Fixes: 2a8e51eae7
("perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1629991963-102621-8-git-send-email-kan.liang@linux.intel.com
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@ -5776,6 +5776,7 @@ static struct intel_uncore_type spr_uncore_upi = {
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static struct intel_uncore_type spr_uncore_m3upi = {
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static struct intel_uncore_type spr_uncore_m3upi = {
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SPR_UNCORE_PCI_COMMON_FORMAT(),
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SPR_UNCORE_PCI_COMMON_FORMAT(),
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.name = "m3upi",
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.name = "m3upi",
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.constraints = icx_uncore_m3upi_constraints,
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};
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};
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static struct intel_uncore_type spr_uncore_mdf = {
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static struct intel_uncore_type spr_uncore_mdf = {
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