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[PATCH] shpchp: Cleanup SHPC commands
This patch cleans up the code related to issuing SHPC commands. This patch has no functional changes. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Cc: Kristen Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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c4cecc1937
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1 changed files with 48 additions and 50 deletions
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@ -147,39 +147,37 @@
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#define CON_PFAULT_SERR_MASK (1 << 30)
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#define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21)
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/* SHPC 'write' operations/commands */
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/* Slot operation - 0x00h to 0x3Fh */
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#define NO_CHANGE 0x00
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/* Slot state - Bits 0 & 1 of controller command register */
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#define SET_SLOT_PWR 0x01
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#define SET_SLOT_ENABLE 0x02
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#define SET_SLOT_DISABLE 0x03
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/* Power indicator state - Bits 2 & 3 of controller command register*/
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#define SET_PWR_ON 0x04
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#define SET_PWR_BLINK 0x08
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#define SET_PWR_OFF 0x0C
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/* Attention indicator state - Bits 4 & 5 of controller command register*/
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#define SET_ATTN_ON 0x010
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#define SET_ATTN_BLINK 0x020
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#define SET_ATTN_OFF 0x030
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/* Set bus speed/mode A - 0x40h to 0x47h */
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#define SETA_PCI_33MHZ 0x40
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/*
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* SHPC Command Code definitnions
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*
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* Slot Operation 00h - 3Fh
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* Set Bus Segment Speed/Mode A 40h - 47h
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* Power-Only All Slots 48h
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* Enable All Slots 49h
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* Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh
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* Reserved Command Codes 60h - BFh
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* Vendor Specific Commands C0h - FFh
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*/
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#define SET_SLOT_PWR 0x01 /* Slot Operation */
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#define SET_SLOT_ENABLE 0x02
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#define SET_SLOT_DISABLE 0x03
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#define SET_PWR_ON 0x04
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#define SET_PWR_BLINK 0x08
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#define SET_PWR_OFF 0x0c
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#define SET_ATTN_ON 0x10
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#define SET_ATTN_BLINK 0x20
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#define SET_ATTN_OFF 0x30
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#define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
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#define SETA_PCI_66MHZ 0x41
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#define SETA_PCIX_66MHZ 0x42
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#define SETA_PCIX_100MHZ 0x43
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#define SETA_PCIX_133MHZ 0x44
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#define RESERV_1 0x45
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#define RESERV_2 0x46
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#define RESERV_3 0x47
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/* Set bus speed/mode B - 0x50h to 0x5fh */
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#define SETB_PCI_33MHZ 0x50
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#define SETA_RESERVED1 0x45
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#define SETA_RESERVED2 0x46
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#define SETA_RESERVED3 0x47
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#define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
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#define SET_ENABLE_ALL 0x49 /* Enable All Slots */
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#define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
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#define SETB_PCI_66MHZ 0x51
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#define SETB_PCIX_66MHZ_PM 0x52
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#define SETB_PCIX_100MHZ_PM 0x53
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@ -193,23 +191,21 @@
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#define SETB_PCIX_66MHZ_533 0x5b
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#define SETB_PCIX_100MHZ_533 0x5c
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#define SETB_PCIX_133MHZ_533 0x5d
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#define SETB_RESERVED1 0x5e
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#define SETB_RESERVED2 0x5f
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/* Power-on all slots - 0x48h */
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#define SET_PWR_ON_ALL 0x48
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/* Enable all slots - 0x49h */
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#define SET_ENABLE_ALL 0x49
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/* SHPC controller command error code */
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/*
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* SHPC controller command error code
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*/
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#define SWITCH_OPEN 0x1
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#define INVALID_CMD 0x2
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#define INVALID_SPEED_MODE 0x4
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/* For accessing SHPC Working Register Set */
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/*
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* For accessing SHPC Working Register Set via PCI Configuration Space
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*/
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#define DWORD_SELECT 0x2
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#define DWORD_DATA 0x4
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#define BASE_OFFSET 0x0
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/* Field Offset in Logical Slot Register - byte boundary */
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#define SLOT_EVENT_LATCH 0x2
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@ -630,13 +626,13 @@ static int hpc_set_attention_status(struct slot *slot, u8 value)
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switch (value) {
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case 0 :
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slot_cmd = 0x30; /* OFF */
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slot_cmd = SET_ATTN_OFF; /* OFF */
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break;
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case 1:
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slot_cmd = 0x10; /* ON */
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slot_cmd = SET_ATTN_ON; /* ON */
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break;
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case 2:
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slot_cmd = 0x20; /* BLINK */
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slot_cmd = SET_ATTN_BLINK; /* BLINK */
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break;
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default:
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return -1;
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@ -648,17 +644,17 @@ static int hpc_set_attention_status(struct slot *slot, u8 value)
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static void hpc_set_green_led_on(struct slot *slot)
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{
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shpc_write_cmd(slot, slot->hp_slot, 0x04);
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shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
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}
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static void hpc_set_green_led_off(struct slot *slot)
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{
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shpc_write_cmd(slot, slot->hp_slot, 0x0c);
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shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
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}
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static void hpc_set_green_led_blink(struct slot *slot)
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{
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shpc_write_cmd(slot, slot->hp_slot, 0x08);
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shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
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}
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int shpc_get_ctlr_slot_config(struct controller *ctrl,
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@ -769,7 +765,7 @@ static int hpc_power_on_slot(struct slot * slot)
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DBG_ENTER_ROUTINE
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retval = shpc_write_cmd(slot, slot->hp_slot, 0x01);
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retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
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if (retval) {
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err("%s: Write command failed!\n", __FUNCTION__);
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return retval;
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@ -786,8 +782,9 @@ static int hpc_slot_enable(struct slot * slot)
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DBG_ENTER_ROUTINE
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/* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
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retval = shpc_write_cmd(slot, slot->hp_slot, 0x3a);
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/* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
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retval = shpc_write_cmd(slot, slot->hp_slot,
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SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
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if (retval) {
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err("%s: Write command failed!\n", __FUNCTION__);
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return retval;
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@ -803,8 +800,9 @@ static int hpc_slot_disable(struct slot * slot)
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DBG_ENTER_ROUTINE
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/* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */
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retval = shpc_write_cmd(slot, slot->hp_slot, 0x1f);
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/* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
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retval = shpc_write_cmd(slot, slot->hp_slot,
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SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
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if (retval) {
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err("%s: Write command failed!\n", __FUNCTION__);
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return retval;
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