dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
Convert Renesas PCI bridge bindings documentation to json-schema. Link: https://lore.kernel.org/r/20220520094155.313784-2-herve.codina@bootlin.com Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
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Herve Codina
Bjorn Helgaas
parent
f2906aa863
commit
409ae431b9
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Renesas AHB to PCI bridge
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-------------------------
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This is the bridge used internally to connect the USB controllers to the
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AHB. There is one bridge instance per USB port connected to the internal
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OHCI and EHCI controllers.
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Required properties:
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- compatible: "renesas,pci-r8a7742" for the R8A7742 SoC;
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"renesas,pci-r8a7743" for the R8A7743 SoC;
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"renesas,pci-r8a7744" for the R8A7744 SoC;
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"renesas,pci-r8a7745" for the R8A7745 SoC;
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"renesas,pci-r8a7790" for the R8A7790 SoC;
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"renesas,pci-r8a7791" for the R8A7791 SoC;
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"renesas,pci-r8a7793" for the R8A7793 SoC;
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"renesas,pci-r8a7794" for the R8A7794 SoC;
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"renesas,pci-rcar-gen2" for a generic R-Car Gen2 or
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RZ/G1 compatible device.
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When compatible with the generic version, nodes must list the
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SoC-specific version corresponding to the platform first
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followed by the generic version.
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- reg: A list of physical regions to access the device: the first is
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the operational registers for the OHCI/EHCI controllers and the
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second is for the bridge configuration and control registers.
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- interrupts: interrupt for the device.
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- clocks: The reference to the device clock.
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- bus-range: The PCI bus number range; as this is a single bus, the range
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should be specified as the same value twice.
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- #address-cells: must be 3.
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- #size-cells: must be 2.
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- #interrupt-cells: must be 1.
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- interrupt-map: standard property used to define the mapping of the PCI
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interrupts to the GIC interrupts.
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- interrupt-map-mask: standard property that helps to define the interrupt
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mapping.
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Optional properties:
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- dma-ranges: a single range for the inbound memory region. If not supplied,
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defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the
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allowed combinations of address and size.
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Example SoC configuration:
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pci0: pci@ee090000 {
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compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
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clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
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reg = <0x0 0xee090000 0x0 0xc00>,
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<0x0 0xee080000 0x0 0x1100>;
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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bus-range = <0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
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interrupt-map-mask = <0xff00 0 0 0x7>;
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interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
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0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
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0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
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usb@1,0 {
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reg = <0x800 0 0 0 0>;
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phys = <&usb0 0>;
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phy-names = "usb";
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};
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usb@2,0 {
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reg = <0x1000 0 0 0 0>;
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phys = <&usb0 0>;
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phy-names = "usb";
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};
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};
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Example board setup:
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&pci0 {
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status = "okay";
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pinctrl-0 = <&usb0_pins>;
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pinctrl-names = "default";
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};
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@ -0,0 +1,156 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas AHB to PCI bridge
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maintainers:
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- Marek Vasut <marek.vasut+renesas@gmail.com>
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- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
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description: |
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This is the bridge used internally to connect the USB controllers to the
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AHB. There is one bridge instance per USB port connected to the internal
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OHCI and EHCI controllers.
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allOf:
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- $ref: /schemas/pci/pci-bus.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- renesas,pci-r8a7742 # RZ/G1H
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- renesas,pci-r8a7743 # RZ/G1M
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- renesas,pci-r8a7744 # RZ/G1N
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- renesas,pci-r8a7745 # RZ/G1E
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- renesas,pci-r8a7790 # R-Car H2
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- renesas,pci-r8a7791 # R-Car M2-W
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- renesas,pci-r8a7793 # R-Car M2-N
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- renesas,pci-r8a7794 # R-Car E2
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- const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
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reg:
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items:
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- description: Operational registers for the OHCI/EHCI controllers.
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- description: Bridge configuration and control registers.
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Device clock
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clock-names:
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items:
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- const: pclk
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resets:
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maxItems: 1
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power-domains:
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maxItems: 1
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bus-range:
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description: |
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The PCI bus number range; as this is a single bus, the range
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should be specified as the same value twice.
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dma-ranges:
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description: |
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A single range for the inbound memory region. If not supplied,
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defaults to 1GiB at 0x40000000. Note there are hardware restrictions on
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the allowed combinations of address and size.
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maxItems: 1
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patternProperties:
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'usb@[0-1],0':
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type: object
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description:
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This a USB controller PCI device
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properties:
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reg:
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description:
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Identify the correct bus, device and function number in the
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form <bdf 0 0 0 0>.
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items:
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minItems: 5
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maxItems: 5
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phys:
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description:
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Reference to the USB phy
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maxItems: 1
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phy-names:
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maxItems: 1
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required:
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- reg
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- phys
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- phy-names
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-map
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- interrupt-map-mask
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- clocks
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- resets
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- power-domains
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- bus-range
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- "#address-cells"
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- "#size-cells"
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- "#interrupt-cells"
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/r8a7790-cpg-mssr.h>
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#include <dt-bindings/power/r8a7790-sysc.h>
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pci@ee090000 {
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compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
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device_type = "pci";
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reg = <0xee090000 0xc00>,
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<0xee080000 0x1100>;
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clocks = <&cpg CPG_MOD 703>;
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power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
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resets = <&cpg 703>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges = <0x02000000 0 0xee080000 0xee080000 0 0x00010000>;
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dma-ranges = <0x42000000 0 0x40000000 0x40000000 0 0x40000000>;
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interrupt-map-mask = <0xf800 0 0 0x7>;
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interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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usb@1,0 {
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reg = <0x800 0 0 0 0>;
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phys = <&usb0 0>;
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phy-names = "usb";
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};
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usb@2,0 {
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reg = <0x1000 0 0 0 0>;
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phys = <&usb0 0>;
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phy-names = "usb";
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};
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};
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