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Code Issues Releases Wiki Activity

drm/i915: Move load time gem_load_init earlier 

The only steps requiring device access is the fence and swizzling
initialization, so split these out keeping them in their current place
and move the rest of init steps earlier.

v2-v3:
- unchanged
v4:
- move call to i915_gem_detect_bit_6_swizzle() to
  i915_gem_load_init_fences() and preserve the original order of
  the detection of HW fence capailities wrt. swizzling (Chris)

CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/1458132843-21860-1-git-send-email-imre.deak@intel.com
This commit is contained in:
Imre Deak 2016-03-16 14:54:03 +02:00
parent 13c8f4c8cd
commit 40ae4e1661
3 changed files with 32 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
drivers/gpu/drm/i915/i915_dma.c
View File

@ -1031,6 +1031,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
intel_init_display_hooks(dev_priv);
intel_init_clock_gating_hooks(dev_priv);
intel_init_audio_hooks(dev_priv);
i915_gem_load_init(dev);
intel_runtime_pm_get(dev_priv);
@ -1114,7 +1115,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
intel_opregion_setup(dev);
i915_gem_load_init(dev);
i915_gem_load_init_fences(dev_priv);
i915_gem_shrinker_init(dev_priv);
/* On the 945G/GM, the chipset reports the MSI capability on the
@ -1136,7 +1138,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
if (INTEL_INFO(dev)->num_pipes) {
ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
if (ret)
goto out_gem_unload;
goto out_cleanup_shrinker;
}
ret = i915_load_modeset_init(dev);
@ -1174,7 +1176,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
out_power_well:
intel_power_domains_fini(dev_priv);
drm_vblank_cleanup(dev);
out_gem_unload:
out_cleanup_shrinker:
i915_gem_shrinker_cleanup(dev_priv);
if (dev->pdev->msi_enabled)
@ -1190,9 +1192,9 @@ out_uncore_fini:
i915_mmio_cleanup(dev);
put_bridge:
pci_dev_put(dev_priv->bridge_dev);
i915_gem_load_cleanup(dev);
out_runtime_pm_put:
intel_runtime_pm_put(dev_priv);
i915_gem_load_cleanup(dev);
i915_workqueues_cleanup(dev_priv);
out_free_priv:
kfree(dev_priv);
@ -1277,8 +1279,8 @@ int i915_driver_unload(struct drm_device *dev)
intel_uncore_fini(dev);
i915_mmio_cleanup(dev);
i915_gem_load_cleanup(dev);
pci_dev_put(dev_priv->bridge_dev);
i915_gem_load_cleanup(dev);
i915_workqueues_cleanup(dev_priv);
kfree(dev_priv);

1
drivers/gpu/drm/i915/i915_drv.h
View File

@ -2859,6 +2859,7 @@ int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
void i915_gem_load_init(struct drm_device *dev);
void i915_gem_load_cleanup(struct drm_device *dev);
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
void *i915_gem_object_alloc(struct drm_device *dev);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
void i915_gem_object_init(struct drm_i915_gem_object *obj,

38
drivers/gpu/drm/i915/i915_gem.c
View File

@ -5028,6 +5028,30 @@ init_engine_lists(struct intel_engine_cs *engine)
INIT_LIST_HEAD(&engine->request_list);
}
void
i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
{
struct drm_device *dev = dev_priv->dev;
if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
!IS_CHERRYVIEW(dev_priv))
dev_priv->num_fence_regs = 32;
else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
IS_I945GM(dev_priv) || IS_G33(dev_priv))
dev_priv->num_fence_regs = 16;
else
dev_priv->num_fence_regs = 8;
if (intel_vgpu_active(dev))
dev_priv->num_fence_regs =
I915_READ(vgtif_reg(avail_rs.fence_num));
/* Initialize fence registers to zero */
i915_gem_restore_fences(dev);
i915_gem_detect_bit_6_swizzle(dev);
}
void
i915_gem_load_init(struct drm_device *dev)
{
@ -5067,17 +5091,6 @@ i915_gem_load_init(struct drm_device *dev)
dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev))
dev_priv->num_fence_regs = 32;
else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
dev_priv->num_fence_regs = 16;
else
dev_priv->num_fence_regs = 8;
if (intel_vgpu_active(dev))
dev_priv->num_fence_regs =
I915_READ(vgtif_reg(avail_rs.fence_num));
/*
* Set initial sequence number for requests.
* Using this number allows the wraparound to happen early,
@ -5086,11 +5099,8 @@ i915_gem_load_init(struct drm_device *dev)
dev_priv->next_seqno = ((u32)~0 - 0x1100);
dev_priv->last_seqno = ((u32)~0 - 0x1101);
/* Initialize fence registers to zero */
INIT_LIST_HEAD(&dev_priv->mm.fence_list);
i915_gem_restore_fences(dev);
i915_gem_detect_bit_6_swizzle(dev);
init_waitqueue_head(&dev_priv->pending_flip_queue);
dev_priv->mm.interruptible = true;