MIPS: Alchemy: Rewrite ethernet platform setup
Rewrite ethernet setup to use runtime cpu detection, and also clean up the ethernet base address mess as far as possible. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Florian Fainelli <florian@openwrt.org> Cc: Wolfgang Grandegger <wg@grandegger.com> Patchwork: https://patchwork.linux-mips.org/patch/2353/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org
This commit is contained in:
Manuel Lauss
Ralf Baechle
parent
80130204b4
commit
40d8bc2817
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@ -13,9 +13,10 @@
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#include <linux/dma-mapping.h>
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#include <linux/etherdevice.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <asm/mach-au1x00/au1xxx.h>
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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@ -372,15 +373,16 @@ static struct platform_device pbdb_smbus_device = {
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#endif
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/* Macro to help defining the Ethernet MAC resources */
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#define MAC_RES_COUNT 3 /* MAC regs base, MAC enable reg, MAC INT */
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#define MAC_RES(_base, _enable, _irq) \
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{ \
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.start = CPHYSADDR(_base), \
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.end = CPHYSADDR(_base + 0xffff), \
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.start = _base, \
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.end = _base + 0xffff, \
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.flags = IORESOURCE_MEM, \
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}, \
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{ \
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.start = CPHYSADDR(_enable), \
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.end = CPHYSADDR(_enable + 0x3), \
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.start = _enable, \
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.end = _enable + 0x3, \
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.flags = IORESOURCE_MEM, \
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}, \
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{ \
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@ -389,19 +391,29 @@ static struct platform_device pbdb_smbus_device = {
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.flags = IORESOURCE_IRQ \
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}
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static struct resource au1xxx_eth0_resources[] = {
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#if defined(CONFIG_SOC_AU1000)
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MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT),
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#elif defined(CONFIG_SOC_AU1100)
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MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT),
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#elif defined(CONFIG_SOC_AU1550)
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MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT),
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#elif defined(CONFIG_SOC_AU1500)
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MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT),
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#endif
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static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = {
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[ALCHEMY_CPU_AU1000] = {
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MAC_RES(AU1000_MAC0_PHYS_ADDR,
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AU1000_MACEN_PHYS_ADDR,
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AU1000_MAC0_DMA_INT)
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},
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[ALCHEMY_CPU_AU1500] = {
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MAC_RES(AU1500_MAC0_PHYS_ADDR,
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AU1500_MACEN_PHYS_ADDR,
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AU1500_MAC0_DMA_INT)
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},
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[ALCHEMY_CPU_AU1100] = {
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MAC_RES(AU1000_MAC0_PHYS_ADDR,
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AU1000_MACEN_PHYS_ADDR,
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AU1100_MAC0_DMA_INT)
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},
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[ALCHEMY_CPU_AU1550] = {
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MAC_RES(AU1000_MAC0_PHYS_ADDR,
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AU1000_MACEN_PHYS_ADDR,
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AU1550_MAC0_DMA_INT)
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},
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};
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static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
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.phy1_search_mac0 = 1,
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};
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@ -409,20 +421,26 @@ static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
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static struct platform_device au1xxx_eth0_device = {
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.name = "au1000-eth",
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.id = 0,
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.num_resources = ARRAY_SIZE(au1xxx_eth0_resources),
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.resource = au1xxx_eth0_resources,
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.num_resources = MAC_RES_COUNT,
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.dev.platform_data = &au1xxx_eth0_platform_data,
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};
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#ifndef CONFIG_SOC_AU1100
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static struct resource au1xxx_eth1_resources[] = {
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#if defined(CONFIG_SOC_AU1000)
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MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT),
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#elif defined(CONFIG_SOC_AU1550)
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MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT),
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#elif defined(CONFIG_SOC_AU1500)
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MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT),
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#endif
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static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = {
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[ALCHEMY_CPU_AU1000] = {
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MAC_RES(AU1000_MAC1_PHYS_ADDR,
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AU1000_MACEN_PHYS_ADDR + 4,
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AU1000_MAC1_DMA_INT)
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},
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[ALCHEMY_CPU_AU1500] = {
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MAC_RES(AU1500_MAC1_PHYS_ADDR,
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AU1500_MACEN_PHYS_ADDR + 4,
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AU1500_MAC1_DMA_INT)
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},
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[ALCHEMY_CPU_AU1550] = {
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MAC_RES(AU1000_MAC1_PHYS_ADDR,
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AU1000_MACEN_PHYS_ADDR + 4,
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AU1550_MAC1_DMA_INT)
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},
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};
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static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
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@ -432,11 +450,9 @@ static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
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static struct platform_device au1xxx_eth1_device = {
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.name = "au1000-eth",
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.id = 1,
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.num_resources = ARRAY_SIZE(au1xxx_eth1_resources),
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.resource = au1xxx_eth1_resources,
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.num_resources = MAC_RES_COUNT,
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.dev.platform_data = &au1xxx_eth1_platform_data,
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};
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#endif
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void __init au1xxx_override_eth_cfg(unsigned int port,
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struct au1000_eth_platform_data *eth_data)
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@ -447,11 +463,62 @@ void __init au1xxx_override_eth_cfg(unsigned int port,
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if (port == 0)
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memcpy(&au1xxx_eth0_platform_data, eth_data,
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sizeof(struct au1000_eth_platform_data));
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#ifndef CONFIG_SOC_AU1100
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else
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memcpy(&au1xxx_eth1_platform_data, eth_data,
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sizeof(struct au1000_eth_platform_data));
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#endif
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}
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static void __init alchemy_setup_macs(int ctype)
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{
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int ret, i;
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unsigned char ethaddr[6];
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struct resource *macres;
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/* Handle 1st MAC */
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if (alchemy_get_macs(ctype) < 1)
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return;
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macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
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if (!macres) {
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printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n");
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return;
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}
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memcpy(macres, au1xxx_eth0_resources[ctype],
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sizeof(struct resource) * MAC_RES_COUNT);
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au1xxx_eth0_device.resource = macres;
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i = prom_get_ethernet_addr(ethaddr);
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if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
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memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
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ret = platform_device_register(&au1xxx_eth0_device);
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if (!ret)
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printk(KERN_INFO "Alchemy: failed to register MAC0\n");
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/* Handle 2nd MAC */
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if (alchemy_get_macs(ctype) < 2)
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return;
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macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
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if (!macres) {
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printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n");
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return;
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}
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memcpy(macres, au1xxx_eth1_resources[ctype],
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sizeof(struct resource) * MAC_RES_COUNT);
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au1xxx_eth1_device.resource = macres;
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ethaddr[5] += 1; /* next addr for 2nd MAC */
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if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
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memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
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/* Register second MAC if enabled in pinfunc */
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if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) {
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ret = platform_device_register(&au1xxx_eth1_device);
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if (ret)
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printk(KERN_INFO "Alchemy: failed to register MAC1\n");
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}
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}
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static struct platform_device *au1xxx_platform_devices[] __initdata = {
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@ -472,33 +539,17 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
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#ifdef SMBUS_PSC_BASE
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&pbdb_smbus_device,
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#endif
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&au1xxx_eth0_device,
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};
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static int __init au1xxx_platform_init(void)
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{
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int err, i, ctype = alchemy_get_cputype();
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unsigned char ethaddr[6];
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int err, ctype = alchemy_get_cputype();
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alchemy_setup_uarts(ctype);
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/* use firmware-provided mac addr if available and necessary */
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i = prom_get_ethernet_addr(ethaddr);
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if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
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memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
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alchemy_setup_macs(ctype);
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err = platform_add_devices(au1xxx_platform_devices,
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ARRAY_SIZE(au1xxx_platform_devices));
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#ifndef CONFIG_SOC_AU1100
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ethaddr[5] += 1; /* next addr for 2nd MAC */
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if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
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memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
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/* Register second MAC if enabled in pinfunc */
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if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
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err = platform_device_register(&au1xxx_eth1_device);
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#endif
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return err;
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}
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@ -219,6 +219,20 @@ static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
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wmb();
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}
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/* return number of ethernet MACs on a given cputype */
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static inline int alchemy_get_macs(int type)
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{
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switch (type) {
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case ALCHEMY_CPU_AU1000:
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case ALCHEMY_CPU_AU1500:
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case ALCHEMY_CPU_AU1550:
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return 2;
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case ALCHEMY_CPU_AU1100:
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return 1;
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}
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return 0;
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}
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/* arch/mips/au1000/common/clocks.c */
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extern void set_au1x00_speed(unsigned int new_freq);
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extern unsigned int get_au1x00_speed(void);
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@ -673,6 +687,12 @@ enum soc_au1200_ints {
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*/
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#define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
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#define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
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#define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
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#define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
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#define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
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#define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
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#define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
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#define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
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#define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
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#define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
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@ -680,6 +700,8 @@ enum soc_au1200_ints {
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#define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
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#define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */
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#define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */
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#define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
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#define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
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#ifdef CONFIG_SOC_AU1000
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@ -697,11 +719,6 @@ enum soc_au1200_ints {
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#define USBH_PHYS_ADDR 0x10100000
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#define USBD_PHYS_ADDR 0x10200000
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#define IRDA_PHYS_ADDR 0x10300000
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#define MAC0_PHYS_ADDR 0x10500000
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#define MAC1_PHYS_ADDR 0x10510000
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#define MACEN_PHYS_ADDR 0x10520000
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#define MACDMA0_PHYS_ADDR 0x14004000
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#define MACDMA1_PHYS_ADDR 0x14004200
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#define I2S_PHYS_ADDR 0x11000000
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#define SSI0_PHYS_ADDR 0x11600000
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#define SSI1_PHYS_ADDR 0x11680000
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@ -728,11 +745,6 @@ enum soc_au1200_ints {
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#define USBH_PHYS_ADDR 0x10100000
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#define USBD_PHYS_ADDR 0x10200000
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#define PCI_PHYS_ADDR 0x14005000
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#define MAC0_PHYS_ADDR 0x11500000
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#define MAC1_PHYS_ADDR 0x11510000
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#define MACEN_PHYS_ADDR 0x11520000
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#define MACDMA0_PHYS_ADDR 0x14004000
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#define MACDMA1_PHYS_ADDR 0x14004200
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#define I2S_PHYS_ADDR 0x11000000
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#define GPIO2_PHYS_ADDR 0x11700000
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#define SYS_PHYS_ADDR 0x11900000
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@ -764,10 +776,6 @@ enum soc_au1200_ints {
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#define USBH_PHYS_ADDR 0x10100000
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#define USBD_PHYS_ADDR 0x10200000
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#define IRDA_PHYS_ADDR 0x10300000
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#define MAC0_PHYS_ADDR 0x10500000
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#define MACEN_PHYS_ADDR 0x10520000
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#define MACDMA0_PHYS_ADDR 0x14004000
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#define MACDMA1_PHYS_ADDR 0x14004200
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#define I2S_PHYS_ADDR 0x11000000
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#define SSI0_PHYS_ADDR 0x11600000
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#define SSI1_PHYS_ADDR 0x11680000
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@ -787,11 +795,6 @@ enum soc_au1200_ints {
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#define USBH_PHYS_ADDR 0x14020000
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#define USBD_PHYS_ADDR 0x10200000
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#define PCI_PHYS_ADDR 0x14005000
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#define MAC0_PHYS_ADDR 0x10500000
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#define MAC1_PHYS_ADDR 0x10510000
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#define MACEN_PHYS_ADDR 0x10520000
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#define MACDMA0_PHYS_ADDR 0x14004000
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#define MACDMA1_PHYS_ADDR 0x14004200
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#define GPIO2_PHYS_ADDR 0x11700000
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#define SYS_PHYS_ADDR 0x11900000
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#define PE_PHYS_ADDR 0x14008000
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@ -870,12 +873,6 @@ enum soc_au1200_ints {
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#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
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#define USB_HOST_CONFIG 0xB017FFFC
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#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
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#define AU1000_ETH0_BASE 0xB0500000
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#define AU1000_ETH1_BASE 0xB0510000
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#define AU1000_MAC0_ENABLE 0xB0520000
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#define AU1000_MAC1_ENABLE 0xB0520004
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#define NUM_ETH_INTERFACES 2
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#endif /* CONFIG_SOC_AU1000 */
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/* Au1500 */
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@ -887,12 +884,6 @@ enum soc_au1200_ints {
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#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
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#define USB_HOST_CONFIG 0xB017fffc
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#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
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#define AU1500_ETH0_BASE 0xB1500000
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#define AU1500_ETH1_BASE 0xB1510000
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#define AU1500_MAC0_ENABLE 0xB1520000
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#define AU1500_MAC1_ENABLE 0xB1520004
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#define NUM_ETH_INTERFACES 2
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#endif /* CONFIG_SOC_AU1500 */
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/* Au1100 */
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@ -904,10 +895,6 @@ enum soc_au1200_ints {
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#define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
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#define USB_HOST_CONFIG 0xB017FFFC
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#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
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#define AU1100_ETH0_BASE 0xB0500000
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#define AU1100_MAC0_ENABLE 0xB0520000
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#define NUM_ETH_INTERFACES 1
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#endif /* CONFIG_SOC_AU1100 */
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#ifdef CONFIG_SOC_AU1550
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@ -917,12 +904,6 @@ enum soc_au1200_ints {
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#define USB_OHCI_LEN 0x00060000
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#define USB_HOST_CONFIG 0xB4027ffc
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#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
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#define AU1550_ETH0_BASE 0xB0500000
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#define AU1550_ETH1_BASE 0xB0510000
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#define AU1550_MAC0_ENABLE 0xB0520000
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#define AU1550_MAC1_ENABLE 0xB0520004
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#define NUM_ETH_INTERFACES 2
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#endif /* CONFIG_SOC_AU1550 */
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