mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 17:30:02 +00:00
clk: meson: meson8b: remove compatibility code for old .dtbs
The XTAL clock is provided via .dts since Linux 5.6. Remove compatibility code for .dtbs which are older than that. The switch to the HHI syscon has been done with Linux 5.1. Also remove any code needed to support .dtbs that have not switched to the HHI syscon yet. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201221183624.932649-2-martin.blumenstingl@googlemail.com
This commit is contained in:
parent
ccdc1f0836
commit
40e977400d
1 changed files with 5 additions and 40 deletions
|
@ -52,15 +52,6 @@ static const struct pll_params_table sys_pll_params_table[] = {
|
||||||
{ /* sentinel */ },
|
{ /* sentinel */ },
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_fixed_rate meson8b_xtal = {
|
|
||||||
.fixed_rate = 24000000,
|
|
||||||
.hw.init = &(struct clk_init_data){
|
|
||||||
.name = "xtal",
|
|
||||||
.num_parents = 0,
|
|
||||||
.ops = &clk_fixed_rate_ops,
|
|
||||||
},
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct clk_regmap meson8b_fixed_pll_dco = {
|
static struct clk_regmap meson8b_fixed_pll_dco = {
|
||||||
.data = &(struct meson_clk_pll_data){
|
.data = &(struct meson_clk_pll_data){
|
||||||
.en = {
|
.en = {
|
||||||
|
@ -2715,7 +2706,6 @@ static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
|
||||||
|
|
||||||
static struct clk_hw_onecell_data meson8_hw_onecell_data = {
|
static struct clk_hw_onecell_data meson8_hw_onecell_data = {
|
||||||
.hws = {
|
.hws = {
|
||||||
[CLKID_XTAL] = &meson8b_xtal.hw,
|
|
||||||
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
|
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
|
||||||
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
|
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
|
||||||
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
|
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
|
||||||
|
@ -2922,7 +2912,6 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = {
|
||||||
|
|
||||||
static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
|
static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
|
||||||
.hws = {
|
.hws = {
|
||||||
[CLKID_XTAL] = &meson8b_xtal.hw,
|
|
||||||
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
|
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
|
||||||
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
|
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
|
||||||
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
|
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
|
||||||
|
@ -3140,7 +3129,6 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
|
||||||
|
|
||||||
static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
|
static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
|
||||||
.hws = {
|
.hws = {
|
||||||
[CLKID_XTAL] = &meson8b_xtal.hw,
|
|
||||||
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
|
[CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
|
||||||
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
|
[CLKID_PLL_VID] = &meson8b_vid_pll.hw,
|
||||||
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
|
[CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
|
||||||
|
@ -3725,35 +3713,18 @@ static struct meson8b_nb_data meson8b_cpu_nb_data = {
|
||||||
.nb.notifier_call = meson8b_cpu_clk_notifier_cb,
|
.nb.notifier_call = meson8b_cpu_clk_notifier_cb,
|
||||||
};
|
};
|
||||||
|
|
||||||
static const struct regmap_config clkc_regmap_config = {
|
|
||||||
.reg_bits = 32,
|
|
||||||
.val_bits = 32,
|
|
||||||
.reg_stride = 4,
|
|
||||||
};
|
|
||||||
|
|
||||||
static void __init meson8b_clkc_init_common(struct device_node *np,
|
static void __init meson8b_clkc_init_common(struct device_node *np,
|
||||||
struct clk_hw_onecell_data *clk_hw_onecell_data)
|
struct clk_hw_onecell_data *clk_hw_onecell_data)
|
||||||
{
|
{
|
||||||
struct meson8b_clk_reset *rstc;
|
struct meson8b_clk_reset *rstc;
|
||||||
const char *notifier_clk_name;
|
const char *notifier_clk_name;
|
||||||
struct clk *notifier_clk;
|
struct clk *notifier_clk;
|
||||||
void __iomem *clk_base;
|
|
||||||
struct regmap *map;
|
struct regmap *map;
|
||||||
int i, ret;
|
int i, ret;
|
||||||
|
|
||||||
map = syscon_node_to_regmap(of_get_parent(np));
|
map = syscon_node_to_regmap(of_get_parent(np));
|
||||||
if (IS_ERR(map)) {
|
if (IS_ERR(map)) {
|
||||||
pr_info("failed to get HHI regmap - Trying obsolete regs\n");
|
pr_err("failed to get HHI regmap - Trying obsolete regs\n");
|
||||||
|
|
||||||
/* Generic clocks, PLLs and some of the reset-bits */
|
|
||||||
clk_base = of_iomap(np, 1);
|
|
||||||
if (!clk_base) {
|
|
||||||
pr_err("%s: Unable to map clk base\n", __func__);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
map = regmap_init_mmio(NULL, clk_base, &clkc_regmap_config);
|
|
||||||
if (IS_ERR(map))
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -3778,16 +3749,10 @@ static void __init meson8b_clkc_init_common(struct device_node *np,
|
||||||
meson8b_clk_regmaps[i]->map = map;
|
meson8b_clk_regmaps[i]->map = map;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* always skip CLKID_UNUSED and also skip XTAL if the .dtb provides the
|
* register all clks and start with the first used ID (which is
|
||||||
* XTAL clock as input.
|
* CLKID_PLL_FIXED)
|
||||||
*/
|
*/
|
||||||
if (!IS_ERR(of_clk_get_by_name(np, "xtal")))
|
for (i = CLKID_PLL_FIXED; i < CLK_NR_CLKS; i++) {
|
||||||
i = CLKID_PLL_FIXED;
|
|
||||||
else
|
|
||||||
i = CLKID_XTAL;
|
|
||||||
|
|
||||||
/* register all clks */
|
|
||||||
for (; i < CLK_NR_CLKS; i++) {
|
|
||||||
/* array might be sparse */
|
/* array might be sparse */
|
||||||
if (!clk_hw_onecell_data->hws[i])
|
if (!clk_hw_onecell_data->hws[i])
|
||||||
continue;
|
continue;
|
||||||
|
|
Loading…
Reference in a new issue